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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
0004  *
0005  * Copyright (C) STMicroelectronics SA 2017
0006  * Author:  Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
0007  */
0008 
0009 #include <linux/clk.h>
0010 #include <linux/kernel.h>
0011 #include <linux/mfd/syscon.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/of_device.h>
0015 #include <linux/of_net.h>
0016 #include <linux/phy.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pm_wakeirq.h>
0019 #include <linux/regmap.h>
0020 #include <linux/slab.h>
0021 #include <linux/stmmac.h>
0022 
0023 #include "stmmac_platform.h"
0024 
0025 #define SYSCFG_MCU_ETH_MASK     BIT(23)
0026 #define SYSCFG_MP1_ETH_MASK     GENMASK(23, 16)
0027 #define SYSCFG_PMCCLRR_OFFSET       0x40
0028 
0029 #define SYSCFG_PMCR_ETH_CLK_SEL     BIT(16)
0030 #define SYSCFG_PMCR_ETH_REF_CLK_SEL BIT(17)
0031 
0032 /* CLOCK feed to PHY*/
0033 #define ETH_CK_F_25M    25000000
0034 #define ETH_CK_F_50M    50000000
0035 #define ETH_CK_F_125M   125000000
0036 
0037 /*  Ethernet PHY interface selection in register SYSCFG Configuration
0038  *------------------------------------------
0039  * src   |BIT(23)| BIT(22)| BIT(21)|BIT(20)|
0040  *------------------------------------------
0041  * MII   |   0   |   0    |   0    |   1   |
0042  *------------------------------------------
0043  * GMII  |   0   |   0    |   0    |   0   |
0044  *------------------------------------------
0045  * RGMII |   0   |   0    |   1    |  n/a  |
0046  *------------------------------------------
0047  * RMII  |   1   |   0    |   0    |  n/a  |
0048  *------------------------------------------
0049  */
0050 #define SYSCFG_PMCR_ETH_SEL_MII     BIT(20)
0051 #define SYSCFG_PMCR_ETH_SEL_RGMII   BIT(21)
0052 #define SYSCFG_PMCR_ETH_SEL_RMII    BIT(23)
0053 #define SYSCFG_PMCR_ETH_SEL_GMII    0
0054 #define SYSCFG_MCU_ETH_SEL_MII      0
0055 #define SYSCFG_MCU_ETH_SEL_RMII     1
0056 
0057 /* STM32MP1 register definitions
0058  *
0059  * Below table summarizes the clock requirement and clock sources for
0060  * supported phy interface modes.
0061  * __________________________________________________________________________
0062  *|PHY_MODE | Normal | PHY wo crystal|   PHY wo crystal   |No 125Mhz from PHY|
0063  *|         |        |      25MHz    |        50MHz       |                  |
0064  * ---------------------------------------------------------------------------
0065  *|  MII    |    -   |     eth-ck    |        n/a     |   n/a        |
0066  *|         |        | st,ext-phyclk |                    |          |
0067  * ---------------------------------------------------------------------------
0068  *|  GMII   |    -   |     eth-ck    |        n/a     |   n/a        |
0069  *|         |        | st,ext-phyclk |                    |          |
0070  * ---------------------------------------------------------------------------
0071  *| RGMII   |    -   |     eth-ck    |        n/a     |      eth-ck      |
0072  *|         |        | st,ext-phyclk |                    | st,eth-clk-sel or|
0073  *|         |        |               |                    | st,ext-phyclk    |
0074  * ---------------------------------------------------------------------------
0075  *| RMII    |    -   |     eth-ck    |      eth-ck        |   n/a        |
0076  *|         |        | st,ext-phyclk | st,eth-ref-clk-sel |          |
0077  *|         |        |               | or st,ext-phyclk   |          |
0078  * ---------------------------------------------------------------------------
0079  *
0080  */
0081 
0082 struct stm32_dwmac {
0083     struct clk *clk_tx;
0084     struct clk *clk_rx;
0085     struct clk *clk_eth_ck;
0086     struct clk *clk_ethstp;
0087     struct clk *syscfg_clk;
0088     int ext_phyclk;
0089     int enable_eth_ck;
0090     int eth_clk_sel_reg;
0091     int eth_ref_clk_sel_reg;
0092     int irq_pwr_wakeup;
0093     u32 mode_reg;        /* MAC glue-logic mode register */
0094     struct regmap *regmap;
0095     u32 speed;
0096     const struct stm32_ops *ops;
0097     struct device *dev;
0098 };
0099 
0100 struct stm32_ops {
0101     int (*set_mode)(struct plat_stmmacenet_data *plat_dat);
0102     int (*clk_prepare)(struct stm32_dwmac *dwmac, bool prepare);
0103     int (*suspend)(struct stm32_dwmac *dwmac);
0104     void (*resume)(struct stm32_dwmac *dwmac);
0105     int (*parse_data)(struct stm32_dwmac *dwmac,
0106               struct device *dev);
0107     u32 syscfg_eth_mask;
0108 };
0109 
0110 static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat)
0111 {
0112     struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
0113     int ret;
0114 
0115     if (dwmac->ops->set_mode) {
0116         ret = dwmac->ops->set_mode(plat_dat);
0117         if (ret)
0118             return ret;
0119     }
0120 
0121     ret = clk_prepare_enable(dwmac->clk_tx);
0122     if (ret)
0123         return ret;
0124 
0125     if (!dwmac->dev->power.is_suspended) {
0126         ret = clk_prepare_enable(dwmac->clk_rx);
0127         if (ret) {
0128             clk_disable_unprepare(dwmac->clk_tx);
0129             return ret;
0130         }
0131     }
0132 
0133     if (dwmac->ops->clk_prepare) {
0134         ret = dwmac->ops->clk_prepare(dwmac, true);
0135         if (ret) {
0136             clk_disable_unprepare(dwmac->clk_rx);
0137             clk_disable_unprepare(dwmac->clk_tx);
0138         }
0139     }
0140 
0141     return ret;
0142 }
0143 
0144 static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
0145 {
0146     int ret = 0;
0147 
0148     if (prepare) {
0149         ret = clk_prepare_enable(dwmac->syscfg_clk);
0150         if (ret)
0151             return ret;
0152         if (dwmac->enable_eth_ck) {
0153             ret = clk_prepare_enable(dwmac->clk_eth_ck);
0154             if (ret) {
0155                 clk_disable_unprepare(dwmac->syscfg_clk);
0156                 return ret;
0157             }
0158         }
0159     } else {
0160         clk_disable_unprepare(dwmac->syscfg_clk);
0161         if (dwmac->enable_eth_ck)
0162             clk_disable_unprepare(dwmac->clk_eth_ck);
0163     }
0164     return ret;
0165 }
0166 
0167 static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
0168 {
0169     struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
0170     u32 reg = dwmac->mode_reg, clk_rate;
0171     int val;
0172 
0173     clk_rate = clk_get_rate(dwmac->clk_eth_ck);
0174     dwmac->enable_eth_ck = false;
0175     switch (plat_dat->interface) {
0176     case PHY_INTERFACE_MODE_MII:
0177         if (clk_rate == ETH_CK_F_25M && dwmac->ext_phyclk)
0178             dwmac->enable_eth_ck = true;
0179         val = SYSCFG_PMCR_ETH_SEL_MII;
0180         pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
0181         break;
0182     case PHY_INTERFACE_MODE_GMII:
0183         val = SYSCFG_PMCR_ETH_SEL_GMII;
0184         if (clk_rate == ETH_CK_F_25M &&
0185             (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
0186             dwmac->enable_eth_ck = true;
0187             val |= SYSCFG_PMCR_ETH_CLK_SEL;
0188         }
0189         pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
0190         break;
0191     case PHY_INTERFACE_MODE_RMII:
0192         val = SYSCFG_PMCR_ETH_SEL_RMII;
0193         if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) &&
0194             (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) {
0195             dwmac->enable_eth_ck = true;
0196             val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
0197         }
0198         pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
0199         break;
0200     case PHY_INTERFACE_MODE_RGMII:
0201     case PHY_INTERFACE_MODE_RGMII_ID:
0202     case PHY_INTERFACE_MODE_RGMII_RXID:
0203     case PHY_INTERFACE_MODE_RGMII_TXID:
0204         val = SYSCFG_PMCR_ETH_SEL_RGMII;
0205         if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) &&
0206             (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
0207             dwmac->enable_eth_ck = true;
0208             val |= SYSCFG_PMCR_ETH_CLK_SEL;
0209         }
0210         pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
0211         break;
0212     default:
0213         pr_debug("SYSCFG init :  Do not manage %d interface\n",
0214              plat_dat->interface);
0215         /* Do not manage others interfaces */
0216         return -EINVAL;
0217     }
0218 
0219     /* Need to update PMCCLRR (clear register) */
0220     regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
0221              dwmac->ops->syscfg_eth_mask);
0222 
0223     /* Update PMCSETR (set register) */
0224     return regmap_update_bits(dwmac->regmap, reg,
0225                  dwmac->ops->syscfg_eth_mask, val);
0226 }
0227 
0228 static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
0229 {
0230     struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
0231     u32 reg = dwmac->mode_reg;
0232     int val;
0233 
0234     switch (plat_dat->interface) {
0235     case PHY_INTERFACE_MODE_MII:
0236         val = SYSCFG_MCU_ETH_SEL_MII;
0237         pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
0238         break;
0239     case PHY_INTERFACE_MODE_RMII:
0240         val = SYSCFG_MCU_ETH_SEL_RMII;
0241         pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
0242         break;
0243     default:
0244         pr_debug("SYSCFG init :  Do not manage %d interface\n",
0245              plat_dat->interface);
0246         /* Do not manage others interfaces */
0247         return -EINVAL;
0248     }
0249 
0250     return regmap_update_bits(dwmac->regmap, reg,
0251                  dwmac->ops->syscfg_eth_mask, val << 23);
0252 }
0253 
0254 static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac)
0255 {
0256     clk_disable_unprepare(dwmac->clk_tx);
0257     clk_disable_unprepare(dwmac->clk_rx);
0258 
0259     if (dwmac->ops->clk_prepare)
0260         dwmac->ops->clk_prepare(dwmac, false);
0261 }
0262 
0263 static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
0264                   struct device *dev)
0265 {
0266     struct device_node *np = dev->of_node;
0267     int err;
0268 
0269     /*  Get TX/RX clocks */
0270     dwmac->clk_tx = devm_clk_get(dev, "mac-clk-tx");
0271     if (IS_ERR(dwmac->clk_tx)) {
0272         dev_err(dev, "No ETH Tx clock provided...\n");
0273         return PTR_ERR(dwmac->clk_tx);
0274     }
0275 
0276     dwmac->clk_rx = devm_clk_get(dev, "mac-clk-rx");
0277     if (IS_ERR(dwmac->clk_rx)) {
0278         dev_err(dev, "No ETH Rx clock provided...\n");
0279         return PTR_ERR(dwmac->clk_rx);
0280     }
0281 
0282     if (dwmac->ops->parse_data) {
0283         err = dwmac->ops->parse_data(dwmac, dev);
0284         if (err)
0285             return err;
0286     }
0287 
0288     /* Get mode register */
0289     dwmac->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
0290     if (IS_ERR(dwmac->regmap))
0291         return PTR_ERR(dwmac->regmap);
0292 
0293     err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg);
0294     if (err)
0295         dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err);
0296 
0297     return err;
0298 }
0299 
0300 static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
0301                    struct device *dev)
0302 {
0303     struct platform_device *pdev = to_platform_device(dev);
0304     struct device_node *np = dev->of_node;
0305     int err = 0;
0306 
0307     /* Ethernet PHY have no crystal */
0308     dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
0309 
0310     /* Gigabit Ethernet 125MHz clock selection. */
0311     dwmac->eth_clk_sel_reg = of_property_read_bool(np, "st,eth-clk-sel");
0312 
0313     /* Ethernet 50Mhz RMII clock selection */
0314     dwmac->eth_ref_clk_sel_reg =
0315         of_property_read_bool(np, "st,eth-ref-clk-sel");
0316 
0317     /*  Get ETH_CLK clocks */
0318     dwmac->clk_eth_ck = devm_clk_get(dev, "eth-ck");
0319     if (IS_ERR(dwmac->clk_eth_ck)) {
0320         dev_info(dev, "No phy clock provided...\n");
0321         dwmac->clk_eth_ck = NULL;
0322     }
0323 
0324     /*  Clock used for low power mode */
0325     dwmac->clk_ethstp = devm_clk_get(dev, "ethstp");
0326     if (IS_ERR(dwmac->clk_ethstp)) {
0327         dev_err(dev,
0328             "No ETH peripheral clock provided for CStop mode ...\n");
0329         return PTR_ERR(dwmac->clk_ethstp);
0330     }
0331 
0332     /*  Optional Clock for sysconfig */
0333     dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk");
0334     if (IS_ERR(dwmac->syscfg_clk))
0335         dwmac->syscfg_clk = NULL;
0336 
0337     /* Get IRQ information early to have an ability to ask for deferred
0338      * probe if needed before we went too far with resource allocation.
0339      */
0340     dwmac->irq_pwr_wakeup = platform_get_irq_byname_optional(pdev,
0341                             "stm32_pwr_wakeup");
0342     if (dwmac->irq_pwr_wakeup == -EPROBE_DEFER)
0343         return -EPROBE_DEFER;
0344 
0345     if (!dwmac->clk_eth_ck && dwmac->irq_pwr_wakeup >= 0) {
0346         err = device_init_wakeup(&pdev->dev, true);
0347         if (err) {
0348             dev_err(&pdev->dev, "Failed to init wake up irq\n");
0349             return err;
0350         }
0351         err = dev_pm_set_dedicated_wake_irq(&pdev->dev,
0352                             dwmac->irq_pwr_wakeup);
0353         if (err) {
0354             dev_err(&pdev->dev, "Failed to set wake up irq\n");
0355             device_init_wakeup(&pdev->dev, false);
0356         }
0357         device_set_wakeup_enable(&pdev->dev, false);
0358     }
0359     return err;
0360 }
0361 
0362 static int stm32_dwmac_probe(struct platform_device *pdev)
0363 {
0364     struct plat_stmmacenet_data *plat_dat;
0365     struct stmmac_resources stmmac_res;
0366     struct stm32_dwmac *dwmac;
0367     const struct stm32_ops *data;
0368     int ret;
0369 
0370     ret = stmmac_get_platform_resources(pdev, &stmmac_res);
0371     if (ret)
0372         return ret;
0373 
0374     plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
0375     if (IS_ERR(plat_dat))
0376         return PTR_ERR(plat_dat);
0377 
0378     dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
0379     if (!dwmac) {
0380         ret = -ENOMEM;
0381         goto err_remove_config_dt;
0382     }
0383 
0384     data = of_device_get_match_data(&pdev->dev);
0385     if (!data) {
0386         dev_err(&pdev->dev, "no of match data provided\n");
0387         ret = -EINVAL;
0388         goto err_remove_config_dt;
0389     }
0390 
0391     dwmac->ops = data;
0392     dwmac->dev = &pdev->dev;
0393 
0394     ret = stm32_dwmac_parse_data(dwmac, &pdev->dev);
0395     if (ret) {
0396         dev_err(&pdev->dev, "Unable to parse OF data\n");
0397         goto err_remove_config_dt;
0398     }
0399 
0400     plat_dat->bsp_priv = dwmac;
0401 
0402     ret = stm32_dwmac_init(plat_dat);
0403     if (ret)
0404         goto err_remove_config_dt;
0405 
0406     ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
0407     if (ret)
0408         goto err_clk_disable;
0409 
0410     return 0;
0411 
0412 err_clk_disable:
0413     stm32_dwmac_clk_disable(dwmac);
0414 err_remove_config_dt:
0415     stmmac_remove_config_dt(pdev, plat_dat);
0416 
0417     return ret;
0418 }
0419 
0420 static int stm32_dwmac_remove(struct platform_device *pdev)
0421 {
0422     struct net_device *ndev = platform_get_drvdata(pdev);
0423     struct stmmac_priv *priv = netdev_priv(ndev);
0424     int ret = stmmac_dvr_remove(&pdev->dev);
0425     struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
0426 
0427     stm32_dwmac_clk_disable(priv->plat->bsp_priv);
0428 
0429     if (dwmac->irq_pwr_wakeup >= 0) {
0430         dev_pm_clear_wake_irq(&pdev->dev);
0431         device_init_wakeup(&pdev->dev, false);
0432     }
0433 
0434     return ret;
0435 }
0436 
0437 static int stm32mp1_suspend(struct stm32_dwmac *dwmac)
0438 {
0439     int ret = 0;
0440 
0441     ret = clk_prepare_enable(dwmac->clk_ethstp);
0442     if (ret)
0443         return ret;
0444 
0445     clk_disable_unprepare(dwmac->clk_tx);
0446     clk_disable_unprepare(dwmac->syscfg_clk);
0447     if (dwmac->enable_eth_ck)
0448         clk_disable_unprepare(dwmac->clk_eth_ck);
0449 
0450     return ret;
0451 }
0452 
0453 static void stm32mp1_resume(struct stm32_dwmac *dwmac)
0454 {
0455     clk_disable_unprepare(dwmac->clk_ethstp);
0456 }
0457 
0458 static int stm32mcu_suspend(struct stm32_dwmac *dwmac)
0459 {
0460     clk_disable_unprepare(dwmac->clk_tx);
0461     clk_disable_unprepare(dwmac->clk_rx);
0462 
0463     return 0;
0464 }
0465 
0466 #ifdef CONFIG_PM_SLEEP
0467 static int stm32_dwmac_suspend(struct device *dev)
0468 {
0469     struct net_device *ndev = dev_get_drvdata(dev);
0470     struct stmmac_priv *priv = netdev_priv(ndev);
0471     struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
0472 
0473     int ret;
0474 
0475     ret = stmmac_suspend(dev);
0476 
0477     if (dwmac->ops->suspend)
0478         ret = dwmac->ops->suspend(dwmac);
0479 
0480     return ret;
0481 }
0482 
0483 static int stm32_dwmac_resume(struct device *dev)
0484 {
0485     struct net_device *ndev = dev_get_drvdata(dev);
0486     struct stmmac_priv *priv = netdev_priv(ndev);
0487     struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
0488     int ret;
0489 
0490     if (dwmac->ops->resume)
0491         dwmac->ops->resume(dwmac);
0492 
0493     ret = stm32_dwmac_init(priv->plat);
0494     if (ret)
0495         return ret;
0496 
0497     ret = stmmac_resume(dev);
0498 
0499     return ret;
0500 }
0501 #endif /* CONFIG_PM_SLEEP */
0502 
0503 static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
0504     stm32_dwmac_suspend, stm32_dwmac_resume);
0505 
0506 static struct stm32_ops stm32mcu_dwmac_data = {
0507     .set_mode = stm32mcu_set_mode,
0508     .suspend = stm32mcu_suspend,
0509     .syscfg_eth_mask = SYSCFG_MCU_ETH_MASK
0510 };
0511 
0512 static struct stm32_ops stm32mp1_dwmac_data = {
0513     .set_mode = stm32mp1_set_mode,
0514     .clk_prepare = stm32mp1_clk_prepare,
0515     .suspend = stm32mp1_suspend,
0516     .resume = stm32mp1_resume,
0517     .parse_data = stm32mp1_parse_data,
0518     .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK
0519 };
0520 
0521 static const struct of_device_id stm32_dwmac_match[] = {
0522     { .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data},
0523     { .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data},
0524     { }
0525 };
0526 MODULE_DEVICE_TABLE(of, stm32_dwmac_match);
0527 
0528 static struct platform_driver stm32_dwmac_driver = {
0529     .probe  = stm32_dwmac_probe,
0530     .remove = stm32_dwmac_remove,
0531     .driver = {
0532         .name           = "stm32-dwmac",
0533         .pm     = &stm32_dwmac_pm_ops,
0534         .of_match_table = stm32_dwmac_match,
0535     },
0536 };
0537 module_platform_driver(stm32_dwmac_driver);
0538 
0539 MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@gmail.com>");
0540 MODULE_AUTHOR("Christophe Roullier <christophe.roullier@st.com>");
0541 MODULE_DESCRIPTION("STMicroelectronics STM32 DWMAC Specific Glue layer");
0542 MODULE_LICENSE("GPL v2");
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