Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /**
0003  * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
0004  *
0005  * Copyright (C) 2014 Chen-Zhi (Roger Chen)
0006  *
0007  * Chen-Zhi (Roger Chen)  <roger.chen@rock-chips.com>
0008  */
0009 
0010 #include <linux/stmmac.h>
0011 #include <linux/bitops.h>
0012 #include <linux/clk.h>
0013 #include <linux/phy.h>
0014 #include <linux/of_net.h>
0015 #include <linux/gpio.h>
0016 #include <linux/module.h>
0017 #include <linux/of_gpio.h>
0018 #include <linux/of_device.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/regulator/consumer.h>
0021 #include <linux/delay.h>
0022 #include <linux/mfd/syscon.h>
0023 #include <linux/regmap.h>
0024 #include <linux/pm_runtime.h>
0025 
0026 #include "stmmac_platform.h"
0027 
0028 struct rk_priv_data;
0029 struct rk_gmac_ops {
0030     void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
0031                  int tx_delay, int rx_delay);
0032     void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
0033     void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
0034     void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
0035     void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
0036     bool regs_valid;
0037     u32 regs[];
0038 };
0039 
0040 struct rk_priv_data {
0041     struct platform_device *pdev;
0042     phy_interface_t phy_iface;
0043     int id;
0044     struct regulator *regulator;
0045     bool suspended;
0046     const struct rk_gmac_ops *ops;
0047 
0048     bool clk_enabled;
0049     bool clock_input;
0050     bool integrated_phy;
0051 
0052     struct clk *clk_mac;
0053     struct clk *gmac_clkin;
0054     struct clk *mac_clk_rx;
0055     struct clk *mac_clk_tx;
0056     struct clk *clk_mac_ref;
0057     struct clk *clk_mac_refout;
0058     struct clk *clk_mac_speed;
0059     struct clk *aclk_mac;
0060     struct clk *pclk_mac;
0061     struct clk *clk_phy;
0062 
0063     struct reset_control *phy_reset;
0064 
0065     int tx_delay;
0066     int rx_delay;
0067 
0068     struct regmap *grf;
0069 };
0070 
0071 #define HIWORD_UPDATE(val, mask, shift) \
0072         ((val) << (shift) | (mask) << ((shift) + 16))
0073 
0074 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
0075 #define GRF_CLR_BIT(nr) (BIT(nr+16))
0076 
0077 #define DELAY_ENABLE(soc, tx, rx) \
0078     (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
0079      ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
0080 
0081 #define PX30_GRF_GMAC_CON1      0x0904
0082 
0083 /* PX30_GRF_GMAC_CON1 */
0084 #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
0085                      GRF_BIT(6))
0086 #define PX30_GMAC_SPEED_10M     GRF_CLR_BIT(2)
0087 #define PX30_GMAC_SPEED_100M        GRF_BIT(2)
0088 
0089 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
0090 {
0091     struct device *dev = &bsp_priv->pdev->dev;
0092 
0093     if (IS_ERR(bsp_priv->grf)) {
0094         dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
0095         return;
0096     }
0097 
0098     regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
0099              PX30_GMAC_PHY_INTF_SEL_RMII);
0100 }
0101 
0102 static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
0103 {
0104     struct device *dev = &bsp_priv->pdev->dev;
0105     int ret;
0106 
0107     if (IS_ERR(bsp_priv->clk_mac_speed)) {
0108         dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
0109         return;
0110     }
0111 
0112     if (speed == 10) {
0113         regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
0114                  PX30_GMAC_SPEED_10M);
0115 
0116         ret = clk_set_rate(bsp_priv->clk_mac_speed, 2500000);
0117         if (ret)
0118             dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
0119                 __func__, ret);
0120     } else if (speed == 100) {
0121         regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
0122                  PX30_GMAC_SPEED_100M);
0123 
0124         ret = clk_set_rate(bsp_priv->clk_mac_speed, 25000000);
0125         if (ret)
0126             dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
0127                 __func__, ret);
0128 
0129     } else {
0130         dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
0131     }
0132 }
0133 
0134 static const struct rk_gmac_ops px30_ops = {
0135     .set_to_rmii = px30_set_to_rmii,
0136     .set_rmii_speed = px30_set_rmii_speed,
0137 };
0138 
0139 #define RK3128_GRF_MAC_CON0 0x0168
0140 #define RK3128_GRF_MAC_CON1 0x016c
0141 
0142 /* RK3128_GRF_MAC_CON0 */
0143 #define RK3128_GMAC_TXCLK_DLY_ENABLE   GRF_BIT(14)
0144 #define RK3128_GMAC_TXCLK_DLY_DISABLE  GRF_CLR_BIT(14)
0145 #define RK3128_GMAC_RXCLK_DLY_ENABLE   GRF_BIT(15)
0146 #define RK3128_GMAC_RXCLK_DLY_DISABLE  GRF_CLR_BIT(15)
0147 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
0148 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
0149 
0150 /* RK3128_GRF_MAC_CON1 */
0151 #define RK3128_GMAC_PHY_INTF_SEL_RGMII  \
0152         (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
0153 #define RK3128_GMAC_PHY_INTF_SEL_RMII   \
0154         (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
0155 #define RK3128_GMAC_FLOW_CTRL          GRF_BIT(9)
0156 #define RK3128_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(9)
0157 #define RK3128_GMAC_SPEED_10M          GRF_CLR_BIT(10)
0158 #define RK3128_GMAC_SPEED_100M         GRF_BIT(10)
0159 #define RK3128_GMAC_RMII_CLK_25M       GRF_BIT(11)
0160 #define RK3128_GMAC_RMII_CLK_2_5M      GRF_CLR_BIT(11)
0161 #define RK3128_GMAC_CLK_125M           (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
0162 #define RK3128_GMAC_CLK_25M            (GRF_BIT(12) | GRF_BIT(13))
0163 #define RK3128_GMAC_CLK_2_5M           (GRF_CLR_BIT(12) | GRF_BIT(13))
0164 #define RK3128_GMAC_RMII_MODE          GRF_BIT(14)
0165 #define RK3128_GMAC_RMII_MODE_CLR      GRF_CLR_BIT(14)
0166 
0167 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
0168                 int tx_delay, int rx_delay)
0169 {
0170     struct device *dev = &bsp_priv->pdev->dev;
0171 
0172     if (IS_ERR(bsp_priv->grf)) {
0173         dev_err(dev, "Missing rockchip,grf property\n");
0174         return;
0175     }
0176 
0177     regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
0178              RK3128_GMAC_PHY_INTF_SEL_RGMII |
0179              RK3128_GMAC_RMII_MODE_CLR);
0180     regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
0181              DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
0182              RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
0183              RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
0184 }
0185 
0186 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
0187 {
0188     struct device *dev = &bsp_priv->pdev->dev;
0189 
0190     if (IS_ERR(bsp_priv->grf)) {
0191         dev_err(dev, "Missing rockchip,grf property\n");
0192         return;
0193     }
0194 
0195     regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
0196              RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
0197 }
0198 
0199 static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
0200 {
0201     struct device *dev = &bsp_priv->pdev->dev;
0202 
0203     if (IS_ERR(bsp_priv->grf)) {
0204         dev_err(dev, "Missing rockchip,grf property\n");
0205         return;
0206     }
0207 
0208     if (speed == 10)
0209         regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
0210                  RK3128_GMAC_CLK_2_5M);
0211     else if (speed == 100)
0212         regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
0213                  RK3128_GMAC_CLK_25M);
0214     else if (speed == 1000)
0215         regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
0216                  RK3128_GMAC_CLK_125M);
0217     else
0218         dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
0219 }
0220 
0221 static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
0222 {
0223     struct device *dev = &bsp_priv->pdev->dev;
0224 
0225     if (IS_ERR(bsp_priv->grf)) {
0226         dev_err(dev, "Missing rockchip,grf property\n");
0227         return;
0228     }
0229 
0230     if (speed == 10) {
0231         regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
0232                  RK3128_GMAC_RMII_CLK_2_5M |
0233                  RK3128_GMAC_SPEED_10M);
0234     } else if (speed == 100) {
0235         regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
0236                  RK3128_GMAC_RMII_CLK_25M |
0237                  RK3128_GMAC_SPEED_100M);
0238     } else {
0239         dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
0240     }
0241 }
0242 
0243 static const struct rk_gmac_ops rk3128_ops = {
0244     .set_to_rgmii = rk3128_set_to_rgmii,
0245     .set_to_rmii = rk3128_set_to_rmii,
0246     .set_rgmii_speed = rk3128_set_rgmii_speed,
0247     .set_rmii_speed = rk3128_set_rmii_speed,
0248 };
0249 
0250 #define RK3228_GRF_MAC_CON0 0x0900
0251 #define RK3228_GRF_MAC_CON1 0x0904
0252 
0253 #define RK3228_GRF_CON_MUX  0x50
0254 
0255 /* RK3228_GRF_MAC_CON0 */
0256 #define RK3228_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
0257 #define RK3228_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
0258 
0259 /* RK3228_GRF_MAC_CON1 */
0260 #define RK3228_GMAC_PHY_INTF_SEL_RGMII  \
0261         (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
0262 #define RK3228_GMAC_PHY_INTF_SEL_RMII   \
0263         (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
0264 #define RK3228_GMAC_FLOW_CTRL       GRF_BIT(3)
0265 #define RK3228_GMAC_FLOW_CTRL_CLR   GRF_CLR_BIT(3)
0266 #define RK3228_GMAC_SPEED_10M       GRF_CLR_BIT(2)
0267 #define RK3228_GMAC_SPEED_100M      GRF_BIT(2)
0268 #define RK3228_GMAC_RMII_CLK_25M    GRF_BIT(7)
0269 #define RK3228_GMAC_RMII_CLK_2_5M   GRF_CLR_BIT(7)
0270 #define RK3228_GMAC_CLK_125M        (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
0271 #define RK3228_GMAC_CLK_25M     (GRF_BIT(8) | GRF_BIT(9))
0272 #define RK3228_GMAC_CLK_2_5M        (GRF_CLR_BIT(8) | GRF_BIT(9))
0273 #define RK3228_GMAC_RMII_MODE       GRF_BIT(10)
0274 #define RK3228_GMAC_RMII_MODE_CLR   GRF_CLR_BIT(10)
0275 #define RK3228_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
0276 #define RK3228_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
0277 #define RK3228_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
0278 #define RK3228_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(1)
0279 
0280 /* RK3228_GRF_COM_MUX */
0281 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY  GRF_BIT(15)
0282 
0283 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
0284                 int tx_delay, int rx_delay)
0285 {
0286     struct device *dev = &bsp_priv->pdev->dev;
0287 
0288     if (IS_ERR(bsp_priv->grf)) {
0289         dev_err(dev, "Missing rockchip,grf property\n");
0290         return;
0291     }
0292 
0293     regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
0294              RK3228_GMAC_PHY_INTF_SEL_RGMII |
0295              RK3228_GMAC_RMII_MODE_CLR |
0296              DELAY_ENABLE(RK3228, tx_delay, rx_delay));
0297 
0298     regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
0299              RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
0300              RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
0301 }
0302 
0303 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
0304 {
0305     struct device *dev = &bsp_priv->pdev->dev;
0306 
0307     if (IS_ERR(bsp_priv->grf)) {
0308         dev_err(dev, "Missing rockchip,grf property\n");
0309         return;
0310     }
0311 
0312     regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
0313              RK3228_GMAC_PHY_INTF_SEL_RMII |
0314              RK3228_GMAC_RMII_MODE);
0315 
0316     /* set MAC to RMII mode */
0317     regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
0318 }
0319 
0320 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
0321 {
0322     struct device *dev = &bsp_priv->pdev->dev;
0323 
0324     if (IS_ERR(bsp_priv->grf)) {
0325         dev_err(dev, "Missing rockchip,grf property\n");
0326         return;
0327     }
0328 
0329     if (speed == 10)
0330         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
0331                  RK3228_GMAC_CLK_2_5M);
0332     else if (speed == 100)
0333         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
0334                  RK3228_GMAC_CLK_25M);
0335     else if (speed == 1000)
0336         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
0337                  RK3228_GMAC_CLK_125M);
0338     else
0339         dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
0340 }
0341 
0342 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
0343 {
0344     struct device *dev = &bsp_priv->pdev->dev;
0345 
0346     if (IS_ERR(bsp_priv->grf)) {
0347         dev_err(dev, "Missing rockchip,grf property\n");
0348         return;
0349     }
0350 
0351     if (speed == 10)
0352         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
0353                  RK3228_GMAC_RMII_CLK_2_5M |
0354                  RK3228_GMAC_SPEED_10M);
0355     else if (speed == 100)
0356         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
0357                  RK3228_GMAC_RMII_CLK_25M |
0358                  RK3228_GMAC_SPEED_100M);
0359     else
0360         dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
0361 }
0362 
0363 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
0364 {
0365     regmap_write(priv->grf, RK3228_GRF_CON_MUX,
0366              RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
0367 }
0368 
0369 static const struct rk_gmac_ops rk3228_ops = {
0370     .set_to_rgmii = rk3228_set_to_rgmii,
0371     .set_to_rmii = rk3228_set_to_rmii,
0372     .set_rgmii_speed = rk3228_set_rgmii_speed,
0373     .set_rmii_speed = rk3228_set_rmii_speed,
0374     .integrated_phy_powerup =  rk3228_integrated_phy_powerup,
0375 };
0376 
0377 #define RK3288_GRF_SOC_CON1 0x0248
0378 #define RK3288_GRF_SOC_CON3 0x0250
0379 
0380 /*RK3288_GRF_SOC_CON1*/
0381 #define RK3288_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(6) | GRF_CLR_BIT(7) | \
0382                      GRF_CLR_BIT(8))
0383 #define RK3288_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
0384                      GRF_BIT(8))
0385 #define RK3288_GMAC_FLOW_CTRL       GRF_BIT(9)
0386 #define RK3288_GMAC_FLOW_CTRL_CLR   GRF_CLR_BIT(9)
0387 #define RK3288_GMAC_SPEED_10M       GRF_CLR_BIT(10)
0388 #define RK3288_GMAC_SPEED_100M      GRF_BIT(10)
0389 #define RK3288_GMAC_RMII_CLK_25M    GRF_BIT(11)
0390 #define RK3288_GMAC_RMII_CLK_2_5M   GRF_CLR_BIT(11)
0391 #define RK3288_GMAC_CLK_125M        (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
0392 #define RK3288_GMAC_CLK_25M     (GRF_BIT(12) | GRF_BIT(13))
0393 #define RK3288_GMAC_CLK_2_5M        (GRF_CLR_BIT(12) | GRF_BIT(13))
0394 #define RK3288_GMAC_RMII_MODE       GRF_BIT(14)
0395 #define RK3288_GMAC_RMII_MODE_CLR   GRF_CLR_BIT(14)
0396 
0397 /*RK3288_GRF_SOC_CON3*/
0398 #define RK3288_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(14)
0399 #define RK3288_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(14)
0400 #define RK3288_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
0401 #define RK3288_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
0402 #define RK3288_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
0403 #define RK3288_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
0404 
0405 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
0406                 int tx_delay, int rx_delay)
0407 {
0408     struct device *dev = &bsp_priv->pdev->dev;
0409 
0410     if (IS_ERR(bsp_priv->grf)) {
0411         dev_err(dev, "Missing rockchip,grf property\n");
0412         return;
0413     }
0414 
0415     regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
0416              RK3288_GMAC_PHY_INTF_SEL_RGMII |
0417              RK3288_GMAC_RMII_MODE_CLR);
0418     regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
0419              DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
0420              RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
0421              RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
0422 }
0423 
0424 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
0425 {
0426     struct device *dev = &bsp_priv->pdev->dev;
0427 
0428     if (IS_ERR(bsp_priv->grf)) {
0429         dev_err(dev, "Missing rockchip,grf property\n");
0430         return;
0431     }
0432 
0433     regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
0434              RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
0435 }
0436 
0437 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
0438 {
0439     struct device *dev = &bsp_priv->pdev->dev;
0440 
0441     if (IS_ERR(bsp_priv->grf)) {
0442         dev_err(dev, "Missing rockchip,grf property\n");
0443         return;
0444     }
0445 
0446     if (speed == 10)
0447         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
0448                  RK3288_GMAC_CLK_2_5M);
0449     else if (speed == 100)
0450         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
0451                  RK3288_GMAC_CLK_25M);
0452     else if (speed == 1000)
0453         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
0454                  RK3288_GMAC_CLK_125M);
0455     else
0456         dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
0457 }
0458 
0459 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
0460 {
0461     struct device *dev = &bsp_priv->pdev->dev;
0462 
0463     if (IS_ERR(bsp_priv->grf)) {
0464         dev_err(dev, "Missing rockchip,grf property\n");
0465         return;
0466     }
0467 
0468     if (speed == 10) {
0469         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
0470                  RK3288_GMAC_RMII_CLK_2_5M |
0471                  RK3288_GMAC_SPEED_10M);
0472     } else if (speed == 100) {
0473         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
0474                  RK3288_GMAC_RMII_CLK_25M |
0475                  RK3288_GMAC_SPEED_100M);
0476     } else {
0477         dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
0478     }
0479 }
0480 
0481 static const struct rk_gmac_ops rk3288_ops = {
0482     .set_to_rgmii = rk3288_set_to_rgmii,
0483     .set_to_rmii = rk3288_set_to_rmii,
0484     .set_rgmii_speed = rk3288_set_rgmii_speed,
0485     .set_rmii_speed = rk3288_set_rmii_speed,
0486 };
0487 
0488 #define RK3308_GRF_MAC_CON0     0x04a0
0489 
0490 /* RK3308_GRF_MAC_CON0 */
0491 #define RK3308_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \
0492                     GRF_BIT(4))
0493 #define RK3308_GMAC_FLOW_CTRL       GRF_BIT(3)
0494 #define RK3308_GMAC_FLOW_CTRL_CLR   GRF_CLR_BIT(3)
0495 #define RK3308_GMAC_SPEED_10M       GRF_CLR_BIT(0)
0496 #define RK3308_GMAC_SPEED_100M      GRF_BIT(0)
0497 
0498 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
0499 {
0500     struct device *dev = &bsp_priv->pdev->dev;
0501 
0502     if (IS_ERR(bsp_priv->grf)) {
0503         dev_err(dev, "Missing rockchip,grf property\n");
0504         return;
0505     }
0506 
0507     regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
0508              RK3308_GMAC_PHY_INTF_SEL_RMII);
0509 }
0510 
0511 static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
0512 {
0513     struct device *dev = &bsp_priv->pdev->dev;
0514 
0515     if (IS_ERR(bsp_priv->grf)) {
0516         dev_err(dev, "Missing rockchip,grf property\n");
0517         return;
0518     }
0519 
0520     if (speed == 10) {
0521         regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
0522                  RK3308_GMAC_SPEED_10M);
0523     } else if (speed == 100) {
0524         regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
0525                  RK3308_GMAC_SPEED_100M);
0526     } else {
0527         dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
0528     }
0529 }
0530 
0531 static const struct rk_gmac_ops rk3308_ops = {
0532     .set_to_rmii = rk3308_set_to_rmii,
0533     .set_rmii_speed = rk3308_set_rmii_speed,
0534 };
0535 
0536 #define RK3328_GRF_MAC_CON0 0x0900
0537 #define RK3328_GRF_MAC_CON1 0x0904
0538 #define RK3328_GRF_MAC_CON2 0x0908
0539 #define RK3328_GRF_MACPHY_CON1  0xb04
0540 
0541 /* RK3328_GRF_MAC_CON0 */
0542 #define RK3328_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
0543 #define RK3328_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
0544 
0545 /* RK3328_GRF_MAC_CON1 */
0546 #define RK3328_GMAC_PHY_INTF_SEL_RGMII  \
0547         (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
0548 #define RK3328_GMAC_PHY_INTF_SEL_RMII   \
0549         (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
0550 #define RK3328_GMAC_FLOW_CTRL       GRF_BIT(3)
0551 #define RK3328_GMAC_FLOW_CTRL_CLR   GRF_CLR_BIT(3)
0552 #define RK3328_GMAC_SPEED_10M       GRF_CLR_BIT(2)
0553 #define RK3328_GMAC_SPEED_100M      GRF_BIT(2)
0554 #define RK3328_GMAC_RMII_CLK_25M    GRF_BIT(7)
0555 #define RK3328_GMAC_RMII_CLK_2_5M   GRF_CLR_BIT(7)
0556 #define RK3328_GMAC_CLK_125M        (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
0557 #define RK3328_GMAC_CLK_25M     (GRF_BIT(11) | GRF_BIT(12))
0558 #define RK3328_GMAC_CLK_2_5M        (GRF_CLR_BIT(11) | GRF_BIT(12))
0559 #define RK3328_GMAC_RMII_MODE       GRF_BIT(9)
0560 #define RK3328_GMAC_RMII_MODE_CLR   GRF_CLR_BIT(9)
0561 #define RK3328_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
0562 #define RK3328_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
0563 #define RK3328_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
0564 #define RK3328_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
0565 
0566 /* RK3328_GRF_MACPHY_CON1 */
0567 #define RK3328_MACPHY_RMII_MODE     GRF_BIT(9)
0568 
0569 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
0570                 int tx_delay, int rx_delay)
0571 {
0572     struct device *dev = &bsp_priv->pdev->dev;
0573 
0574     if (IS_ERR(bsp_priv->grf)) {
0575         dev_err(dev, "Missing rockchip,grf property\n");
0576         return;
0577     }
0578 
0579     regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
0580              RK3328_GMAC_PHY_INTF_SEL_RGMII |
0581              RK3328_GMAC_RMII_MODE_CLR |
0582              RK3328_GMAC_RXCLK_DLY_ENABLE |
0583              RK3328_GMAC_TXCLK_DLY_ENABLE);
0584 
0585     regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
0586              RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
0587              RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
0588 }
0589 
0590 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
0591 {
0592     struct device *dev = &bsp_priv->pdev->dev;
0593     unsigned int reg;
0594 
0595     if (IS_ERR(bsp_priv->grf)) {
0596         dev_err(dev, "Missing rockchip,grf property\n");
0597         return;
0598     }
0599 
0600     reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
0601           RK3328_GRF_MAC_CON1;
0602 
0603     regmap_write(bsp_priv->grf, reg,
0604              RK3328_GMAC_PHY_INTF_SEL_RMII |
0605              RK3328_GMAC_RMII_MODE);
0606 }
0607 
0608 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
0609 {
0610     struct device *dev = &bsp_priv->pdev->dev;
0611 
0612     if (IS_ERR(bsp_priv->grf)) {
0613         dev_err(dev, "Missing rockchip,grf property\n");
0614         return;
0615     }
0616 
0617     if (speed == 10)
0618         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
0619                  RK3328_GMAC_CLK_2_5M);
0620     else if (speed == 100)
0621         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
0622                  RK3328_GMAC_CLK_25M);
0623     else if (speed == 1000)
0624         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
0625                  RK3328_GMAC_CLK_125M);
0626     else
0627         dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
0628 }
0629 
0630 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
0631 {
0632     struct device *dev = &bsp_priv->pdev->dev;
0633     unsigned int reg;
0634 
0635     if (IS_ERR(bsp_priv->grf)) {
0636         dev_err(dev, "Missing rockchip,grf property\n");
0637         return;
0638     }
0639 
0640     reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
0641           RK3328_GRF_MAC_CON1;
0642 
0643     if (speed == 10)
0644         regmap_write(bsp_priv->grf, reg,
0645                  RK3328_GMAC_RMII_CLK_2_5M |
0646                  RK3328_GMAC_SPEED_10M);
0647     else if (speed == 100)
0648         regmap_write(bsp_priv->grf, reg,
0649                  RK3328_GMAC_RMII_CLK_25M |
0650                  RK3328_GMAC_SPEED_100M);
0651     else
0652         dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
0653 }
0654 
0655 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
0656 {
0657     regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
0658              RK3328_MACPHY_RMII_MODE);
0659 }
0660 
0661 static const struct rk_gmac_ops rk3328_ops = {
0662     .set_to_rgmii = rk3328_set_to_rgmii,
0663     .set_to_rmii = rk3328_set_to_rmii,
0664     .set_rgmii_speed = rk3328_set_rgmii_speed,
0665     .set_rmii_speed = rk3328_set_rmii_speed,
0666     .integrated_phy_powerup =  rk3328_integrated_phy_powerup,
0667 };
0668 
0669 #define RK3366_GRF_SOC_CON6 0x0418
0670 #define RK3366_GRF_SOC_CON7 0x041c
0671 
0672 /* RK3366_GRF_SOC_CON6 */
0673 #define RK3366_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
0674                      GRF_CLR_BIT(11))
0675 #define RK3366_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
0676                      GRF_BIT(11))
0677 #define RK3366_GMAC_FLOW_CTRL       GRF_BIT(8)
0678 #define RK3366_GMAC_FLOW_CTRL_CLR   GRF_CLR_BIT(8)
0679 #define RK3366_GMAC_SPEED_10M       GRF_CLR_BIT(7)
0680 #define RK3366_GMAC_SPEED_100M      GRF_BIT(7)
0681 #define RK3366_GMAC_RMII_CLK_25M    GRF_BIT(3)
0682 #define RK3366_GMAC_RMII_CLK_2_5M   GRF_CLR_BIT(3)
0683 #define RK3366_GMAC_CLK_125M        (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
0684 #define RK3366_GMAC_CLK_25M     (GRF_BIT(4) | GRF_BIT(5))
0685 #define RK3366_GMAC_CLK_2_5M        (GRF_CLR_BIT(4) | GRF_BIT(5))
0686 #define RK3366_GMAC_RMII_MODE       GRF_BIT(6)
0687 #define RK3366_GMAC_RMII_MODE_CLR   GRF_CLR_BIT(6)
0688 
0689 /* RK3366_GRF_SOC_CON7 */
0690 #define RK3366_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
0691 #define RK3366_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
0692 #define RK3366_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
0693 #define RK3366_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
0694 #define RK3366_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
0695 #define RK3366_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
0696 
0697 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
0698                 int tx_delay, int rx_delay)
0699 {
0700     struct device *dev = &bsp_priv->pdev->dev;
0701 
0702     if (IS_ERR(bsp_priv->grf)) {
0703         dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
0704         return;
0705     }
0706 
0707     regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
0708              RK3366_GMAC_PHY_INTF_SEL_RGMII |
0709              RK3366_GMAC_RMII_MODE_CLR);
0710     regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
0711              DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
0712              RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
0713              RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
0714 }
0715 
0716 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
0717 {
0718     struct device *dev = &bsp_priv->pdev->dev;
0719 
0720     if (IS_ERR(bsp_priv->grf)) {
0721         dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
0722         return;
0723     }
0724 
0725     regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
0726              RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
0727 }
0728 
0729 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
0730 {
0731     struct device *dev = &bsp_priv->pdev->dev;
0732 
0733     if (IS_ERR(bsp_priv->grf)) {
0734         dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
0735         return;
0736     }
0737 
0738     if (speed == 10)
0739         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
0740                  RK3366_GMAC_CLK_2_5M);
0741     else if (speed == 100)
0742         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
0743                  RK3366_GMAC_CLK_25M);
0744     else if (speed == 1000)
0745         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
0746                  RK3366_GMAC_CLK_125M);
0747     else
0748         dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
0749 }
0750 
0751 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
0752 {
0753     struct device *dev = &bsp_priv->pdev->dev;
0754 
0755     if (IS_ERR(bsp_priv->grf)) {
0756         dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
0757         return;
0758     }
0759 
0760     if (speed == 10) {
0761         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
0762                  RK3366_GMAC_RMII_CLK_2_5M |
0763                  RK3366_GMAC_SPEED_10M);
0764     } else if (speed == 100) {
0765         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
0766                  RK3366_GMAC_RMII_CLK_25M |
0767                  RK3366_GMAC_SPEED_100M);
0768     } else {
0769         dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
0770     }
0771 }
0772 
0773 static const struct rk_gmac_ops rk3366_ops = {
0774     .set_to_rgmii = rk3366_set_to_rgmii,
0775     .set_to_rmii = rk3366_set_to_rmii,
0776     .set_rgmii_speed = rk3366_set_rgmii_speed,
0777     .set_rmii_speed = rk3366_set_rmii_speed,
0778 };
0779 
0780 #define RK3368_GRF_SOC_CON15    0x043c
0781 #define RK3368_GRF_SOC_CON16    0x0440
0782 
0783 /* RK3368_GRF_SOC_CON15 */
0784 #define RK3368_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
0785                      GRF_CLR_BIT(11))
0786 #define RK3368_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
0787                      GRF_BIT(11))
0788 #define RK3368_GMAC_FLOW_CTRL       GRF_BIT(8)
0789 #define RK3368_GMAC_FLOW_CTRL_CLR   GRF_CLR_BIT(8)
0790 #define RK3368_GMAC_SPEED_10M       GRF_CLR_BIT(7)
0791 #define RK3368_GMAC_SPEED_100M      GRF_BIT(7)
0792 #define RK3368_GMAC_RMII_CLK_25M    GRF_BIT(3)
0793 #define RK3368_GMAC_RMII_CLK_2_5M   GRF_CLR_BIT(3)
0794 #define RK3368_GMAC_CLK_125M        (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
0795 #define RK3368_GMAC_CLK_25M     (GRF_BIT(4) | GRF_BIT(5))
0796 #define RK3368_GMAC_CLK_2_5M        (GRF_CLR_BIT(4) | GRF_BIT(5))
0797 #define RK3368_GMAC_RMII_MODE       GRF_BIT(6)
0798 #define RK3368_GMAC_RMII_MODE_CLR   GRF_CLR_BIT(6)
0799 
0800 /* RK3368_GRF_SOC_CON16 */
0801 #define RK3368_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
0802 #define RK3368_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
0803 #define RK3368_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
0804 #define RK3368_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
0805 #define RK3368_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
0806 #define RK3368_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
0807 
0808 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
0809                 int tx_delay, int rx_delay)
0810 {
0811     struct device *dev = &bsp_priv->pdev->dev;
0812 
0813     if (IS_ERR(bsp_priv->grf)) {
0814         dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
0815         return;
0816     }
0817 
0818     regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
0819              RK3368_GMAC_PHY_INTF_SEL_RGMII |
0820              RK3368_GMAC_RMII_MODE_CLR);
0821     regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
0822              DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
0823              RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
0824              RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
0825 }
0826 
0827 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
0828 {
0829     struct device *dev = &bsp_priv->pdev->dev;
0830 
0831     if (IS_ERR(bsp_priv->grf)) {
0832         dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
0833         return;
0834     }
0835 
0836     regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
0837              RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
0838 }
0839 
0840 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
0841 {
0842     struct device *dev = &bsp_priv->pdev->dev;
0843 
0844     if (IS_ERR(bsp_priv->grf)) {
0845         dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
0846         return;
0847     }
0848 
0849     if (speed == 10)
0850         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
0851                  RK3368_GMAC_CLK_2_5M);
0852     else if (speed == 100)
0853         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
0854                  RK3368_GMAC_CLK_25M);
0855     else if (speed == 1000)
0856         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
0857                  RK3368_GMAC_CLK_125M);
0858     else
0859         dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
0860 }
0861 
0862 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
0863 {
0864     struct device *dev = &bsp_priv->pdev->dev;
0865 
0866     if (IS_ERR(bsp_priv->grf)) {
0867         dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
0868         return;
0869     }
0870 
0871     if (speed == 10) {
0872         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
0873                  RK3368_GMAC_RMII_CLK_2_5M |
0874                  RK3368_GMAC_SPEED_10M);
0875     } else if (speed == 100) {
0876         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
0877                  RK3368_GMAC_RMII_CLK_25M |
0878                  RK3368_GMAC_SPEED_100M);
0879     } else {
0880         dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
0881     }
0882 }
0883 
0884 static const struct rk_gmac_ops rk3368_ops = {
0885     .set_to_rgmii = rk3368_set_to_rgmii,
0886     .set_to_rmii = rk3368_set_to_rmii,
0887     .set_rgmii_speed = rk3368_set_rgmii_speed,
0888     .set_rmii_speed = rk3368_set_rmii_speed,
0889 };
0890 
0891 #define RK3399_GRF_SOC_CON5 0xc214
0892 #define RK3399_GRF_SOC_CON6 0xc218
0893 
0894 /* RK3399_GRF_SOC_CON5 */
0895 #define RK3399_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
0896                      GRF_CLR_BIT(11))
0897 #define RK3399_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
0898                      GRF_BIT(11))
0899 #define RK3399_GMAC_FLOW_CTRL       GRF_BIT(8)
0900 #define RK3399_GMAC_FLOW_CTRL_CLR   GRF_CLR_BIT(8)
0901 #define RK3399_GMAC_SPEED_10M       GRF_CLR_BIT(7)
0902 #define RK3399_GMAC_SPEED_100M      GRF_BIT(7)
0903 #define RK3399_GMAC_RMII_CLK_25M    GRF_BIT(3)
0904 #define RK3399_GMAC_RMII_CLK_2_5M   GRF_CLR_BIT(3)
0905 #define RK3399_GMAC_CLK_125M        (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
0906 #define RK3399_GMAC_CLK_25M     (GRF_BIT(4) | GRF_BIT(5))
0907 #define RK3399_GMAC_CLK_2_5M        (GRF_CLR_BIT(4) | GRF_BIT(5))
0908 #define RK3399_GMAC_RMII_MODE       GRF_BIT(6)
0909 #define RK3399_GMAC_RMII_MODE_CLR   GRF_CLR_BIT(6)
0910 
0911 /* RK3399_GRF_SOC_CON6 */
0912 #define RK3399_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
0913 #define RK3399_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
0914 #define RK3399_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
0915 #define RK3399_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
0916 #define RK3399_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
0917 #define RK3399_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
0918 
0919 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
0920                 int tx_delay, int rx_delay)
0921 {
0922     struct device *dev = &bsp_priv->pdev->dev;
0923 
0924     if (IS_ERR(bsp_priv->grf)) {
0925         dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
0926         return;
0927     }
0928 
0929     regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
0930              RK3399_GMAC_PHY_INTF_SEL_RGMII |
0931              RK3399_GMAC_RMII_MODE_CLR);
0932     regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
0933              DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
0934              RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
0935              RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
0936 }
0937 
0938 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
0939 {
0940     struct device *dev = &bsp_priv->pdev->dev;
0941 
0942     if (IS_ERR(bsp_priv->grf)) {
0943         dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
0944         return;
0945     }
0946 
0947     regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
0948              RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
0949 }
0950 
0951 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
0952 {
0953     struct device *dev = &bsp_priv->pdev->dev;
0954 
0955     if (IS_ERR(bsp_priv->grf)) {
0956         dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
0957         return;
0958     }
0959 
0960     if (speed == 10)
0961         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
0962                  RK3399_GMAC_CLK_2_5M);
0963     else if (speed == 100)
0964         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
0965                  RK3399_GMAC_CLK_25M);
0966     else if (speed == 1000)
0967         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
0968                  RK3399_GMAC_CLK_125M);
0969     else
0970         dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
0971 }
0972 
0973 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
0974 {
0975     struct device *dev = &bsp_priv->pdev->dev;
0976 
0977     if (IS_ERR(bsp_priv->grf)) {
0978         dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
0979         return;
0980     }
0981 
0982     if (speed == 10) {
0983         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
0984                  RK3399_GMAC_RMII_CLK_2_5M |
0985                  RK3399_GMAC_SPEED_10M);
0986     } else if (speed == 100) {
0987         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
0988                  RK3399_GMAC_RMII_CLK_25M |
0989                  RK3399_GMAC_SPEED_100M);
0990     } else {
0991         dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
0992     }
0993 }
0994 
0995 static const struct rk_gmac_ops rk3399_ops = {
0996     .set_to_rgmii = rk3399_set_to_rgmii,
0997     .set_to_rmii = rk3399_set_to_rmii,
0998     .set_rgmii_speed = rk3399_set_rgmii_speed,
0999     .set_rmii_speed = rk3399_set_rmii_speed,
1000 };
1001 
1002 #define RK3568_GRF_GMAC0_CON0       0x0380
1003 #define RK3568_GRF_GMAC0_CON1       0x0384
1004 #define RK3568_GRF_GMAC1_CON0       0x0388
1005 #define RK3568_GRF_GMAC1_CON1       0x038c
1006 
1007 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
1008 #define RK3568_GMAC_PHY_INTF_SEL_RGMII  \
1009         (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
1010 #define RK3568_GMAC_PHY_INTF_SEL_RMII   \
1011         (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
1012 #define RK3568_GMAC_FLOW_CTRL           GRF_BIT(3)
1013 #define RK3568_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
1014 #define RK3568_GMAC_RXCLK_DLY_ENABLE        GRF_BIT(1)
1015 #define RK3568_GMAC_RXCLK_DLY_DISABLE       GRF_CLR_BIT(1)
1016 #define RK3568_GMAC_TXCLK_DLY_ENABLE        GRF_BIT(0)
1017 #define RK3568_GMAC_TXCLK_DLY_DISABLE       GRF_CLR_BIT(0)
1018 
1019 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
1020 #define RK3568_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
1021 #define RK3568_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
1022 
1023 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
1024                 int tx_delay, int rx_delay)
1025 {
1026     struct device *dev = &bsp_priv->pdev->dev;
1027     u32 con0, con1;
1028 
1029     if (IS_ERR(bsp_priv->grf)) {
1030         dev_err(dev, "Missing rockchip,grf property\n");
1031         return;
1032     }
1033 
1034     con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 :
1035                      RK3568_GRF_GMAC0_CON0;
1036     con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1037                      RK3568_GRF_GMAC0_CON1;
1038 
1039     regmap_write(bsp_priv->grf, con0,
1040              RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
1041              RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
1042 
1043     regmap_write(bsp_priv->grf, con1,
1044              RK3568_GMAC_PHY_INTF_SEL_RGMII |
1045              RK3568_GMAC_RXCLK_DLY_ENABLE |
1046              RK3568_GMAC_TXCLK_DLY_ENABLE);
1047 }
1048 
1049 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
1050 {
1051     struct device *dev = &bsp_priv->pdev->dev;
1052     u32 con1;
1053 
1054     if (IS_ERR(bsp_priv->grf)) {
1055         dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1056         return;
1057     }
1058 
1059     con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1060                      RK3568_GRF_GMAC0_CON1;
1061     regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
1062 }
1063 
1064 static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1065 {
1066     struct device *dev = &bsp_priv->pdev->dev;
1067     unsigned long rate;
1068     int ret;
1069 
1070     switch (speed) {
1071     case 10:
1072         rate = 2500000;
1073         break;
1074     case 100:
1075         rate = 25000000;
1076         break;
1077     case 1000:
1078         rate = 125000000;
1079         break;
1080     default:
1081         dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1082         return;
1083     }
1084 
1085     ret = clk_set_rate(bsp_priv->clk_mac_speed, rate);
1086     if (ret)
1087         dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1088             __func__, rate, ret);
1089 }
1090 
1091 static const struct rk_gmac_ops rk3568_ops = {
1092     .set_to_rgmii = rk3568_set_to_rgmii,
1093     .set_to_rmii = rk3568_set_to_rmii,
1094     .set_rgmii_speed = rk3568_set_gmac_speed,
1095     .set_rmii_speed = rk3568_set_gmac_speed,
1096     .regs_valid = true,
1097     .regs = {
1098         0xfe2a0000, /* gmac0 */
1099         0xfe010000, /* gmac1 */
1100         0x0, /* sentinel */
1101     },
1102 };
1103 
1104 #define RV1108_GRF_GMAC_CON0        0X0900
1105 
1106 /* RV1108_GRF_GMAC_CON0 */
1107 #define RV1108_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
1108                     GRF_BIT(6))
1109 #define RV1108_GMAC_FLOW_CTRL       GRF_BIT(3)
1110 #define RV1108_GMAC_FLOW_CTRL_CLR   GRF_CLR_BIT(3)
1111 #define RV1108_GMAC_SPEED_10M       GRF_CLR_BIT(2)
1112 #define RV1108_GMAC_SPEED_100M      GRF_BIT(2)
1113 #define RV1108_GMAC_RMII_CLK_25M    GRF_BIT(7)
1114 #define RV1108_GMAC_RMII_CLK_2_5M   GRF_CLR_BIT(7)
1115 
1116 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
1117 {
1118     struct device *dev = &bsp_priv->pdev->dev;
1119 
1120     if (IS_ERR(bsp_priv->grf)) {
1121         dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1122         return;
1123     }
1124 
1125     regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1126              RV1108_GMAC_PHY_INTF_SEL_RMII);
1127 }
1128 
1129 static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1130 {
1131     struct device *dev = &bsp_priv->pdev->dev;
1132 
1133     if (IS_ERR(bsp_priv->grf)) {
1134         dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1135         return;
1136     }
1137 
1138     if (speed == 10) {
1139         regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1140                  RV1108_GMAC_RMII_CLK_2_5M |
1141                  RV1108_GMAC_SPEED_10M);
1142     } else if (speed == 100) {
1143         regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1144                  RV1108_GMAC_RMII_CLK_25M |
1145                  RV1108_GMAC_SPEED_100M);
1146     } else {
1147         dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
1148     }
1149 }
1150 
1151 static const struct rk_gmac_ops rv1108_ops = {
1152     .set_to_rmii = rv1108_set_to_rmii,
1153     .set_rmii_speed = rv1108_set_rmii_speed,
1154 };
1155 
1156 #define RK_GRF_MACPHY_CON0      0xb00
1157 #define RK_GRF_MACPHY_CON1      0xb04
1158 #define RK_GRF_MACPHY_CON2      0xb08
1159 #define RK_GRF_MACPHY_CON3      0xb0c
1160 
1161 #define RK_MACPHY_ENABLE        GRF_BIT(0)
1162 #define RK_MACPHY_DISABLE       GRF_CLR_BIT(0)
1163 #define RK_MACPHY_CFG_CLK_50M       GRF_BIT(14)
1164 #define RK_GMAC2PHY_RMII_MODE       (GRF_BIT(6) | GRF_CLR_BIT(7))
1165 #define RK_GRF_CON2_MACPHY_ID       HIWORD_UPDATE(0x1234, 0xffff, 0)
1166 #define RK_GRF_CON3_MACPHY_ID       HIWORD_UPDATE(0x35, 0x3f, 0)
1167 
1168 static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
1169 {
1170     if (priv->ops->integrated_phy_powerup)
1171         priv->ops->integrated_phy_powerup(priv);
1172 
1173     regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
1174     regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
1175 
1176     regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
1177     regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
1178 
1179     if (priv->phy_reset) {
1180         /* PHY needs to be disabled before trying to reset it */
1181         regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1182         if (priv->phy_reset)
1183             reset_control_assert(priv->phy_reset);
1184         usleep_range(10, 20);
1185         if (priv->phy_reset)
1186             reset_control_deassert(priv->phy_reset);
1187         usleep_range(10, 20);
1188         regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
1189         msleep(30);
1190     }
1191 }
1192 
1193 static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
1194 {
1195     regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1196     if (priv->phy_reset)
1197         reset_control_assert(priv->phy_reset);
1198 }
1199 
1200 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
1201 {
1202     struct rk_priv_data *bsp_priv = plat->bsp_priv;
1203     struct device *dev = &bsp_priv->pdev->dev;
1204     int ret;
1205 
1206     bsp_priv->clk_enabled = false;
1207 
1208     bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
1209     if (IS_ERR(bsp_priv->mac_clk_rx))
1210         dev_err(dev, "cannot get clock %s\n",
1211             "mac_clk_rx");
1212 
1213     bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
1214     if (IS_ERR(bsp_priv->mac_clk_tx))
1215         dev_err(dev, "cannot get clock %s\n",
1216             "mac_clk_tx");
1217 
1218     bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
1219     if (IS_ERR(bsp_priv->aclk_mac))
1220         dev_err(dev, "cannot get clock %s\n",
1221             "aclk_mac");
1222 
1223     bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
1224     if (IS_ERR(bsp_priv->pclk_mac))
1225         dev_err(dev, "cannot get clock %s\n",
1226             "pclk_mac");
1227 
1228     bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
1229     if (IS_ERR(bsp_priv->clk_mac))
1230         dev_err(dev, "cannot get clock %s\n",
1231             "stmmaceth");
1232 
1233     if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
1234         bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
1235         if (IS_ERR(bsp_priv->clk_mac_ref))
1236             dev_err(dev, "cannot get clock %s\n",
1237                 "clk_mac_ref");
1238 
1239         if (!bsp_priv->clock_input) {
1240             bsp_priv->clk_mac_refout =
1241                 devm_clk_get(dev, "clk_mac_refout");
1242             if (IS_ERR(bsp_priv->clk_mac_refout))
1243                 dev_err(dev, "cannot get clock %s\n",
1244                     "clk_mac_refout");
1245         }
1246     }
1247 
1248     bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed");
1249     if (IS_ERR(bsp_priv->clk_mac_speed))
1250         dev_err(dev, "cannot get clock %s\n", "clk_mac_speed");
1251 
1252     if (bsp_priv->clock_input) {
1253         dev_info(dev, "clock input from PHY\n");
1254     } else {
1255         if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1256             clk_set_rate(bsp_priv->clk_mac, 50000000);
1257     }
1258 
1259     if (plat->phy_node && bsp_priv->integrated_phy) {
1260         bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
1261         if (IS_ERR(bsp_priv->clk_phy)) {
1262             ret = PTR_ERR(bsp_priv->clk_phy);
1263             dev_err(dev, "Cannot get PHY clock: %d\n", ret);
1264             return -EINVAL;
1265         }
1266         clk_set_rate(bsp_priv->clk_phy, 50000000);
1267     }
1268 
1269     return 0;
1270 }
1271 
1272 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
1273 {
1274     int phy_iface = bsp_priv->phy_iface;
1275 
1276     if (enable) {
1277         if (!bsp_priv->clk_enabled) {
1278             if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1279                 if (!IS_ERR(bsp_priv->mac_clk_rx))
1280                     clk_prepare_enable(
1281                         bsp_priv->mac_clk_rx);
1282 
1283                 if (!IS_ERR(bsp_priv->clk_mac_ref))
1284                     clk_prepare_enable(
1285                         bsp_priv->clk_mac_ref);
1286 
1287                 if (!IS_ERR(bsp_priv->clk_mac_refout))
1288                     clk_prepare_enable(
1289                         bsp_priv->clk_mac_refout);
1290             }
1291 
1292             if (!IS_ERR(bsp_priv->clk_phy))
1293                 clk_prepare_enable(bsp_priv->clk_phy);
1294 
1295             if (!IS_ERR(bsp_priv->aclk_mac))
1296                 clk_prepare_enable(bsp_priv->aclk_mac);
1297 
1298             if (!IS_ERR(bsp_priv->pclk_mac))
1299                 clk_prepare_enable(bsp_priv->pclk_mac);
1300 
1301             if (!IS_ERR(bsp_priv->mac_clk_tx))
1302                 clk_prepare_enable(bsp_priv->mac_clk_tx);
1303 
1304             if (!IS_ERR(bsp_priv->clk_mac_speed))
1305                 clk_prepare_enable(bsp_priv->clk_mac_speed);
1306 
1307             /**
1308              * if (!IS_ERR(bsp_priv->clk_mac))
1309              *  clk_prepare_enable(bsp_priv->clk_mac);
1310              */
1311             mdelay(5);
1312             bsp_priv->clk_enabled = true;
1313         }
1314     } else {
1315         if (bsp_priv->clk_enabled) {
1316             if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1317                 clk_disable_unprepare(bsp_priv->mac_clk_rx);
1318 
1319                 clk_disable_unprepare(bsp_priv->clk_mac_ref);
1320 
1321                 clk_disable_unprepare(bsp_priv->clk_mac_refout);
1322             }
1323 
1324             clk_disable_unprepare(bsp_priv->clk_phy);
1325 
1326             clk_disable_unprepare(bsp_priv->aclk_mac);
1327 
1328             clk_disable_unprepare(bsp_priv->pclk_mac);
1329 
1330             clk_disable_unprepare(bsp_priv->mac_clk_tx);
1331 
1332             clk_disable_unprepare(bsp_priv->clk_mac_speed);
1333             /**
1334              * if (!IS_ERR(bsp_priv->clk_mac))
1335              *  clk_disable_unprepare(bsp_priv->clk_mac);
1336              */
1337             bsp_priv->clk_enabled = false;
1338         }
1339     }
1340 
1341     return 0;
1342 }
1343 
1344 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
1345 {
1346     struct regulator *ldo = bsp_priv->regulator;
1347     int ret;
1348     struct device *dev = &bsp_priv->pdev->dev;
1349 
1350     if (!ldo)
1351         return 0;
1352 
1353     if (enable) {
1354         ret = regulator_enable(ldo);
1355         if (ret)
1356             dev_err(dev, "fail to enable phy-supply\n");
1357     } else {
1358         ret = regulator_disable(ldo);
1359         if (ret)
1360             dev_err(dev, "fail to disable phy-supply\n");
1361     }
1362 
1363     return 0;
1364 }
1365 
1366 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
1367                       struct plat_stmmacenet_data *plat,
1368                       const struct rk_gmac_ops *ops)
1369 {
1370     struct rk_priv_data *bsp_priv;
1371     struct device *dev = &pdev->dev;
1372     struct resource *res;
1373     int ret;
1374     const char *strings = NULL;
1375     int value;
1376 
1377     bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
1378     if (!bsp_priv)
1379         return ERR_PTR(-ENOMEM);
1380 
1381     of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface);
1382     bsp_priv->ops = ops;
1383 
1384     /* Some SoCs have multiple MAC controllers, which need
1385      * to be distinguished.
1386      */
1387     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1388     if (res && ops->regs_valid) {
1389         int i = 0;
1390 
1391         while (ops->regs[i]) {
1392             if (ops->regs[i] == res->start) {
1393                 bsp_priv->id = i;
1394                 break;
1395             }
1396             i++;
1397         }
1398     }
1399 
1400     bsp_priv->regulator = devm_regulator_get_optional(dev, "phy");
1401     if (IS_ERR(bsp_priv->regulator)) {
1402         if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) {
1403             dev_err(dev, "phy regulator is not available yet, deferred probing\n");
1404             return ERR_PTR(-EPROBE_DEFER);
1405         }
1406         dev_err(dev, "no regulator found\n");
1407         bsp_priv->regulator = NULL;
1408     }
1409 
1410     ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
1411     if (ret) {
1412         dev_err(dev, "Can not read property: clock_in_out.\n");
1413         bsp_priv->clock_input = true;
1414     } else {
1415         dev_info(dev, "clock input or output? (%s).\n",
1416              strings);
1417         if (!strcmp(strings, "input"))
1418             bsp_priv->clock_input = true;
1419         else
1420             bsp_priv->clock_input = false;
1421     }
1422 
1423     ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
1424     if (ret) {
1425         bsp_priv->tx_delay = 0x30;
1426         dev_err(dev, "Can not read property: tx_delay.");
1427         dev_err(dev, "set tx_delay to 0x%x\n",
1428             bsp_priv->tx_delay);
1429     } else {
1430         dev_info(dev, "TX delay(0x%x).\n", value);
1431         bsp_priv->tx_delay = value;
1432     }
1433 
1434     ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
1435     if (ret) {
1436         bsp_priv->rx_delay = 0x10;
1437         dev_err(dev, "Can not read property: rx_delay.");
1438         dev_err(dev, "set rx_delay to 0x%x\n",
1439             bsp_priv->rx_delay);
1440     } else {
1441         dev_info(dev, "RX delay(0x%x).\n", value);
1442         bsp_priv->rx_delay = value;
1443     }
1444 
1445     bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1446                             "rockchip,grf");
1447 
1448     if (plat->phy_node) {
1449         bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
1450                                  "phy-is-integrated");
1451         if (bsp_priv->integrated_phy) {
1452             bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
1453             if (IS_ERR(bsp_priv->phy_reset)) {
1454                 dev_err(&pdev->dev, "No PHY reset control found.\n");
1455                 bsp_priv->phy_reset = NULL;
1456             }
1457         }
1458     }
1459     dev_info(dev, "integrated PHY? (%s).\n",
1460          bsp_priv->integrated_phy ? "yes" : "no");
1461 
1462     bsp_priv->pdev = pdev;
1463 
1464     return bsp_priv;
1465 }
1466 
1467 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv)
1468 {
1469     switch (bsp_priv->phy_iface) {
1470     case PHY_INTERFACE_MODE_RGMII:
1471     case PHY_INTERFACE_MODE_RGMII_ID:
1472     case PHY_INTERFACE_MODE_RGMII_RXID:
1473     case PHY_INTERFACE_MODE_RGMII_TXID:
1474         if (!bsp_priv->ops->set_to_rgmii)
1475             return -EINVAL;
1476         break;
1477     case PHY_INTERFACE_MODE_RMII:
1478         if (!bsp_priv->ops->set_to_rmii)
1479             return -EINVAL;
1480         break;
1481     default:
1482         dev_err(&bsp_priv->pdev->dev,
1483             "unsupported interface %d", bsp_priv->phy_iface);
1484     }
1485     return 0;
1486 }
1487 
1488 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
1489 {
1490     int ret;
1491     struct device *dev = &bsp_priv->pdev->dev;
1492 
1493     ret = rk_gmac_check_ops(bsp_priv);
1494     if (ret)
1495         return ret;
1496 
1497     ret = gmac_clk_enable(bsp_priv, true);
1498     if (ret)
1499         return ret;
1500 
1501     /*rmii or rgmii*/
1502     switch (bsp_priv->phy_iface) {
1503     case PHY_INTERFACE_MODE_RGMII:
1504         dev_info(dev, "init for RGMII\n");
1505         bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
1506                         bsp_priv->rx_delay);
1507         break;
1508     case PHY_INTERFACE_MODE_RGMII_ID:
1509         dev_info(dev, "init for RGMII_ID\n");
1510         bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
1511         break;
1512     case PHY_INTERFACE_MODE_RGMII_RXID:
1513         dev_info(dev, "init for RGMII_RXID\n");
1514         bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
1515         break;
1516     case PHY_INTERFACE_MODE_RGMII_TXID:
1517         dev_info(dev, "init for RGMII_TXID\n");
1518         bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
1519         break;
1520     case PHY_INTERFACE_MODE_RMII:
1521         dev_info(dev, "init for RMII\n");
1522         bsp_priv->ops->set_to_rmii(bsp_priv);
1523         break;
1524     default:
1525         dev_err(dev, "NO interface defined!\n");
1526     }
1527 
1528     ret = phy_power_on(bsp_priv, true);
1529     if (ret) {
1530         gmac_clk_enable(bsp_priv, false);
1531         return ret;
1532     }
1533 
1534     pm_runtime_get_sync(dev);
1535 
1536     if (bsp_priv->integrated_phy)
1537         rk_gmac_integrated_phy_powerup(bsp_priv);
1538 
1539     return 0;
1540 }
1541 
1542 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
1543 {
1544     if (gmac->integrated_phy)
1545         rk_gmac_integrated_phy_powerdown(gmac);
1546 
1547     pm_runtime_put_sync(&gmac->pdev->dev);
1548 
1549     phy_power_on(gmac, false);
1550     gmac_clk_enable(gmac, false);
1551 }
1552 
1553 static void rk_fix_speed(void *priv, unsigned int speed)
1554 {
1555     struct rk_priv_data *bsp_priv = priv;
1556     struct device *dev = &bsp_priv->pdev->dev;
1557 
1558     switch (bsp_priv->phy_iface) {
1559     case PHY_INTERFACE_MODE_RGMII:
1560     case PHY_INTERFACE_MODE_RGMII_ID:
1561     case PHY_INTERFACE_MODE_RGMII_RXID:
1562     case PHY_INTERFACE_MODE_RGMII_TXID:
1563         if (bsp_priv->ops->set_rgmii_speed)
1564             bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
1565         break;
1566     case PHY_INTERFACE_MODE_RMII:
1567         if (bsp_priv->ops->set_rmii_speed)
1568             bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
1569         break;
1570     default:
1571         dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
1572     }
1573 }
1574 
1575 static int rk_gmac_probe(struct platform_device *pdev)
1576 {
1577     struct plat_stmmacenet_data *plat_dat;
1578     struct stmmac_resources stmmac_res;
1579     const struct rk_gmac_ops *data;
1580     int ret;
1581 
1582     data = of_device_get_match_data(&pdev->dev);
1583     if (!data) {
1584         dev_err(&pdev->dev, "no of match data provided\n");
1585         return -EINVAL;
1586     }
1587 
1588     ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1589     if (ret)
1590         return ret;
1591 
1592     plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
1593     if (IS_ERR(plat_dat))
1594         return PTR_ERR(plat_dat);
1595 
1596     /* If the stmmac is not already selected as gmac4,
1597      * then make sure we fallback to gmac.
1598      */
1599     if (!plat_dat->has_gmac4)
1600         plat_dat->has_gmac = true;
1601     plat_dat->fix_mac_speed = rk_fix_speed;
1602 
1603     plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
1604     if (IS_ERR(plat_dat->bsp_priv)) {
1605         ret = PTR_ERR(plat_dat->bsp_priv);
1606         goto err_remove_config_dt;
1607     }
1608 
1609     ret = rk_gmac_clk_init(plat_dat);
1610     if (ret)
1611         goto err_remove_config_dt;
1612 
1613     ret = rk_gmac_powerup(plat_dat->bsp_priv);
1614     if (ret)
1615         goto err_remove_config_dt;
1616 
1617     ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1618     if (ret)
1619         goto err_gmac_powerdown;
1620 
1621     return 0;
1622 
1623 err_gmac_powerdown:
1624     rk_gmac_powerdown(plat_dat->bsp_priv);
1625 err_remove_config_dt:
1626     stmmac_remove_config_dt(pdev, plat_dat);
1627 
1628     return ret;
1629 }
1630 
1631 static int rk_gmac_remove(struct platform_device *pdev)
1632 {
1633     struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev);
1634     int ret = stmmac_dvr_remove(&pdev->dev);
1635 
1636     rk_gmac_powerdown(bsp_priv);
1637 
1638     return ret;
1639 }
1640 
1641 #ifdef CONFIG_PM_SLEEP
1642 static int rk_gmac_suspend(struct device *dev)
1643 {
1644     struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1645     int ret = stmmac_suspend(dev);
1646 
1647     /* Keep the PHY up if we use Wake-on-Lan. */
1648     if (!device_may_wakeup(dev)) {
1649         rk_gmac_powerdown(bsp_priv);
1650         bsp_priv->suspended = true;
1651     }
1652 
1653     return ret;
1654 }
1655 
1656 static int rk_gmac_resume(struct device *dev)
1657 {
1658     struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1659 
1660     /* The PHY was up for Wake-on-Lan. */
1661     if (bsp_priv->suspended) {
1662         rk_gmac_powerup(bsp_priv);
1663         bsp_priv->suspended = false;
1664     }
1665 
1666     return stmmac_resume(dev);
1667 }
1668 #endif /* CONFIG_PM_SLEEP */
1669 
1670 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
1671 
1672 static const struct of_device_id rk_gmac_dwmac_match[] = {
1673     { .compatible = "rockchip,px30-gmac",   .data = &px30_ops   },
1674     { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
1675     { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
1676     { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
1677     { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops },
1678     { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
1679     { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
1680     { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
1681     { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
1682     { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
1683     { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
1684     { }
1685 };
1686 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
1687 
1688 static struct platform_driver rk_gmac_dwmac_driver = {
1689     .probe  = rk_gmac_probe,
1690     .remove = rk_gmac_remove,
1691     .driver = {
1692         .name           = "rk_gmac-dwmac",
1693         .pm     = &rk_gmac_pm_ops,
1694         .of_match_table = rk_gmac_dwmac_match,
1695     },
1696 };
1697 module_platform_driver(rk_gmac_dwmac_driver);
1698 
1699 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
1700 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
1701 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!