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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2018-19, Linaro Limited
0003 
0004 #include <linux/module.h>
0005 #include <linux/of.h>
0006 #include <linux/of_device.h>
0007 #include <linux/platform_device.h>
0008 #include <linux/phy.h>
0009 #include "stmmac.h"
0010 #include "stmmac_platform.h"
0011 
0012 #define RGMII_IO_MACRO_CONFIG       0x0
0013 #define SDCC_HC_REG_DLL_CONFIG      0x4
0014 #define SDCC_HC_REG_DDR_CONFIG      0xC
0015 #define SDCC_HC_REG_DLL_CONFIG2     0x10
0016 #define SDC4_STATUS         0x14
0017 #define SDCC_USR_CTL            0x18
0018 #define RGMII_IO_MACRO_CONFIG2      0x1C
0019 #define RGMII_IO_MACRO_DEBUG1       0x20
0020 #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28
0021 
0022 /* RGMII_IO_MACRO_CONFIG fields */
0023 #define RGMII_CONFIG_FUNC_CLK_EN        BIT(30)
0024 #define RGMII_CONFIG_POS_NEG_DATA_SEL       BIT(23)
0025 #define RGMII_CONFIG_GPIO_CFG_RX_INT        GENMASK(21, 20)
0026 #define RGMII_CONFIG_GPIO_CFG_TX_INT        GENMASK(19, 17)
0027 #define RGMII_CONFIG_MAX_SPD_PRG_9      GENMASK(16, 8)
0028 #define RGMII_CONFIG_MAX_SPD_PRG_2      GENMASK(7, 6)
0029 #define RGMII_CONFIG_INTF_SEL           GENMASK(5, 4)
0030 #define RGMII_CONFIG_BYPASS_TX_ID_EN        BIT(3)
0031 #define RGMII_CONFIG_LOOPBACK_EN        BIT(2)
0032 #define RGMII_CONFIG_PROG_SWAP          BIT(1)
0033 #define RGMII_CONFIG_DDR_MODE           BIT(0)
0034 
0035 /* SDCC_HC_REG_DLL_CONFIG fields */
0036 #define SDCC_DLL_CONFIG_DLL_RST         BIT(30)
0037 #define SDCC_DLL_CONFIG_PDN         BIT(29)
0038 #define SDCC_DLL_CONFIG_MCLK_FREQ       GENMASK(26, 24)
0039 #define SDCC_DLL_CONFIG_CDR_SELEXT      GENMASK(23, 20)
0040 #define SDCC_DLL_CONFIG_CDR_EXT_EN      BIT(19)
0041 #define SDCC_DLL_CONFIG_CK_OUT_EN       BIT(18)
0042 #define SDCC_DLL_CONFIG_CDR_EN          BIT(17)
0043 #define SDCC_DLL_CONFIG_DLL_EN          BIT(16)
0044 #define SDCC_DLL_MCLK_GATING_EN         BIT(5)
0045 #define SDCC_DLL_CDR_FINE_PHASE         GENMASK(3, 2)
0046 
0047 /* SDCC_HC_REG_DDR_CONFIG fields */
0048 #define SDCC_DDR_CONFIG_PRG_DLY_EN      BIT(31)
0049 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY    GENMASK(26, 21)
0050 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE   GENMASK(29, 27)
0051 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30)
0052 #define SDCC_DDR_CONFIG_PRG_RCLK_DLY        GENMASK(8, 0)
0053 
0054 /* SDCC_HC_REG_DLL_CONFIG2 fields */
0055 #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS      BIT(21)
0056 #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC     GENMASK(17, 10)
0057 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL   GENMASK(3, 2)
0058 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW    BIT(1)
0059 #define SDCC_DLL_CONFIG2_DDR_CAL_EN     BIT(0)
0060 
0061 /* SDC4_STATUS bits */
0062 #define SDC4_STATUS_DLL_LOCK            BIT(7)
0063 
0064 /* RGMII_IO_MACRO_CONFIG2 fields */
0065 #define RGMII_CONFIG2_RSVD_CONFIG15     GENMASK(31, 17)
0066 #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG     BIT(16)
0067 #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN  BIT(13)
0068 #define RGMII_CONFIG2_CLK_DIVIDE_SEL        BIT(12)
0069 #define RGMII_CONFIG2_RX_PROG_SWAP      BIT(7)
0070 #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL   BIT(6)
0071 #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5)
0072 
0073 struct ethqos_emac_por {
0074     unsigned int offset;
0075     unsigned int value;
0076 };
0077 
0078 struct ethqos_emac_driver_data {
0079     const struct ethqos_emac_por *por;
0080     unsigned int num_por;
0081     bool rgmii_config_looback_en;
0082 };
0083 
0084 struct qcom_ethqos {
0085     struct platform_device *pdev;
0086     void __iomem *rgmii_base;
0087 
0088     unsigned int rgmii_clk_rate;
0089     struct clk *rgmii_clk;
0090     unsigned int speed;
0091 
0092     const struct ethqos_emac_por *por;
0093     unsigned int num_por;
0094     bool rgmii_config_looback_en;
0095 };
0096 
0097 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
0098 {
0099     return readl(ethqos->rgmii_base + offset);
0100 }
0101 
0102 static void rgmii_writel(struct qcom_ethqos *ethqos,
0103              int value, unsigned int offset)
0104 {
0105     writel(value, ethqos->rgmii_base + offset);
0106 }
0107 
0108 static void rgmii_updatel(struct qcom_ethqos *ethqos,
0109               int mask, int val, unsigned int offset)
0110 {
0111     unsigned int temp;
0112 
0113     temp =  rgmii_readl(ethqos, offset);
0114     temp = (temp & ~(mask)) | val;
0115     rgmii_writel(ethqos, temp, offset);
0116 }
0117 
0118 static void rgmii_dump(void *priv)
0119 {
0120     struct qcom_ethqos *ethqos = priv;
0121 
0122     dev_dbg(&ethqos->pdev->dev, "Rgmii register dump\n");
0123     dev_dbg(&ethqos->pdev->dev, "RGMII_IO_MACRO_CONFIG: %x\n",
0124         rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG));
0125     dev_dbg(&ethqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG: %x\n",
0126         rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG));
0127     dev_dbg(&ethqos->pdev->dev, "SDCC_HC_REG_DDR_CONFIG: %x\n",
0128         rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG));
0129     dev_dbg(&ethqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n",
0130         rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2));
0131     dev_dbg(&ethqos->pdev->dev, "SDC4_STATUS: %x\n",
0132         rgmii_readl(ethqos, SDC4_STATUS));
0133     dev_dbg(&ethqos->pdev->dev, "SDCC_USR_CTL: %x\n",
0134         rgmii_readl(ethqos, SDCC_USR_CTL));
0135     dev_dbg(&ethqos->pdev->dev, "RGMII_IO_MACRO_CONFIG2: %x\n",
0136         rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2));
0137     dev_dbg(&ethqos->pdev->dev, "RGMII_IO_MACRO_DEBUG1: %x\n",
0138         rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1));
0139     dev_dbg(&ethqos->pdev->dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n",
0140         rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
0141 }
0142 
0143 /* Clock rates */
0144 #define RGMII_1000_NOM_CLK_FREQ         (250 * 1000 * 1000UL)
0145 #define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ   (50 * 1000 * 1000UL)
0146 #define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ     (5 * 1000 * 1000UL)
0147 
0148 static void
0149 ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed)
0150 {
0151     switch (speed) {
0152     case SPEED_1000:
0153         ethqos->rgmii_clk_rate =  RGMII_1000_NOM_CLK_FREQ;
0154         break;
0155 
0156     case SPEED_100:
0157         ethqos->rgmii_clk_rate =  RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
0158         break;
0159 
0160     case SPEED_10:
0161         ethqos->rgmii_clk_rate =  RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
0162         break;
0163     }
0164 
0165     clk_set_rate(ethqos->rgmii_clk, ethqos->rgmii_clk_rate);
0166 }
0167 
0168 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
0169 {
0170     rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN,
0171               RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);
0172 }
0173 
0174 static const struct ethqos_emac_por emac_v2_3_0_por[] = {
0175     { .offset = RGMII_IO_MACRO_CONFIG,  .value = 0x00C01343 },
0176     { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
0177     { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
0178     { .offset = SDCC_HC_REG_DLL_CONFIG2,    .value = 0x00200000 },
0179     { .offset = SDCC_USR_CTL,       .value = 0x00010800 },
0180     { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
0181 };
0182 
0183 static const struct ethqos_emac_driver_data emac_v2_3_0_data = {
0184     .por = emac_v2_3_0_por,
0185     .num_por = ARRAY_SIZE(emac_v2_3_0_por),
0186     .rgmii_config_looback_en = true,
0187 };
0188 
0189 static const struct ethqos_emac_por emac_v2_1_0_por[] = {
0190     { .offset = RGMII_IO_MACRO_CONFIG,  .value = 0x40C01343 },
0191     { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
0192     { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
0193     { .offset = SDCC_HC_REG_DLL_CONFIG2,    .value = 0x00200000 },
0194     { .offset = SDCC_USR_CTL,       .value = 0x00010800 },
0195     { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
0196 };
0197 
0198 static const struct ethqos_emac_driver_data emac_v2_1_0_data = {
0199     .por = emac_v2_1_0_por,
0200     .num_por = ARRAY_SIZE(emac_v2_1_0_por),
0201     .rgmii_config_looback_en = false,
0202 };
0203 
0204 static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
0205 {
0206     unsigned int val;
0207     int retry = 1000;
0208 
0209     /* Set CDR_EN */
0210     rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,
0211               SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG);
0212 
0213     /* Set CDR_EXT_EN */
0214     rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,
0215               SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG);
0216 
0217     /* Clear CK_OUT_EN */
0218     rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
0219               0, SDCC_HC_REG_DLL_CONFIG);
0220 
0221     /* Set DLL_EN */
0222     rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
0223               SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
0224 
0225     rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
0226               0, SDCC_HC_REG_DLL_CONFIG);
0227 
0228     rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
0229               0, SDCC_HC_REG_DLL_CONFIG);
0230 
0231     /* Wait for CK_OUT_EN clear */
0232     do {
0233         val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
0234         val &= SDCC_DLL_CONFIG_CK_OUT_EN;
0235         if (!val)
0236             break;
0237         mdelay(1);
0238         retry--;
0239     } while (retry > 0);
0240     if (!retry)
0241         dev_err(&ethqos->pdev->dev, "Clear CK_OUT_EN timedout\n");
0242 
0243     /* Set CK_OUT_EN */
0244     rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
0245               SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG);
0246 
0247     /* Wait for CK_OUT_EN set */
0248     retry = 1000;
0249     do {
0250         val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
0251         val &= SDCC_DLL_CONFIG_CK_OUT_EN;
0252         if (val)
0253             break;
0254         mdelay(1);
0255         retry--;
0256     } while (retry > 0);
0257     if (!retry)
0258         dev_err(&ethqos->pdev->dev, "Set CK_OUT_EN timedout\n");
0259 
0260     /* Set DDR_CAL_EN */
0261     rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
0262               SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);
0263 
0264     rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
0265               0, SDCC_HC_REG_DLL_CONFIG2);
0266 
0267     rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
0268               0x1A << 10, SDCC_HC_REG_DLL_CONFIG2);
0269 
0270     rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
0271               BIT(2), SDCC_HC_REG_DLL_CONFIG2);
0272 
0273     rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
0274               SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
0275               SDCC_HC_REG_DLL_CONFIG2);
0276 
0277     return 0;
0278 }
0279 
0280 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
0281 {
0282     /* Disable loopback mode */
0283     rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,
0284               0, RGMII_IO_MACRO_CONFIG2);
0285 
0286     /* Select RGMII, write 0 to interface select */
0287     rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL,
0288               0, RGMII_IO_MACRO_CONFIG);
0289 
0290     switch (ethqos->speed) {
0291     case SPEED_1000:
0292         rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
0293                   RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
0294         rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
0295                   0, RGMII_IO_MACRO_CONFIG);
0296         rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
0297                   RGMII_CONFIG_POS_NEG_DATA_SEL,
0298                   RGMII_IO_MACRO_CONFIG);
0299         rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
0300                   RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG);
0301         rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
0302                   0, RGMII_IO_MACRO_CONFIG2);
0303         rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
0304                   RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
0305                   RGMII_IO_MACRO_CONFIG2);
0306         rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
0307                   0, RGMII_IO_MACRO_CONFIG2);
0308         rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
0309                   RGMII_CONFIG2_RX_PROG_SWAP,
0310                   RGMII_IO_MACRO_CONFIG2);
0311 
0312         /* Set PRG_RCLK_DLY to 57 for 1.8 ns delay */
0313         rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
0314                   57, SDCC_HC_REG_DDR_CONFIG);
0315         rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
0316                   SDCC_DDR_CONFIG_PRG_DLY_EN,
0317                   SDCC_HC_REG_DDR_CONFIG);
0318         if (ethqos->rgmii_config_looback_en)
0319             rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
0320                       RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
0321         else
0322             rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
0323                       0, RGMII_IO_MACRO_CONFIG);
0324         break;
0325 
0326     case SPEED_100:
0327         rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
0328                   RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
0329         rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
0330                   RGMII_CONFIG_BYPASS_TX_ID_EN,
0331                   RGMII_IO_MACRO_CONFIG);
0332         rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
0333                   0, RGMII_IO_MACRO_CONFIG);
0334         rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
0335                   0, RGMII_IO_MACRO_CONFIG);
0336         rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
0337                   0, RGMII_IO_MACRO_CONFIG2);
0338         rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
0339                   RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
0340                   RGMII_IO_MACRO_CONFIG2);
0341         rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2,
0342                   BIT(6), RGMII_IO_MACRO_CONFIG);
0343         rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
0344                   0, RGMII_IO_MACRO_CONFIG2);
0345         rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
0346                   0, RGMII_IO_MACRO_CONFIG2);
0347         /* Write 0x5 to PRG_RCLK_DLY_CODE */
0348         rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
0349                   (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
0350         rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
0351                   SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
0352                   SDCC_HC_REG_DDR_CONFIG);
0353         rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
0354                   SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
0355                   SDCC_HC_REG_DDR_CONFIG);
0356         if (ethqos->rgmii_config_looback_en)
0357             rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
0358                       RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
0359         else
0360             rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
0361                       0, RGMII_IO_MACRO_CONFIG);
0362 
0363         break;
0364 
0365     case SPEED_10:
0366         rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
0367                   RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
0368         rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
0369                   RGMII_CONFIG_BYPASS_TX_ID_EN,
0370                   RGMII_IO_MACRO_CONFIG);
0371         rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
0372                   0, RGMII_IO_MACRO_CONFIG);
0373         rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
0374                   0, RGMII_IO_MACRO_CONFIG);
0375         rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
0376                   0, RGMII_IO_MACRO_CONFIG2);
0377         rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
0378                   0, RGMII_IO_MACRO_CONFIG2);
0379         rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,
0380                   BIT(12) | GENMASK(9, 8),
0381                   RGMII_IO_MACRO_CONFIG);
0382         rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
0383                   0, RGMII_IO_MACRO_CONFIG2);
0384         rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
0385                   0, RGMII_IO_MACRO_CONFIG2);
0386         /* Write 0x5 to PRG_RCLK_DLY_CODE */
0387         rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
0388                   (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
0389         rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
0390                   SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
0391                   SDCC_HC_REG_DDR_CONFIG);
0392         rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
0393                   SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
0394                   SDCC_HC_REG_DDR_CONFIG);
0395         rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
0396                   RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
0397         break;
0398     default:
0399         dev_err(&ethqos->pdev->dev,
0400             "Invalid speed %d\n", ethqos->speed);
0401         return -EINVAL;
0402     }
0403 
0404     return 0;
0405 }
0406 
0407 static int ethqos_configure(struct qcom_ethqos *ethqos)
0408 {
0409     volatile unsigned int dll_lock;
0410     unsigned int i, retry = 1000;
0411 
0412     /* Reset to POR values and enable clk */
0413     for (i = 0; i < ethqos->num_por; i++)
0414         rgmii_writel(ethqos, ethqos->por[i].value,
0415                  ethqos->por[i].offset);
0416     ethqos_set_func_clk_en(ethqos);
0417 
0418     /* Initialize the DLL first */
0419 
0420     /* Set DLL_RST */
0421     rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST,
0422               SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG);
0423 
0424     /* Set PDN */
0425     rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
0426               SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);
0427 
0428     /* Clear DLL_RST */
0429     rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0,
0430               SDCC_HC_REG_DLL_CONFIG);
0431 
0432     /* Clear PDN */
0433     rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0,
0434               SDCC_HC_REG_DLL_CONFIG);
0435 
0436     if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) {
0437         /* Set DLL_EN */
0438         rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
0439                   SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
0440 
0441         /* Set CK_OUT_EN */
0442         rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
0443                   SDCC_DLL_CONFIG_CK_OUT_EN,
0444                   SDCC_HC_REG_DLL_CONFIG);
0445 
0446         /* Set USR_CTL bit 26 with mask of 3 bits */
0447         rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), SDCC_USR_CTL);
0448 
0449         /* wait for DLL LOCK */
0450         do {
0451             mdelay(1);
0452             dll_lock = rgmii_readl(ethqos, SDC4_STATUS);
0453             if (dll_lock & SDC4_STATUS_DLL_LOCK)
0454                 break;
0455             retry--;
0456         } while (retry > 0);
0457         if (!retry)
0458             dev_err(&ethqos->pdev->dev,
0459                 "Timeout while waiting for DLL lock\n");
0460     }
0461 
0462     if (ethqos->speed == SPEED_1000)
0463         ethqos_dll_configure(ethqos);
0464 
0465     ethqos_rgmii_macro_init(ethqos);
0466 
0467     return 0;
0468 }
0469 
0470 static void ethqos_fix_mac_speed(void *priv, unsigned int speed)
0471 {
0472     struct qcom_ethqos *ethqos = priv;
0473 
0474     ethqos->speed = speed;
0475     ethqos_update_rgmii_clk(ethqos, speed);
0476     ethqos_configure(ethqos);
0477 }
0478 
0479 static int ethqos_clks_config(void *priv, bool enabled)
0480 {
0481     struct qcom_ethqos *ethqos = priv;
0482     int ret = 0;
0483 
0484     if (enabled) {
0485         ret = clk_prepare_enable(ethqos->rgmii_clk);
0486         if (ret) {
0487             dev_err(&ethqos->pdev->dev, "rgmii_clk enable failed\n");
0488             return ret;
0489         }
0490 
0491         /* Enable functional clock to prevent DMA reset to timeout due
0492          * to lacking PHY clock after the hardware block has been power
0493          * cycled. The actual configuration will be adjusted once
0494          * ethqos_fix_mac_speed() is invoked.
0495          */
0496         ethqos_set_func_clk_en(ethqos);
0497     } else {
0498         clk_disable_unprepare(ethqos->rgmii_clk);
0499     }
0500 
0501     return ret;
0502 }
0503 
0504 static int qcom_ethqos_probe(struct platform_device *pdev)
0505 {
0506     struct device_node *np = pdev->dev.of_node;
0507     struct plat_stmmacenet_data *plat_dat;
0508     struct stmmac_resources stmmac_res;
0509     const struct ethqos_emac_driver_data *data;
0510     struct qcom_ethqos *ethqos;
0511     int ret;
0512 
0513     ret = stmmac_get_platform_resources(pdev, &stmmac_res);
0514     if (ret)
0515         return ret;
0516 
0517     plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
0518     if (IS_ERR(plat_dat)) {
0519         dev_err(&pdev->dev, "dt configuration failed\n");
0520         return PTR_ERR(plat_dat);
0521     }
0522 
0523     plat_dat->clks_config = ethqos_clks_config;
0524 
0525     ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL);
0526     if (!ethqos) {
0527         ret = -ENOMEM;
0528         goto err_mem;
0529     }
0530 
0531     ethqos->pdev = pdev;
0532     ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii");
0533     if (IS_ERR(ethqos->rgmii_base)) {
0534         ret = PTR_ERR(ethqos->rgmii_base);
0535         goto err_mem;
0536     }
0537 
0538     data = of_device_get_match_data(&pdev->dev);
0539     ethqos->por = data->por;
0540     ethqos->num_por = data->num_por;
0541     ethqos->rgmii_config_looback_en = data->rgmii_config_looback_en;
0542 
0543     ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii");
0544     if (IS_ERR(ethqos->rgmii_clk)) {
0545         ret = PTR_ERR(ethqos->rgmii_clk);
0546         goto err_mem;
0547     }
0548 
0549     ret = ethqos_clks_config(ethqos, true);
0550     if (ret)
0551         goto err_mem;
0552 
0553     ethqos->speed = SPEED_1000;
0554     ethqos_update_rgmii_clk(ethqos, SPEED_1000);
0555     ethqos_set_func_clk_en(ethqos);
0556 
0557     plat_dat->bsp_priv = ethqos;
0558     plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
0559     plat_dat->dump_debug_regs = rgmii_dump;
0560     plat_dat->has_gmac4 = 1;
0561     plat_dat->pmt = 1;
0562     plat_dat->tso_en = of_property_read_bool(np, "snps,tso");
0563 
0564     ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
0565     if (ret)
0566         goto err_clk;
0567 
0568     return ret;
0569 
0570 err_clk:
0571     ethqos_clks_config(ethqos, false);
0572 
0573 err_mem:
0574     stmmac_remove_config_dt(pdev, plat_dat);
0575 
0576     return ret;
0577 }
0578 
0579 static int qcom_ethqos_remove(struct platform_device *pdev)
0580 {
0581     struct qcom_ethqos *ethqos;
0582     int ret;
0583 
0584     ethqos = get_stmmac_bsp_priv(&pdev->dev);
0585     if (!ethqos)
0586         return -ENODEV;
0587 
0588     ret = stmmac_pltfr_remove(pdev);
0589     ethqos_clks_config(ethqos, false);
0590 
0591     return ret;
0592 }
0593 
0594 static const struct of_device_id qcom_ethqos_match[] = {
0595     { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
0596     { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
0597     { }
0598 };
0599 MODULE_DEVICE_TABLE(of, qcom_ethqos_match);
0600 
0601 static struct platform_driver qcom_ethqos_driver = {
0602     .probe  = qcom_ethqos_probe,
0603     .remove = qcom_ethqos_remove,
0604     .driver = {
0605         .name           = "qcom-ethqos",
0606         .pm     = &stmmac_pltfr_pm_ops,
0607         .of_match_table = of_match_ptr(qcom_ethqos_match),
0608     },
0609 };
0610 module_platform_driver(qcom_ethqos_driver);
0611 
0612 MODULE_DESCRIPTION("Qualcomm ETHQOS driver");
0613 MODULE_LICENSE("GPL v2");
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