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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2018 MediaTek Inc.
0004  */
0005 #include <linux/bitfield.h>
0006 #include <linux/io.h>
0007 #include <linux/mfd/syscon.h>
0008 #include <linux/module.h>
0009 #include <linux/of.h>
0010 #include <linux/of_device.h>
0011 #include <linux/of_net.h>
0012 #include <linux/regmap.h>
0013 #include <linux/stmmac.h>
0014 
0015 #include "stmmac.h"
0016 #include "stmmac_platform.h"
0017 
0018 /* Peri Configuration register for mt2712 */
0019 #define PERI_ETH_PHY_INTF_SEL   0x418
0020 #define PHY_INTF_MII        0
0021 #define PHY_INTF_RGMII      1
0022 #define PHY_INTF_RMII       4
0023 #define RMII_CLK_SRC_RXC    BIT(4)
0024 #define RMII_CLK_SRC_INTERNAL   BIT(5)
0025 
0026 #define PERI_ETH_DLY    0x428
0027 #define ETH_DLY_GTXC_INV    BIT(6)
0028 #define ETH_DLY_GTXC_ENABLE BIT(5)
0029 #define ETH_DLY_GTXC_STAGES GENMASK(4, 0)
0030 #define ETH_DLY_TXC_INV     BIT(20)
0031 #define ETH_DLY_TXC_ENABLE  BIT(19)
0032 #define ETH_DLY_TXC_STAGES  GENMASK(18, 14)
0033 #define ETH_DLY_RXC_INV     BIT(13)
0034 #define ETH_DLY_RXC_ENABLE  BIT(12)
0035 #define ETH_DLY_RXC_STAGES  GENMASK(11, 7)
0036 
0037 #define PERI_ETH_DLY_FINE   0x800
0038 #define ETH_RMII_DLY_TX_INV BIT(2)
0039 #define ETH_FINE_DLY_GTXC   BIT(1)
0040 #define ETH_FINE_DLY_RXC    BIT(0)
0041 
0042 /* Peri Configuration register for mt8195 */
0043 #define MT8195_PERI_ETH_CTRL0       0xFD0
0044 #define MT8195_RMII_CLK_SRC_INTERNAL    BIT(28)
0045 #define MT8195_RMII_CLK_SRC_RXC     BIT(27)
0046 #define MT8195_ETH_INTF_SEL     GENMASK(26, 24)
0047 #define MT8195_RGMII_TXC_PHASE_CTRL BIT(22)
0048 #define MT8195_EXT_PHY_MODE     BIT(21)
0049 #define MT8195_DLY_GTXC_INV     BIT(12)
0050 #define MT8195_DLY_GTXC_ENABLE      BIT(5)
0051 #define MT8195_DLY_GTXC_STAGES      GENMASK(4, 0)
0052 
0053 #define MT8195_PERI_ETH_CTRL1       0xFD4
0054 #define MT8195_DLY_RXC_INV      BIT(25)
0055 #define MT8195_DLY_RXC_ENABLE       BIT(18)
0056 #define MT8195_DLY_RXC_STAGES       GENMASK(17, 13)
0057 #define MT8195_DLY_TXC_INV      BIT(12)
0058 #define MT8195_DLY_TXC_ENABLE       BIT(5)
0059 #define MT8195_DLY_TXC_STAGES       GENMASK(4, 0)
0060 
0061 #define MT8195_PERI_ETH_CTRL2       0xFD8
0062 #define MT8195_DLY_RMII_RXC_INV     BIT(25)
0063 #define MT8195_DLY_RMII_RXC_ENABLE  BIT(18)
0064 #define MT8195_DLY_RMII_RXC_STAGES  GENMASK(17, 13)
0065 #define MT8195_DLY_RMII_TXC_INV     BIT(12)
0066 #define MT8195_DLY_RMII_TXC_ENABLE  BIT(5)
0067 #define MT8195_DLY_RMII_TXC_STAGES  GENMASK(4, 0)
0068 
0069 struct mac_delay_struct {
0070     u32 tx_delay;
0071     u32 rx_delay;
0072     bool tx_inv;
0073     bool rx_inv;
0074 };
0075 
0076 struct mediatek_dwmac_plat_data {
0077     const struct mediatek_dwmac_variant *variant;
0078     struct mac_delay_struct mac_delay;
0079     struct clk *rmii_internal_clk;
0080     struct clk_bulk_data *clks;
0081     struct regmap *peri_regmap;
0082     struct device_node *np;
0083     struct device *dev;
0084     phy_interface_t phy_mode;
0085     bool rmii_clk_from_mac;
0086     bool rmii_rxc;
0087     bool mac_wol;
0088 };
0089 
0090 struct mediatek_dwmac_variant {
0091     int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat);
0092     int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat);
0093     void (*dwmac_fix_mac_speed)(void *priv, unsigned int speed);
0094 
0095     /* clock ids to be requested */
0096     const char * const *clk_list;
0097     int num_clks;
0098 
0099     u32 dma_bit_mask;
0100     u32 rx_delay_max;
0101     u32 tx_delay_max;
0102 };
0103 
0104 /* list of clocks required for mac */
0105 static const char * const mt2712_dwmac_clk_l[] = {
0106     "axi", "apb", "mac_main", "ptp_ref"
0107 };
0108 
0109 static const char * const mt8195_dwmac_clk_l[] = {
0110     "axi", "apb", "mac_cg", "mac_main", "ptp_ref"
0111 };
0112 
0113 static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat)
0114 {
0115     int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0;
0116     int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0;
0117     u32 intf_val = 0;
0118 
0119     /* select phy interface in top control domain */
0120     switch (plat->phy_mode) {
0121     case PHY_INTERFACE_MODE_MII:
0122         intf_val |= PHY_INTF_MII;
0123         break;
0124     case PHY_INTERFACE_MODE_RMII:
0125         intf_val |= (PHY_INTF_RMII | rmii_rxc | rmii_clk_from_mac);
0126         break;
0127     case PHY_INTERFACE_MODE_RGMII:
0128     case PHY_INTERFACE_MODE_RGMII_TXID:
0129     case PHY_INTERFACE_MODE_RGMII_RXID:
0130     case PHY_INTERFACE_MODE_RGMII_ID:
0131         intf_val |= PHY_INTF_RGMII;
0132         break;
0133     default:
0134         dev_err(plat->dev, "phy interface not supported\n");
0135         return -EINVAL;
0136     }
0137 
0138     regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val);
0139 
0140     return 0;
0141 }
0142 
0143 static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
0144 {
0145     struct mac_delay_struct *mac_delay = &plat->mac_delay;
0146 
0147     switch (plat->phy_mode) {
0148     case PHY_INTERFACE_MODE_MII:
0149     case PHY_INTERFACE_MODE_RMII:
0150         /* 550ps per stage for MII/RMII */
0151         mac_delay->tx_delay /= 550;
0152         mac_delay->rx_delay /= 550;
0153         break;
0154     case PHY_INTERFACE_MODE_RGMII:
0155     case PHY_INTERFACE_MODE_RGMII_TXID:
0156     case PHY_INTERFACE_MODE_RGMII_RXID:
0157     case PHY_INTERFACE_MODE_RGMII_ID:
0158         /* 170ps per stage for RGMII */
0159         mac_delay->tx_delay /= 170;
0160         mac_delay->rx_delay /= 170;
0161         break;
0162     default:
0163         dev_err(plat->dev, "phy interface not supported\n");
0164         break;
0165     }
0166 }
0167 
0168 static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
0169 {
0170     struct mac_delay_struct *mac_delay = &plat->mac_delay;
0171 
0172     switch (plat->phy_mode) {
0173     case PHY_INTERFACE_MODE_MII:
0174     case PHY_INTERFACE_MODE_RMII:
0175         /* 550ps per stage for MII/RMII */
0176         mac_delay->tx_delay *= 550;
0177         mac_delay->rx_delay *= 550;
0178         break;
0179     case PHY_INTERFACE_MODE_RGMII:
0180     case PHY_INTERFACE_MODE_RGMII_TXID:
0181     case PHY_INTERFACE_MODE_RGMII_RXID:
0182     case PHY_INTERFACE_MODE_RGMII_ID:
0183         /* 170ps per stage for RGMII */
0184         mac_delay->tx_delay *= 170;
0185         mac_delay->rx_delay *= 170;
0186         break;
0187     default:
0188         dev_err(plat->dev, "phy interface not supported\n");
0189         break;
0190     }
0191 }
0192 
0193 static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)
0194 {
0195     struct mac_delay_struct *mac_delay = &plat->mac_delay;
0196     u32 delay_val = 0, fine_val = 0;
0197 
0198     mt2712_delay_ps2stage(plat);
0199 
0200     switch (plat->phy_mode) {
0201     case PHY_INTERFACE_MODE_MII:
0202         delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->tx_delay);
0203         delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay);
0204         delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->tx_inv);
0205 
0206         delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
0207         delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
0208         delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
0209         break;
0210     case PHY_INTERFACE_MODE_RMII:
0211         if (plat->rmii_clk_from_mac) {
0212             /* case 1: mac provides the rmii reference clock,
0213              * and the clock output to TXC pin.
0214              * The egress timing can be adjusted by GTXC delay macro circuit.
0215              * The ingress timing can be adjusted by TXC delay macro circuit.
0216              */
0217             delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay);
0218             delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay);
0219             delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv);
0220 
0221             delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);
0222             delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay);
0223             delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv);
0224         } else {
0225             /* case 2: the rmii reference clock is from external phy,
0226              * and the property "rmii_rxc" indicates which pin(TXC/RXC)
0227              * the reference clk is connected to. The reference clock is a
0228              * received signal, so rx_delay/rx_inv are used to indicate
0229              * the reference clock timing adjustment
0230              */
0231             if (plat->rmii_rxc) {
0232                 /* the rmii reference clock from outside is connected
0233                  * to RXC pin, the reference clock will be adjusted
0234                  * by RXC delay macro circuit.
0235                  */
0236                 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
0237                 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
0238                 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
0239             } else {
0240                 /* the rmii reference clock from outside is connected
0241                  * to TXC pin, the reference clock will be adjusted
0242                  * by TXC delay macro circuit.
0243                  */
0244                 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay);
0245                 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay);
0246                 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv);
0247             }
0248             /* tx_inv will inverse the tx clock inside mac relateive to
0249              * reference clock from external phy,
0250              * and this bit is located in the same register with fine-tune
0251              */
0252             if (mac_delay->tx_inv)
0253                 fine_val = ETH_RMII_DLY_TX_INV;
0254         }
0255         break;
0256     case PHY_INTERFACE_MODE_RGMII:
0257     case PHY_INTERFACE_MODE_RGMII_TXID:
0258     case PHY_INTERFACE_MODE_RGMII_RXID:
0259     case PHY_INTERFACE_MODE_RGMII_ID:
0260         fine_val = ETH_FINE_DLY_GTXC | ETH_FINE_DLY_RXC;
0261 
0262         delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);
0263         delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay);
0264         delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv);
0265 
0266         delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
0267         delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
0268         delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
0269         break;
0270     default:
0271         dev_err(plat->dev, "phy interface not supported\n");
0272         return -EINVAL;
0273     }
0274     regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val);
0275     regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val);
0276 
0277     mt2712_delay_stage2ps(plat);
0278 
0279     return 0;
0280 }
0281 
0282 static const struct mediatek_dwmac_variant mt2712_gmac_variant = {
0283         .dwmac_set_phy_interface = mt2712_set_interface,
0284         .dwmac_set_delay = mt2712_set_delay,
0285         .clk_list = mt2712_dwmac_clk_l,
0286         .num_clks = ARRAY_SIZE(mt2712_dwmac_clk_l),
0287         .dma_bit_mask = 33,
0288         .rx_delay_max = 17600,
0289         .tx_delay_max = 17600,
0290 };
0291 
0292 static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat)
0293 {
0294     int rmii_clk_from_mac = plat->rmii_clk_from_mac ? MT8195_RMII_CLK_SRC_INTERNAL : 0;
0295     int rmii_rxc = plat->rmii_rxc ? MT8195_RMII_CLK_SRC_RXC : 0;
0296     u32 intf_val = 0;
0297 
0298     /* select phy interface in top control domain */
0299     switch (plat->phy_mode) {
0300     case PHY_INTERFACE_MODE_MII:
0301         intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_MII);
0302         break;
0303     case PHY_INTERFACE_MODE_RMII:
0304         intf_val |= (rmii_rxc | rmii_clk_from_mac);
0305         intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_RMII);
0306         break;
0307     case PHY_INTERFACE_MODE_RGMII:
0308     case PHY_INTERFACE_MODE_RGMII_TXID:
0309     case PHY_INTERFACE_MODE_RGMII_RXID:
0310     case PHY_INTERFACE_MODE_RGMII_ID:
0311         intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_RGMII);
0312         break;
0313     default:
0314         dev_err(plat->dev, "phy interface not supported\n");
0315         return -EINVAL;
0316     }
0317 
0318     /* MT8195 only support external PHY */
0319     intf_val |= MT8195_EXT_PHY_MODE;
0320 
0321     regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL0, intf_val);
0322 
0323     return 0;
0324 }
0325 
0326 static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
0327 {
0328     struct mac_delay_struct *mac_delay = &plat->mac_delay;
0329 
0330     /* 290ps per stage */
0331     mac_delay->tx_delay /= 290;
0332     mac_delay->rx_delay /= 290;
0333 }
0334 
0335 static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
0336 {
0337     struct mac_delay_struct *mac_delay = &plat->mac_delay;
0338 
0339     /* 290ps per stage */
0340     mac_delay->tx_delay *= 290;
0341     mac_delay->rx_delay *= 290;
0342 }
0343 
0344 static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat)
0345 {
0346     struct mac_delay_struct *mac_delay = &plat->mac_delay;
0347     u32 gtxc_delay_val = 0, delay_val = 0, rmii_delay_val = 0;
0348 
0349     mt8195_delay_ps2stage(plat);
0350 
0351     switch (plat->phy_mode) {
0352     case PHY_INTERFACE_MODE_MII:
0353         delay_val |= FIELD_PREP(MT8195_DLY_TXC_ENABLE, !!mac_delay->tx_delay);
0354         delay_val |= FIELD_PREP(MT8195_DLY_TXC_STAGES, mac_delay->tx_delay);
0355         delay_val |= FIELD_PREP(MT8195_DLY_TXC_INV, mac_delay->tx_inv);
0356 
0357         delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
0358         delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay);
0359         delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv);
0360         break;
0361     case PHY_INTERFACE_MODE_RMII:
0362         if (plat->rmii_clk_from_mac) {
0363             /* case 1: mac provides the rmii reference clock,
0364              * and the clock output to TXC pin.
0365              * The egress timing can be adjusted by RMII_TXC delay macro circuit.
0366              * The ingress timing can be adjusted by RMII_RXC delay macro circuit.
0367              */
0368             rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_TXC_ENABLE,
0369                              !!mac_delay->tx_delay);
0370             rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_TXC_STAGES,
0371                              mac_delay->tx_delay);
0372             rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_TXC_INV,
0373                              mac_delay->tx_inv);
0374 
0375             rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_RXC_ENABLE,
0376                              !!mac_delay->rx_delay);
0377             rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_RXC_STAGES,
0378                              mac_delay->rx_delay);
0379             rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_RXC_INV,
0380                              mac_delay->rx_inv);
0381         } else {
0382             /* case 2: the rmii reference clock is from external phy,
0383              * and the property "rmii_rxc" indicates which pin(TXC/RXC)
0384              * the reference clk is connected to. The reference clock is a
0385              * received signal, so rx_delay/rx_inv are used to indicate
0386              * the reference clock timing adjustment
0387              */
0388             if (plat->rmii_rxc) {
0389                 /* the rmii reference clock from outside is connected
0390                  * to RXC pin, the reference clock will be adjusted
0391                  * by RXC delay macro circuit.
0392                  */
0393                 delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE,
0394                             !!mac_delay->rx_delay);
0395                 delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES,
0396                             mac_delay->rx_delay);
0397                 delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV,
0398                             mac_delay->rx_inv);
0399             } else {
0400                 /* the rmii reference clock from outside is connected
0401                  * to TXC pin, the reference clock will be adjusted
0402                  * by TXC delay macro circuit.
0403                  */
0404                 delay_val |= FIELD_PREP(MT8195_DLY_TXC_ENABLE,
0405                             !!mac_delay->rx_delay);
0406                 delay_val |= FIELD_PREP(MT8195_DLY_TXC_STAGES,
0407                             mac_delay->rx_delay);
0408                 delay_val |= FIELD_PREP(MT8195_DLY_TXC_INV,
0409                             mac_delay->rx_inv);
0410             }
0411         }
0412         break;
0413     case PHY_INTERFACE_MODE_RGMII:
0414     case PHY_INTERFACE_MODE_RGMII_TXID:
0415     case PHY_INTERFACE_MODE_RGMII_RXID:
0416     case PHY_INTERFACE_MODE_RGMII_ID:
0417         gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);
0418         gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_STAGES, mac_delay->tx_delay);
0419         gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_INV, mac_delay->tx_inv);
0420 
0421         delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
0422         delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay);
0423         delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv);
0424 
0425         break;
0426     default:
0427         dev_err(plat->dev, "phy interface not supported\n");
0428         return -EINVAL;
0429     }
0430 
0431     regmap_update_bits(plat->peri_regmap,
0432                MT8195_PERI_ETH_CTRL0,
0433                MT8195_RGMII_TXC_PHASE_CTRL |
0434                MT8195_DLY_GTXC_INV |
0435                MT8195_DLY_GTXC_ENABLE |
0436                MT8195_DLY_GTXC_STAGES,
0437                gtxc_delay_val);
0438     regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL1, delay_val);
0439     regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val);
0440 
0441     mt8195_delay_stage2ps(plat);
0442 
0443     return 0;
0444 }
0445 
0446 static void mt8195_fix_mac_speed(void *priv, unsigned int speed)
0447 {
0448     struct mediatek_dwmac_plat_data *priv_plat = priv;
0449 
0450     if ((phy_interface_mode_is_rgmii(priv_plat->phy_mode))) {
0451         /* prefer 2ns fixed delay which is controlled by TXC_PHASE_CTRL,
0452          * when link speed is 1Gbps with RGMII interface,
0453          * Fall back to delay macro circuit for 10/100Mbps link speed.
0454          */
0455         if (speed == SPEED_1000)
0456             regmap_update_bits(priv_plat->peri_regmap,
0457                        MT8195_PERI_ETH_CTRL0,
0458                        MT8195_RGMII_TXC_PHASE_CTRL |
0459                        MT8195_DLY_GTXC_ENABLE |
0460                        MT8195_DLY_GTXC_INV |
0461                        MT8195_DLY_GTXC_STAGES,
0462                        MT8195_RGMII_TXC_PHASE_CTRL);
0463         else
0464             mt8195_set_delay(priv_plat);
0465     }
0466 }
0467 
0468 static const struct mediatek_dwmac_variant mt8195_gmac_variant = {
0469     .dwmac_set_phy_interface = mt8195_set_interface,
0470     .dwmac_set_delay = mt8195_set_delay,
0471     .dwmac_fix_mac_speed = mt8195_fix_mac_speed,
0472     .clk_list = mt8195_dwmac_clk_l,
0473     .num_clks = ARRAY_SIZE(mt8195_dwmac_clk_l),
0474     .dma_bit_mask = 35,
0475     .rx_delay_max = 9280,
0476     .tx_delay_max = 9280,
0477 };
0478 
0479 static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
0480 {
0481     struct mac_delay_struct *mac_delay = &plat->mac_delay;
0482     u32 tx_delay_ps, rx_delay_ps;
0483     int err;
0484 
0485     plat->peri_regmap = syscon_regmap_lookup_by_phandle(plat->np, "mediatek,pericfg");
0486     if (IS_ERR(plat->peri_regmap)) {
0487         dev_err(plat->dev, "Failed to get pericfg syscon\n");
0488         return PTR_ERR(plat->peri_regmap);
0489     }
0490 
0491     err = of_get_phy_mode(plat->np, &plat->phy_mode);
0492     if (err) {
0493         dev_err(plat->dev, "not find phy-mode\n");
0494         return err;
0495     }
0496 
0497     if (!of_property_read_u32(plat->np, "mediatek,tx-delay-ps", &tx_delay_ps)) {
0498         if (tx_delay_ps < plat->variant->tx_delay_max) {
0499             mac_delay->tx_delay = tx_delay_ps;
0500         } else {
0501             dev_err(plat->dev, "Invalid TX clock delay: %dps\n", tx_delay_ps);
0502             return -EINVAL;
0503         }
0504     }
0505 
0506     if (!of_property_read_u32(plat->np, "mediatek,rx-delay-ps", &rx_delay_ps)) {
0507         if (rx_delay_ps < plat->variant->rx_delay_max) {
0508             mac_delay->rx_delay = rx_delay_ps;
0509         } else {
0510             dev_err(plat->dev, "Invalid RX clock delay: %dps\n", rx_delay_ps);
0511             return -EINVAL;
0512         }
0513     }
0514 
0515     mac_delay->tx_inv = of_property_read_bool(plat->np, "mediatek,txc-inverse");
0516     mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse");
0517     plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc");
0518     plat->rmii_clk_from_mac = of_property_read_bool(plat->np, "mediatek,rmii-clk-from-mac");
0519     plat->mac_wol = of_property_read_bool(plat->np, "mediatek,mac-wol");
0520 
0521     return 0;
0522 }
0523 
0524 static int mediatek_dwmac_clk_init(struct mediatek_dwmac_plat_data *plat)
0525 {
0526     const struct mediatek_dwmac_variant *variant = plat->variant;
0527     int i, ret;
0528 
0529     plat->clks = devm_kcalloc(plat->dev, variant->num_clks, sizeof(*plat->clks), GFP_KERNEL);
0530     if (!plat->clks)
0531         return -ENOMEM;
0532 
0533     for (i = 0; i < variant->num_clks; i++)
0534         plat->clks[i].id = variant->clk_list[i];
0535 
0536     ret = devm_clk_bulk_get(plat->dev, variant->num_clks, plat->clks);
0537     if (ret)
0538         return ret;
0539 
0540     /* The clock labeled as "rmii_internal" is needed only in RMII(when
0541      * MAC provides the reference clock), and useless for RGMII/MII or
0542      * RMII(when PHY provides the reference clock).
0543      * So, "rmii_internal" clock is got and configured only when
0544      * reference clock of RMII is from MAC.
0545      */
0546     if (plat->rmii_clk_from_mac) {
0547         plat->rmii_internal_clk = devm_clk_get(plat->dev, "rmii_internal");
0548         if (IS_ERR(plat->rmii_internal_clk))
0549             ret = PTR_ERR(plat->rmii_internal_clk);
0550     } else {
0551         plat->rmii_internal_clk = NULL;
0552     }
0553 
0554     return ret;
0555 }
0556 
0557 static int mediatek_dwmac_init(struct platform_device *pdev, void *priv)
0558 {
0559     struct mediatek_dwmac_plat_data *plat = priv;
0560     const struct mediatek_dwmac_variant *variant = plat->variant;
0561     int ret;
0562 
0563     if (variant->dwmac_set_phy_interface) {
0564         ret = variant->dwmac_set_phy_interface(plat);
0565         if (ret) {
0566             dev_err(plat->dev, "failed to set phy interface, err = %d\n", ret);
0567             return ret;
0568         }
0569     }
0570 
0571     if (variant->dwmac_set_delay) {
0572         ret = variant->dwmac_set_delay(plat);
0573         if (ret) {
0574             dev_err(plat->dev, "failed to set delay value, err = %d\n", ret);
0575             return ret;
0576         }
0577     }
0578 
0579     return 0;
0580 }
0581 
0582 static int mediatek_dwmac_clks_config(void *priv, bool enabled)
0583 {
0584     struct mediatek_dwmac_plat_data *plat = priv;
0585     const struct mediatek_dwmac_variant *variant = plat->variant;
0586     int ret = 0;
0587 
0588     if (enabled) {
0589         ret = clk_bulk_prepare_enable(variant->num_clks, plat->clks);
0590         if (ret) {
0591             dev_err(plat->dev, "failed to enable clks, err = %d\n", ret);
0592             return ret;
0593         }
0594 
0595         ret = clk_prepare_enable(plat->rmii_internal_clk);
0596         if (ret) {
0597             dev_err(plat->dev, "failed to enable rmii internal clk, err = %d\n", ret);
0598             return ret;
0599         }
0600     } else {
0601         clk_disable_unprepare(plat->rmii_internal_clk);
0602         clk_bulk_disable_unprepare(variant->num_clks, plat->clks);
0603     }
0604 
0605     return ret;
0606 }
0607 
0608 static int mediatek_dwmac_common_data(struct platform_device *pdev,
0609                       struct plat_stmmacenet_data *plat,
0610                       struct mediatek_dwmac_plat_data *priv_plat)
0611 {
0612     int i;
0613 
0614     plat->interface = priv_plat->phy_mode;
0615     plat->use_phy_wol = priv_plat->mac_wol ? 0 : 1;
0616     plat->riwt_off = 1;
0617     plat->maxmtu = ETH_DATA_LEN;
0618     plat->addr64 = priv_plat->variant->dma_bit_mask;
0619     plat->bsp_priv = priv_plat;
0620     plat->init = mediatek_dwmac_init;
0621     plat->clks_config = mediatek_dwmac_clks_config;
0622     if (priv_plat->variant->dwmac_fix_mac_speed)
0623         plat->fix_mac_speed = priv_plat->variant->dwmac_fix_mac_speed;
0624 
0625     plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
0626                          sizeof(*plat->safety_feat_cfg),
0627                          GFP_KERNEL);
0628     if (!plat->safety_feat_cfg)
0629         return -ENOMEM;
0630 
0631     plat->safety_feat_cfg->tsoee = 1;
0632     plat->safety_feat_cfg->mrxpee = 0;
0633     plat->safety_feat_cfg->mestee = 1;
0634     plat->safety_feat_cfg->mrxee = 1;
0635     plat->safety_feat_cfg->mtxee = 1;
0636     plat->safety_feat_cfg->epsi = 0;
0637     plat->safety_feat_cfg->edpp = 1;
0638     plat->safety_feat_cfg->prtyen = 1;
0639     plat->safety_feat_cfg->tmouten = 1;
0640 
0641     for (i = 0; i < plat->tx_queues_to_use; i++) {
0642         /* Default TX Q0 to use TSO and rest TXQ for TBS */
0643         if (i > 0)
0644             plat->tx_queues_cfg[i].tbs_en = 1;
0645     }
0646 
0647     return 0;
0648 }
0649 
0650 static int mediatek_dwmac_probe(struct platform_device *pdev)
0651 {
0652     struct mediatek_dwmac_plat_data *priv_plat;
0653     struct plat_stmmacenet_data *plat_dat;
0654     struct stmmac_resources stmmac_res;
0655     int ret;
0656 
0657     priv_plat = devm_kzalloc(&pdev->dev, sizeof(*priv_plat), GFP_KERNEL);
0658     if (!priv_plat)
0659         return -ENOMEM;
0660 
0661     priv_plat->variant = of_device_get_match_data(&pdev->dev);
0662     if (!priv_plat->variant) {
0663         dev_err(&pdev->dev, "Missing dwmac-mediatek variant\n");
0664         return -EINVAL;
0665     }
0666 
0667     priv_plat->dev = &pdev->dev;
0668     priv_plat->np = pdev->dev.of_node;
0669 
0670     ret = mediatek_dwmac_config_dt(priv_plat);
0671     if (ret)
0672         return ret;
0673 
0674     ret = mediatek_dwmac_clk_init(priv_plat);
0675     if (ret)
0676         return ret;
0677 
0678     ret = stmmac_get_platform_resources(pdev, &stmmac_res);
0679     if (ret)
0680         return ret;
0681 
0682     plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
0683     if (IS_ERR(plat_dat))
0684         return PTR_ERR(plat_dat);
0685 
0686     mediatek_dwmac_common_data(pdev, plat_dat, priv_plat);
0687     mediatek_dwmac_init(pdev, priv_plat);
0688 
0689     ret = mediatek_dwmac_clks_config(priv_plat, true);
0690     if (ret)
0691         goto err_remove_config_dt;
0692 
0693     ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
0694     if (ret)
0695         goto err_drv_probe;
0696 
0697     return 0;
0698 
0699 err_drv_probe:
0700     mediatek_dwmac_clks_config(priv_plat, false);
0701 err_remove_config_dt:
0702     stmmac_remove_config_dt(pdev, plat_dat);
0703 
0704     return ret;
0705 }
0706 
0707 static int mediatek_dwmac_remove(struct platform_device *pdev)
0708 {
0709     struct mediatek_dwmac_plat_data *priv_plat = get_stmmac_bsp_priv(&pdev->dev);
0710     int ret;
0711 
0712     ret = stmmac_pltfr_remove(pdev);
0713     mediatek_dwmac_clks_config(priv_plat, false);
0714 
0715     return ret;
0716 }
0717 
0718 static const struct of_device_id mediatek_dwmac_match[] = {
0719     { .compatible = "mediatek,mt2712-gmac",
0720       .data = &mt2712_gmac_variant },
0721     { .compatible = "mediatek,mt8195-gmac",
0722       .data = &mt8195_gmac_variant },
0723     { }
0724 };
0725 
0726 MODULE_DEVICE_TABLE(of, mediatek_dwmac_match);
0727 
0728 static struct platform_driver mediatek_dwmac_driver = {
0729     .probe  = mediatek_dwmac_probe,
0730     .remove = mediatek_dwmac_remove,
0731     .driver = {
0732         .name           = "dwmac-mediatek",
0733         .pm     = &stmmac_pltfr_pm_ops,
0734         .of_match_table = mediatek_dwmac_match,
0735     },
0736 };
0737 module_platform_driver(mediatek_dwmac_driver);
0738 
0739 MODULE_AUTHOR("Biao Huang <biao.huang@mediatek.com>");
0740 MODULE_DESCRIPTION("MediaTek DWMAC specific glue layer");
0741 MODULE_LICENSE("GPL v2");
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