stmicro/stmmac/dwmac-ipq806x.c

0001 /*
0002  * Qualcomm Atheros IPQ806x GMAC glue layer
0003  *
0004  * Copyright (C) 2015 The Linux Foundation
0005  *
0006  * Permission to use, copy, modify, and/or distribute this software for any
0007  * purpose with or without fee is hereby granted, provided that the above
0008  * copyright notice and this permission notice appear in all copies.
0009  *
0010  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0011  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0012  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0013  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0014  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0015  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0016  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0017  */
0018
0019 #include <linux/device.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/phy.h>
0022 #include <linux/regmap.h>
0023 #include <linux/clk.h>
0024 #include <linux/reset.h>
0025 #include <linux/of_net.h>
0026 #include <linux/mfd/syscon.h>
0027 #include <linux/stmmac.h>
0028 #include <linux/of_mdio.h>
0029 #include <linux/module.h>
0030 #include <linux/sys_soc.h>
0031 #include <linux/bitfield.h>
0032
0033 #include "stmmac_platform.h"
0034
0035 #define NSS_COMMON_CLK_GATE         0x8
0036 #define NSS_COMMON_CLK_GATE_PTP_EN(x)       BIT(0x10 + x)
0037 #define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x)  BIT(0x9 + (x * 2))
0038 #define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x)  BIT(0x8 + (x * 2))
0039 #define NSS_COMMON_CLK_GATE_GMII_RX_EN(x)   BIT(0x4 + x)
0040 #define NSS_COMMON_CLK_GATE_GMII_TX_EN(x)   BIT(0x0 + x)
0041
0042 #define NSS_COMMON_CLK_DIV0         0xC
0043 #define NSS_COMMON_CLK_DIV_OFFSET(x)        (x * 8)
0044 #define NSS_COMMON_CLK_DIV_MASK         0x7f
0045
0046 #define NSS_COMMON_CLK_SRC_CTRL         0x14
0047 #define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x)   (x)
0048 /* Mode is coded on 1 bit but is different depending on the MAC ID:
0049  * MAC0: QSGMII=0 RGMII=1
0050  * MAC1: QSGMII=0 SGMII=0 RGMII=1
0051  * MAC2 & MAC3: QSGMII=0 SGMII=1
0052  */
0053 #define NSS_COMMON_CLK_SRC_CTRL_RGMII(x)    1
0054 #define NSS_COMMON_CLK_SRC_CTRL_SGMII(x)    ((x >= 2) ? 1 : 0)
0055
0056 #define NSS_COMMON_GMAC_CTL(x)          (0x30 + (x * 4))
0057 #define NSS_COMMON_GMAC_CTL_CSYS_REQ        BIT(19)
0058 #define NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL   BIT(16)
0059 #define NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET    8
0060 #define NSS_COMMON_GMAC_CTL_IFG_OFFSET      0
0061
0062 #define NSS_COMMON_CLK_DIV_RGMII_1000       1
0063 #define NSS_COMMON_CLK_DIV_RGMII_100        9
0064 #define NSS_COMMON_CLK_DIV_RGMII_10     99
0065 #define NSS_COMMON_CLK_DIV_SGMII_1000       0
0066 #define NSS_COMMON_CLK_DIV_SGMII_100        4
0067 #define NSS_COMMON_CLK_DIV_SGMII_10     49
0068
0069 #define QSGMII_PCS_ALL_CH_CTL           0x80
0070 #define QSGMII_PCS_CH_SPEED_FORCE       BIT(1)
0071 #define QSGMII_PCS_CH_SPEED_10          0x0
0072 #define QSGMII_PCS_CH_SPEED_100         BIT(2)
0073 #define QSGMII_PCS_CH_SPEED_1000        BIT(3)
0074 #define QSGMII_PCS_CH_SPEED_MASK        (QSGMII_PCS_CH_SPEED_FORCE | \
0075                          QSGMII_PCS_CH_SPEED_10 | \
0076                          QSGMII_PCS_CH_SPEED_100 | \
0077                          QSGMII_PCS_CH_SPEED_1000)
0078 #define QSGMII_PCS_CH_SPEED_SHIFT(x)        ((x) * 4)
0079
0080 #define QSGMII_PCS_CAL_LCKDT_CTL        0x120
0081 #define QSGMII_PCS_CAL_LCKDT_CTL_RST        BIT(19)
0082
0083 /* Only GMAC1/2/3 support SGMII and their CTL register are not contiguous */
0084 #define QSGMII_PHY_SGMII_CTL(x)         ((x == 1) ? 0x134 : \
0085                          (0x13c + (4 * (x - 2))))
0086 #define QSGMII_PHY_CDR_EN           BIT(0)
0087 #define QSGMII_PHY_RX_FRONT_EN          BIT(1)
0088 #define QSGMII_PHY_RX_SIGNAL_DETECT_EN      BIT(2)
0089 #define QSGMII_PHY_TX_DRIVER_EN         BIT(3)
0090 #define QSGMII_PHY_QSGMII_EN            BIT(7)
0091 #define QSGMII_PHY_DEEMPHASIS_LVL_MASK      GENMASK(11, 10)
0092 #define QSGMII_PHY_DEEMPHASIS_LVL(x)        FIELD_PREP(QSGMII_PHY_DEEMPHASIS_LVL_MASK, (x))
0093 #define QSGMII_PHY_PHASE_LOOP_GAIN_MASK     GENMASK(14, 12)
0094 #define QSGMII_PHY_PHASE_LOOP_GAIN(x)       FIELD_PREP(QSGMII_PHY_PHASE_LOOP_GAIN_MASK, (x))
0095 #define QSGMII_PHY_RX_DC_BIAS_MASK      GENMASK(19, 18)
0096 #define QSGMII_PHY_RX_DC_BIAS(x)        FIELD_PREP(QSGMII_PHY_RX_DC_BIAS_MASK, (x))
0097 #define QSGMII_PHY_RX_INPUT_EQU_MASK        GENMASK(21, 20)
0098 #define QSGMII_PHY_RX_INPUT_EQU(x)      FIELD_PREP(QSGMII_PHY_RX_INPUT_EQU_MASK, (x))
0099 #define QSGMII_PHY_CDR_PI_SLEW_MASK     GENMASK(23, 22)
0100 #define QSGMII_PHY_CDR_PI_SLEW(x)       FIELD_PREP(QSGMII_PHY_CDR_PI_SLEW_MASK, (x))
0101 #define QSGMII_PHY_TX_SLEW_MASK         GENMASK(27, 26)
0102 #define QSGMII_PHY_TX_SLEW(x)           FIELD_PREP(QSGMII_PHY_TX_SLEW_MASK, (x))
0103 #define QSGMII_PHY_TX_DRV_AMP_MASK      GENMASK(31, 28)
0104 #define QSGMII_PHY_TX_DRV_AMP(x)        FIELD_PREP(QSGMII_PHY_TX_DRV_AMP_MASK, (x))
0105
0106 struct ipq806x_gmac {
0107     struct platform_device *pdev;
0108     struct regmap *nss_common;
0109     struct regmap *qsgmii_csr;
0110     uint32_t id;
0111     struct clk *core_clk;
0112     phy_interface_t phy_mode;
0113 };
0114
0115 static int get_clk_div_sgmii(struct ipq806x_gmac *gmac, unsigned int speed)
0116 {
0117     struct device *dev = &gmac->pdev->dev;
0118     int div;
0119
0120     switch (speed) {
0121     case SPEED_1000:
0122         div = NSS_COMMON_CLK_DIV_SGMII_1000;
0123         break;
0124
0125     case SPEED_100:
0126         div = NSS_COMMON_CLK_DIV_SGMII_100;
0127         break;
0128
0129     case SPEED_10:
0130         div = NSS_COMMON_CLK_DIV_SGMII_10;
0131         break;
0132
0133     default:
0134         dev_err(dev, "Speed %dMbps not supported in SGMII\n", speed);
0135         return -EINVAL;
0136     }
0137
0138     return div;
0139 }
0140
0141 static int get_clk_div_rgmii(struct ipq806x_gmac *gmac, unsigned int speed)
0142 {
0143     struct device *dev = &gmac->pdev->dev;
0144     int div;
0145
0146     switch (speed) {
0147     case SPEED_1000:
0148         div = NSS_COMMON_CLK_DIV_RGMII_1000;
0149         break;
0150
0151     case SPEED_100:
0152         div = NSS_COMMON_CLK_DIV_RGMII_100;
0153         break;
0154
0155     case SPEED_10:
0156         div = NSS_COMMON_CLK_DIV_RGMII_10;
0157         break;
0158
0159     default:
0160         dev_err(dev, "Speed %dMbps not supported in RGMII\n", speed);
0161         return -EINVAL;
0162     }
0163
0164     return div;
0165 }
0166
0167 static int ipq806x_gmac_set_speed(struct ipq806x_gmac *gmac, unsigned int speed)
0168 {
0169     uint32_t clk_bits, val;
0170     int div;
0171
0172     switch (gmac->phy_mode) {
0173     case PHY_INTERFACE_MODE_RGMII:
0174         div = get_clk_div_rgmii(gmac, speed);
0175         clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |
0176                NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);
0177         break;
0178
0179     case PHY_INTERFACE_MODE_SGMII:
0180         div = get_clk_div_sgmii(gmac, speed);
0181         clk_bits = NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) |
0182                NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id);
0183         break;
0184
0185     default:
0186         dev_err(&gmac->pdev->dev, "Unsupported PHY mode: \"%s\"\n",
0187             phy_modes(gmac->phy_mode));
0188         return -EINVAL;
0189     }
0190
0191     /* Disable the clocks */
0192     regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
0193     val &= ~clk_bits;
0194     regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
0195
0196     /* Set the divider */
0197     regmap_read(gmac->nss_common, NSS_COMMON_CLK_DIV0, &val);
0198     val &= ~(NSS_COMMON_CLK_DIV_MASK
0199          << NSS_COMMON_CLK_DIV_OFFSET(gmac->id));
0200     val |= div << NSS_COMMON_CLK_DIV_OFFSET(gmac->id);
0201     regmap_write(gmac->nss_common, NSS_COMMON_CLK_DIV0, val);
0202
0203     /* Enable the clock back */
0204     regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
0205     val |= clk_bits;
0206     regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
0207
0208     return 0;
0209 }
0210
0211 static int ipq806x_gmac_of_parse(struct ipq806x_gmac *gmac)
0212 {
0213     struct device *dev = &gmac->pdev->dev;
0214     int ret;
0215
0216     ret = of_get_phy_mode(dev->of_node, &gmac->phy_mode);
0217     if (ret) {
0218         dev_err(dev, "missing phy mode property\n");
0219         return -EINVAL;
0220     }
0221
0222     if (of_property_read_u32(dev->of_node, "qcom,id", &gmac->id) < 0) {
0223         dev_err(dev, "missing qcom id property\n");
0224         return -EINVAL;
0225     }
0226
0227     /* The GMACs are called 1 to 4 in the documentation, but to simplify the
0228      * code and keep it consistent with the Linux convention, we'll number
0229      * them from 0 to 3 here.
0230      */
0231     if (gmac->id > 3) {
0232         dev_err(dev, "invalid gmac id\n");
0233         return -EINVAL;
0234     }
0235
0236     gmac->core_clk = devm_clk_get(dev, "stmmaceth");
0237     if (IS_ERR(gmac->core_clk)) {
0238         dev_err(dev, "missing stmmaceth clk property\n");
0239         return PTR_ERR(gmac->core_clk);
0240     }
0241     clk_set_rate(gmac->core_clk, 266000000);
0242
0243     /* Setup the register map for the nss common registers */
0244     gmac->nss_common = syscon_regmap_lookup_by_phandle(dev->of_node,
0245                                "qcom,nss-common");
0246     if (IS_ERR(gmac->nss_common)) {
0247         dev_err(dev, "missing nss-common node\n");
0248         return PTR_ERR(gmac->nss_common);
0249     }
0250
0251     /* Setup the register map for the qsgmii csr registers */
0252     gmac->qsgmii_csr = syscon_regmap_lookup_by_phandle(dev->of_node,
0253                                "qcom,qsgmii-csr");
0254     if (IS_ERR(gmac->qsgmii_csr))
0255         dev_err(dev, "missing qsgmii-csr node\n");
0256
0257     return PTR_ERR_OR_ZERO(gmac->qsgmii_csr);
0258 }
0259
0260 static void ipq806x_gmac_fix_mac_speed(void *priv, unsigned int speed)
0261 {
0262     struct ipq806x_gmac *gmac = priv;
0263
0264     ipq806x_gmac_set_speed(gmac, speed);
0265 }
0266
0267 static int
0268 ipq806x_gmac_configure_qsgmii_pcs_speed(struct ipq806x_gmac *gmac)
0269 {
0270     struct platform_device *pdev = gmac->pdev;
0271     struct device *dev = &pdev->dev;
0272     struct device_node *dn;
0273     int link_speed;
0274     int val = 0;
0275     int ret;
0276
0277     /* Some bootloader may apply wrong configuration and cause
0278      * not functioning port. If fixed link is not set,
0279      * reset the force speed bit.
0280      */
0281     if (!of_phy_is_fixed_link(pdev->dev.of_node))
0282         goto write;
0283
0284     dn = of_get_child_by_name(pdev->dev.of_node, "fixed-link");
0285     ret = of_property_read_u32(dn, "speed", &link_speed);
0286     of_node_put(dn);
0287     if (ret) {
0288         dev_err(dev, "found fixed-link node with no speed");
0289         return ret;
0290     }
0291
0292     val = QSGMII_PCS_CH_SPEED_FORCE;
0293
0294     switch (link_speed) {
0295     case SPEED_1000:
0296         val |= QSGMII_PCS_CH_SPEED_1000;
0297         break;
0298     case SPEED_100:
0299         val |= QSGMII_PCS_CH_SPEED_100;
0300         break;
0301     case SPEED_10:
0302         val |= QSGMII_PCS_CH_SPEED_10;
0303         break;
0304     }
0305
0306 write:
0307     regmap_update_bits(gmac->qsgmii_csr, QSGMII_PCS_ALL_CH_CTL,
0308                QSGMII_PCS_CH_SPEED_MASK <<
0309                QSGMII_PCS_CH_SPEED_SHIFT(gmac->id),
0310                val <<
0311                QSGMII_PCS_CH_SPEED_SHIFT(gmac->id));
0312
0313     return 0;
0314 }
0315
0316 static const struct soc_device_attribute ipq806x_gmac_soc_v1[] = {
0317     {
0318         .revision = "1.*",
0319     },
0320     {
0321         /* sentinel */
0322     }
0323 };
0324
0325 static int
0326 ipq806x_gmac_configure_qsgmii_params(struct ipq806x_gmac *gmac)
0327 {
0328     struct platform_device *pdev = gmac->pdev;
0329     const struct soc_device_attribute *soc;
0330     struct device *dev = &pdev->dev;
0331     u32 qsgmii_param;
0332
0333     switch (gmac->id) {
0334     case 1:
0335         soc = soc_device_match(ipq806x_gmac_soc_v1);
0336
0337         if (soc)
0338             qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xc) |
0339                        QSGMII_PHY_TX_SLEW(0x2) |
0340                        QSGMII_PHY_DEEMPHASIS_LVL(0x2);
0341         else
0342             qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xd) |
0343                        QSGMII_PHY_TX_SLEW(0x0) |
0344                        QSGMII_PHY_DEEMPHASIS_LVL(0x0);
0345
0346         qsgmii_param |= QSGMII_PHY_RX_DC_BIAS(0x2);
0347         break;
0348     case 2:
0349     case 3:
0350         qsgmii_param = QSGMII_PHY_RX_DC_BIAS(0x3) |
0351                    QSGMII_PHY_TX_DRV_AMP(0xc);
0352         break;
0353     default: /* gmac 0 can't be set in SGMII mode */
0354         dev_err(dev, "gmac id %d can't be in SGMII mode", gmac->id);
0355         return -EINVAL;
0356     }
0357
0358     /* Common params across all gmac id */
0359     qsgmii_param |= QSGMII_PHY_CDR_EN |
0360             QSGMII_PHY_RX_FRONT_EN |
0361             QSGMII_PHY_RX_SIGNAL_DETECT_EN |
0362             QSGMII_PHY_TX_DRIVER_EN |
0363             QSGMII_PHY_QSGMII_EN |
0364             QSGMII_PHY_PHASE_LOOP_GAIN(0x4) |
0365             QSGMII_PHY_RX_INPUT_EQU(0x1) |
0366             QSGMII_PHY_CDR_PI_SLEW(0x2);
0367
0368     regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id),
0369              qsgmii_param);
0370
0371     return 0;
0372 }
0373
0374 static int ipq806x_gmac_probe(struct platform_device *pdev)
0375 {
0376     struct plat_stmmacenet_data *plat_dat;
0377     struct stmmac_resources stmmac_res;
0378     struct device *dev = &pdev->dev;
0379     struct ipq806x_gmac *gmac;
0380     int val;
0381     int err;
0382
0383     val = stmmac_get_platform_resources(pdev, &stmmac_res);
0384     if (val)
0385         return val;
0386
0387     plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
0388     if (IS_ERR(plat_dat))
0389         return PTR_ERR(plat_dat);
0390
0391     gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
0392     if (!gmac) {
0393         err = -ENOMEM;
0394         goto err_remove_config_dt;
0395     }
0396
0397     gmac->pdev = pdev;
0398
0399     err = ipq806x_gmac_of_parse(gmac);
0400     if (err) {
0401         dev_err(dev, "device tree parsing error\n");
0402         goto err_remove_config_dt;
0403     }
0404
0405     regmap_write(gmac->qsgmii_csr, QSGMII_PCS_CAL_LCKDT_CTL,
0406              QSGMII_PCS_CAL_LCKDT_CTL_RST);
0407
0408     /* Inter frame gap is set to 12 */
0409     val = 12 << NSS_COMMON_GMAC_CTL_IFG_OFFSET |
0410           12 << NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET;
0411     /* We also initiate an AXI low power exit request */
0412     val |= NSS_COMMON_GMAC_CTL_CSYS_REQ;
0413     switch (gmac->phy_mode) {
0414     case PHY_INTERFACE_MODE_RGMII:
0415         val |= NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
0416         break;
0417     case PHY_INTERFACE_MODE_SGMII:
0418         val &= ~NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
0419         break;
0420     default:
0421         goto err_unsupported_phy;
0422     }
0423     regmap_write(gmac->nss_common, NSS_COMMON_GMAC_CTL(gmac->id), val);
0424
0425     /* Configure the clock src according to the mode */
0426     regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val);
0427     val &= ~(1 << NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id));
0428     switch (gmac->phy_mode) {
0429     case PHY_INTERFACE_MODE_RGMII:
0430         val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) <<
0431             NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
0432         break;
0433     case PHY_INTERFACE_MODE_SGMII:
0434         val |= NSS_COMMON_CLK_SRC_CTRL_SGMII(gmac->id) <<
0435             NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
0436         break;
0437     default:
0438         goto err_unsupported_phy;
0439     }
0440     regmap_write(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, val);
0441
0442     /* Enable PTP clock */
0443     regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
0444     val |= NSS_COMMON_CLK_GATE_PTP_EN(gmac->id);
0445     switch (gmac->phy_mode) {
0446     case PHY_INTERFACE_MODE_RGMII:
0447         val |= NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |
0448             NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);
0449         break;
0450     case PHY_INTERFACE_MODE_SGMII:
0451         val |= NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) |
0452                 NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id);
0453         break;
0454     default:
0455         goto err_unsupported_phy;
0456     }
0457     regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
0458
0459     if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) {
0460         err = ipq806x_gmac_configure_qsgmii_params(gmac);
0461         if (err)
0462             goto err_remove_config_dt;
0463
0464         err = ipq806x_gmac_configure_qsgmii_pcs_speed(gmac);
0465         if (err)
0466             goto err_remove_config_dt;
0467     }
0468
0469     plat_dat->has_gmac = true;
0470     plat_dat->bsp_priv = gmac;
0471     plat_dat->fix_mac_speed = ipq806x_gmac_fix_mac_speed;
0472     plat_dat->multicast_filter_bins = 0;
0473     plat_dat->tx_fifo_size = 8192;
0474     plat_dat->rx_fifo_size = 8192;
0475
0476     err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
0477     if (err)
0478         goto err_remove_config_dt;
0479
0480     return 0;
0481
0482 err_unsupported_phy:
0483     dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n",
0484         phy_modes(gmac->phy_mode));
0485     err = -EINVAL;
0486
0487 err_remove_config_dt:
0488     stmmac_remove_config_dt(pdev, plat_dat);
0489
0490     return err;
0491 }
0492
0493 static const struct of_device_id ipq806x_gmac_dwmac_match[] = {
0494     { .compatible = "qcom,ipq806x-gmac" },
0495     { }
0496 };
0497 MODULE_DEVICE_TABLE(of, ipq806x_gmac_dwmac_match);
0498
0499 static struct platform_driver ipq806x_gmac_dwmac_driver = {
0500     .probe = ipq806x_gmac_probe,
0501     .remove = stmmac_pltfr_remove,
0502     .driver = {
0503         .name       = "ipq806x-gmac-dwmac",
0504         .pm     = &stmmac_pltfr_pm_ops,
0505         .of_match_table = ipq806x_gmac_dwmac_match,
0506     },
0507 };
0508 module_platform_driver(ipq806x_gmac_dwmac_driver);
0509
0510 MODULE_AUTHOR("Mathieu Olivari <mathieu@codeaurora.org>");
0511 MODULE_DESCRIPTION("Qualcomm Atheros IPQ806x DWMAC specific glue layer");
0512 MODULE_LICENSE("Dual BSD/GPL");