stmicro/stmmac/dwmac-intel.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (c) 2020, Intel Corporation
0003  * DWMAC Intel header file
0004  */
0005
0006 #ifndef __DWMAC_INTEL_H__
0007 #define __DWMAC_INTEL_H__
0008
0009 #define POLL_DELAY_US 8
0010
0011 /* SERDES Register */
0012 #define SERDES_GCR  0x0 /* Global Conguration */
0013 #define SERDES_GSR0 0x5 /* Global Status Reg0 */
0014 #define SERDES_GCR0 0xb /* Global Configuration Reg0 */
0015
0016 /* SERDES defines */
0017 #define SERDES_PLL_CLK      BIT(0)      /* PLL clk valid signal */
0018 #define SERDES_PHY_RX_CLK   BIT(1)      /* PSE SGMII PHY rx clk */
0019 #define SERDES_RST      BIT(2)      /* Serdes Reset */
0020 #define SERDES_PWR_ST_MASK  GENMASK(6, 4)   /* Serdes Power state*/
0021 #define SERDES_RATE_MASK    GENMASK(9, 8)
0022 #define SERDES_PCLK_MASK    GENMASK(14, 12) /* PCLK rate to PHY */
0023 #define SERDES_LINK_MODE_MASK   GENMASK(2, 1)
0024 #define SERDES_LINK_MODE_SHIFT  1
0025 #define SERDES_PWR_ST_SHIFT 4
0026 #define SERDES_PWR_ST_P0    0x0
0027 #define SERDES_PWR_ST_P3    0x3
0028 #define SERDES_LINK_MODE_2G5    0x3
0029 #define SERSED_LINK_MODE_1G 0x2
0030 #define SERDES_PCLK_37p5MHZ 0x0
0031 #define SERDES_PCLK_70MHZ   0x1
0032 #define SERDES_RATE_PCIE_GEN1   0x0
0033 #define SERDES_RATE_PCIE_GEN2   0x1
0034 #define SERDES_RATE_PCIE_SHIFT  8
0035 #define SERDES_PCLK_SHIFT   12
0036
0037 #define INTEL_MGBE_ADHOC_ADDR   0x15
0038 #define INTEL_MGBE_XPCS_ADDR    0x16
0039
0040 /* Cross-timestamping defines */
0041 #define ART_CPUID_LEAF      0x15
0042 #define EHL_PSE_ART_MHZ     19200000
0043
0044 /* Selection for PTP Clock Freq belongs to PSE & PCH GbE */
0045 #define PSE_PTP_CLK_FREQ_MASK       (GMAC_GPO0 | GMAC_GPO3)
0046 #define PSE_PTP_CLK_FREQ_19_2MHZ    (GMAC_GPO0)
0047 #define PSE_PTP_CLK_FREQ_200MHZ     (GMAC_GPO0 | GMAC_GPO3)
0048 #define PSE_PTP_CLK_FREQ_256MHZ     (0)
0049 #define PCH_PTP_CLK_FREQ_MASK       (GMAC_GPO0)
0050 #define PCH_PTP_CLK_FREQ_19_2MHZ    (GMAC_GPO0)
0051 #define PCH_PTP_CLK_FREQ_200MHZ     (0)
0052
0053 #endif /* __DWMAC_INTEL_H__ */