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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright (c) 2020, Intel Corporation
0003  */
0004 
0005 #include <linux/clk-provider.h>
0006 #include <linux/pci.h>
0007 #include <linux/dmi.h>
0008 #include "dwmac-intel.h"
0009 #include "dwmac4.h"
0010 #include "stmmac.h"
0011 #include "stmmac_ptp.h"
0012 
0013 struct intel_priv_data {
0014     int mdio_adhoc_addr;    /* mdio address for serdes & etc */
0015     unsigned long crossts_adj;
0016     bool is_pse;
0017 };
0018 
0019 /* This struct is used to associate PCI Function of MAC controller on a board,
0020  * discovered via DMI, with the address of PHY connected to the MAC. The
0021  * negative value of the address means that MAC controller is not connected
0022  * with PHY.
0023  */
0024 struct stmmac_pci_func_data {
0025     unsigned int func;
0026     int phy_addr;
0027 };
0028 
0029 struct stmmac_pci_dmi_data {
0030     const struct stmmac_pci_func_data *func;
0031     size_t nfuncs;
0032 };
0033 
0034 struct stmmac_pci_info {
0035     int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
0036 };
0037 
0038 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
0039                     const struct dmi_system_id *dmi_list)
0040 {
0041     const struct stmmac_pci_func_data *func_data;
0042     const struct stmmac_pci_dmi_data *dmi_data;
0043     const struct dmi_system_id *dmi_id;
0044     int func = PCI_FUNC(pdev->devfn);
0045     size_t n;
0046 
0047     dmi_id = dmi_first_match(dmi_list);
0048     if (!dmi_id)
0049         return -ENODEV;
0050 
0051     dmi_data = dmi_id->driver_data;
0052     func_data = dmi_data->func;
0053 
0054     for (n = 0; n < dmi_data->nfuncs; n++, func_data++)
0055         if (func_data->func == func)
0056             return func_data->phy_addr;
0057 
0058     return -ENODEV;
0059 }
0060 
0061 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr,
0062                   int phyreg, u32 mask, u32 val)
0063 {
0064     unsigned int retries = 10;
0065     int val_rd;
0066 
0067     do {
0068         val_rd = mdiobus_read(priv->mii, phyaddr, phyreg);
0069         if ((val_rd & mask) == (val & mask))
0070             return 0;
0071         udelay(POLL_DELAY_US);
0072     } while (--retries);
0073 
0074     return -ETIMEDOUT;
0075 }
0076 
0077 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
0078 {
0079     struct intel_priv_data *intel_priv = priv_data;
0080     struct stmmac_priv *priv = netdev_priv(ndev);
0081     int serdes_phy_addr = 0;
0082     u32 data = 0;
0083 
0084     if (!intel_priv->mdio_adhoc_addr)
0085         return 0;
0086 
0087     serdes_phy_addr = intel_priv->mdio_adhoc_addr;
0088 
0089     /* Set the serdes rate and the PCLK rate */
0090     data = mdiobus_read(priv->mii, serdes_phy_addr,
0091                 SERDES_GCR0);
0092 
0093     data &= ~SERDES_RATE_MASK;
0094     data &= ~SERDES_PCLK_MASK;
0095 
0096     if (priv->plat->max_speed == 2500)
0097         data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT |
0098             SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT;
0099     else
0100         data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT |
0101             SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT;
0102 
0103     mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
0104 
0105     /* assert clk_req */
0106     data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
0107     data |= SERDES_PLL_CLK;
0108     mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
0109 
0110     /* check for clk_ack assertion */
0111     data = serdes_status_poll(priv, serdes_phy_addr,
0112                   SERDES_GSR0,
0113                   SERDES_PLL_CLK,
0114                   SERDES_PLL_CLK);
0115 
0116     if (data) {
0117         dev_err(priv->device, "Serdes PLL clk request timeout\n");
0118         return data;
0119     }
0120 
0121     /* assert lane reset */
0122     data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
0123     data |= SERDES_RST;
0124     mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
0125 
0126     /* check for assert lane reset reflection */
0127     data = serdes_status_poll(priv, serdes_phy_addr,
0128                   SERDES_GSR0,
0129                   SERDES_RST,
0130                   SERDES_RST);
0131 
0132     if (data) {
0133         dev_err(priv->device, "Serdes assert lane reset timeout\n");
0134         return data;
0135     }
0136 
0137     /*  move power state to P0 */
0138     data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
0139 
0140     data &= ~SERDES_PWR_ST_MASK;
0141     data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
0142 
0143     mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
0144 
0145     /* Check for P0 state */
0146     data = serdes_status_poll(priv, serdes_phy_addr,
0147                   SERDES_GSR0,
0148                   SERDES_PWR_ST_MASK,
0149                   SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT);
0150 
0151     if (data) {
0152         dev_err(priv->device, "Serdes power state P0 timeout.\n");
0153         return data;
0154     }
0155 
0156     /* PSE only - ungate SGMII PHY Rx Clock */
0157     if (intel_priv->is_pse)
0158         mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
0159                    0, SERDES_PHY_RX_CLK);
0160 
0161     return 0;
0162 }
0163 
0164 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
0165 {
0166     struct intel_priv_data *intel_priv = intel_data;
0167     struct stmmac_priv *priv = netdev_priv(ndev);
0168     int serdes_phy_addr = 0;
0169     u32 data = 0;
0170 
0171     if (!intel_priv->mdio_adhoc_addr)
0172         return;
0173 
0174     serdes_phy_addr = intel_priv->mdio_adhoc_addr;
0175 
0176     /* PSE only - gate SGMII PHY Rx Clock */
0177     if (intel_priv->is_pse)
0178         mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
0179                    SERDES_PHY_RX_CLK, 0);
0180 
0181     /*  move power state to P3 */
0182     data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
0183 
0184     data &= ~SERDES_PWR_ST_MASK;
0185     data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT;
0186 
0187     mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
0188 
0189     /* Check for P3 state */
0190     data = serdes_status_poll(priv, serdes_phy_addr,
0191                   SERDES_GSR0,
0192                   SERDES_PWR_ST_MASK,
0193                   SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT);
0194 
0195     if (data) {
0196         dev_err(priv->device, "Serdes power state P3 timeout\n");
0197         return;
0198     }
0199 
0200     /* de-assert clk_req */
0201     data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
0202     data &= ~SERDES_PLL_CLK;
0203     mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
0204 
0205     /* check for clk_ack de-assert */
0206     data = serdes_status_poll(priv, serdes_phy_addr,
0207                   SERDES_GSR0,
0208                   SERDES_PLL_CLK,
0209                   (u32)~SERDES_PLL_CLK);
0210 
0211     if (data) {
0212         dev_err(priv->device, "Serdes PLL clk de-assert timeout\n");
0213         return;
0214     }
0215 
0216     /* de-assert lane reset */
0217     data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
0218     data &= ~SERDES_RST;
0219     mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
0220 
0221     /* check for de-assert lane reset reflection */
0222     data = serdes_status_poll(priv, serdes_phy_addr,
0223                   SERDES_GSR0,
0224                   SERDES_RST,
0225                   (u32)~SERDES_RST);
0226 
0227     if (data) {
0228         dev_err(priv->device, "Serdes de-assert lane reset timeout\n");
0229         return;
0230     }
0231 }
0232 
0233 static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data)
0234 {
0235     struct intel_priv_data *intel_priv = intel_data;
0236     struct stmmac_priv *priv = netdev_priv(ndev);
0237     int serdes_phy_addr = 0;
0238     u32 data = 0;
0239 
0240     serdes_phy_addr = intel_priv->mdio_adhoc_addr;
0241 
0242     /* Determine the link speed mode: 2.5Gbps/1Gbps */
0243     data = mdiobus_read(priv->mii, serdes_phy_addr,
0244                 SERDES_GCR);
0245 
0246     if (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) ==
0247         SERDES_LINK_MODE_2G5) {
0248         dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n");
0249         priv->plat->max_speed = 2500;
0250         priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX;
0251         priv->plat->mdio_bus_data->xpcs_an_inband = false;
0252     } else {
0253         priv->plat->max_speed = 1000;
0254         priv->plat->mdio_bus_data->xpcs_an_inband = true;
0255     }
0256 }
0257 
0258 /* Program PTP Clock Frequency for different variant of
0259  * Intel mGBE that has slightly different GPO mapping
0260  */
0261 static void intel_mgbe_ptp_clk_freq_config(void *npriv)
0262 {
0263     struct stmmac_priv *priv = (struct stmmac_priv *)npriv;
0264     struct intel_priv_data *intel_priv;
0265     u32 gpio_value;
0266 
0267     intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv;
0268 
0269     gpio_value = readl(priv->ioaddr + GMAC_GPIO_STATUS);
0270 
0271     if (intel_priv->is_pse) {
0272         /* For PSE GbE, use 200MHz */
0273         gpio_value &= ~PSE_PTP_CLK_FREQ_MASK;
0274         gpio_value |= PSE_PTP_CLK_FREQ_200MHZ;
0275     } else {
0276         /* For PCH GbE, use 200MHz */
0277         gpio_value &= ~PCH_PTP_CLK_FREQ_MASK;
0278         gpio_value |= PCH_PTP_CLK_FREQ_200MHZ;
0279     }
0280 
0281     writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS);
0282 }
0283 
0284 static void get_arttime(struct mii_bus *mii, int intel_adhoc_addr,
0285             u64 *art_time)
0286 {
0287     u64 ns;
0288 
0289     ns = mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE3);
0290     ns <<= GMAC4_ART_TIME_SHIFT;
0291     ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE2);
0292     ns <<= GMAC4_ART_TIME_SHIFT;
0293     ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE1);
0294     ns <<= GMAC4_ART_TIME_SHIFT;
0295     ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE0);
0296 
0297     *art_time = ns;
0298 }
0299 
0300 static int stmmac_cross_ts_isr(struct stmmac_priv *priv)
0301 {
0302     return (readl(priv->ioaddr + GMAC_INT_STATUS) & GMAC_INT_TSIE);
0303 }
0304 
0305 static int intel_crosststamp(ktime_t *device,
0306                  struct system_counterval_t *system,
0307                  void *ctx)
0308 {
0309     struct intel_priv_data *intel_priv;
0310 
0311     struct stmmac_priv *priv = (struct stmmac_priv *)ctx;
0312     void __iomem *ptpaddr = priv->ptpaddr;
0313     void __iomem *ioaddr = priv->hw->pcsr;
0314     unsigned long flags;
0315     u64 art_time = 0;
0316     u64 ptp_time = 0;
0317     u32 num_snapshot;
0318     u32 gpio_value;
0319     u32 acr_value;
0320     int i;
0321 
0322     if (!boot_cpu_has(X86_FEATURE_ART))
0323         return -EOPNOTSUPP;
0324 
0325     intel_priv = priv->plat->bsp_priv;
0326 
0327     /* Both internal crosstimestamping and external triggered event
0328      * timestamping cannot be run concurrently.
0329      */
0330     if (priv->plat->ext_snapshot_en)
0331         return -EBUSY;
0332 
0333     priv->plat->int_snapshot_en = 1;
0334 
0335     mutex_lock(&priv->aux_ts_lock);
0336     /* Enable Internal snapshot trigger */
0337     acr_value = readl(ptpaddr + PTP_ACR);
0338     acr_value &= ~PTP_ACR_MASK;
0339     switch (priv->plat->int_snapshot_num) {
0340     case AUX_SNAPSHOT0:
0341         acr_value |= PTP_ACR_ATSEN0;
0342         break;
0343     case AUX_SNAPSHOT1:
0344         acr_value |= PTP_ACR_ATSEN1;
0345         break;
0346     case AUX_SNAPSHOT2:
0347         acr_value |= PTP_ACR_ATSEN2;
0348         break;
0349     case AUX_SNAPSHOT3:
0350         acr_value |= PTP_ACR_ATSEN3;
0351         break;
0352     default:
0353         mutex_unlock(&priv->aux_ts_lock);
0354         priv->plat->int_snapshot_en = 0;
0355         return -EINVAL;
0356     }
0357     writel(acr_value, ptpaddr + PTP_ACR);
0358 
0359     /* Clear FIFO */
0360     acr_value = readl(ptpaddr + PTP_ACR);
0361     acr_value |= PTP_ACR_ATSFC;
0362     writel(acr_value, ptpaddr + PTP_ACR);
0363     /* Release the mutex */
0364     mutex_unlock(&priv->aux_ts_lock);
0365 
0366     /* Trigger Internal snapshot signal
0367      * Create a rising edge by just toggle the GPO1 to low
0368      * and back to high.
0369      */
0370     gpio_value = readl(ioaddr + GMAC_GPIO_STATUS);
0371     gpio_value &= ~GMAC_GPO1;
0372     writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
0373     gpio_value |= GMAC_GPO1;
0374     writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
0375 
0376     /* Time sync done Indication - Interrupt method */
0377     if (!wait_event_interruptible_timeout(priv->tstamp_busy_wait,
0378                           stmmac_cross_ts_isr(priv),
0379                           HZ / 100)) {
0380         priv->plat->int_snapshot_en = 0;
0381         return -ETIMEDOUT;
0382     }
0383 
0384     num_snapshot = (readl(ioaddr + GMAC_TIMESTAMP_STATUS) &
0385             GMAC_TIMESTAMP_ATSNS_MASK) >>
0386             GMAC_TIMESTAMP_ATSNS_SHIFT;
0387 
0388     /* Repeat until the timestamps are from the FIFO last segment */
0389     for (i = 0; i < num_snapshot; i++) {
0390         read_lock_irqsave(&priv->ptp_lock, flags);
0391         stmmac_get_ptptime(priv, ptpaddr, &ptp_time);
0392         *device = ns_to_ktime(ptp_time);
0393         read_unlock_irqrestore(&priv->ptp_lock, flags);
0394         get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time);
0395         *system = convert_art_to_tsc(art_time);
0396     }
0397 
0398     system->cycles *= intel_priv->crossts_adj;
0399     priv->plat->int_snapshot_en = 0;
0400 
0401     return 0;
0402 }
0403 
0404 static void intel_mgbe_pse_crossts_adj(struct intel_priv_data *intel_priv,
0405                        int base)
0406 {
0407     if (boot_cpu_has(X86_FEATURE_ART)) {
0408         unsigned int art_freq;
0409 
0410         /* On systems that support ART, ART frequency can be obtained
0411          * from ECX register of CPUID leaf (0x15).
0412          */
0413         art_freq = cpuid_ecx(ART_CPUID_LEAF);
0414         do_div(art_freq, base);
0415         intel_priv->crossts_adj = art_freq;
0416     }
0417 }
0418 
0419 static void common_default_data(struct plat_stmmacenet_data *plat)
0420 {
0421     plat->clk_csr = 2;  /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
0422     plat->has_gmac = 1;
0423     plat->force_sf_dma_mode = 1;
0424 
0425     plat->mdio_bus_data->needs_reset = true;
0426 
0427     /* Set default value for multicast hash bins */
0428     plat->multicast_filter_bins = HASH_TABLE_SIZE;
0429 
0430     /* Set default value for unicast filter entries */
0431     plat->unicast_filter_entries = 1;
0432 
0433     /* Set the maxmtu to a default of JUMBO_LEN */
0434     plat->maxmtu = JUMBO_LEN;
0435 
0436     /* Set default number of RX and TX queues to use */
0437     plat->tx_queues_to_use = 1;
0438     plat->rx_queues_to_use = 1;
0439 
0440     /* Disable Priority config by default */
0441     plat->tx_queues_cfg[0].use_prio = false;
0442     plat->rx_queues_cfg[0].use_prio = false;
0443 
0444     /* Disable RX queues routing by default */
0445     plat->rx_queues_cfg[0].pkt_route = 0x0;
0446 }
0447 
0448 static int intel_mgbe_common_data(struct pci_dev *pdev,
0449                   struct plat_stmmacenet_data *plat)
0450 {
0451     struct fwnode_handle *fwnode;
0452     char clk_name[20];
0453     int ret;
0454     int i;
0455 
0456     plat->pdev = pdev;
0457     plat->phy_addr = -1;
0458     plat->clk_csr = 5;
0459     plat->has_gmac = 0;
0460     plat->has_gmac4 = 1;
0461     plat->force_sf_dma_mode = 0;
0462     plat->tso_en = 1;
0463     plat->sph_disable = 1;
0464 
0465     /* Multiplying factor to the clk_eee_i clock time
0466      * period to make it closer to 100 ns. This value
0467      * should be programmed such that the clk_eee_time_period *
0468      * (MULT_FACT_100NS + 1) should be within 80 ns to 120 ns
0469      * clk_eee frequency is 19.2Mhz
0470      * clk_eee_time_period is 52ns
0471      * 52ns * (1 + 1) = 104ns
0472      * MULT_FACT_100NS = 1
0473      */
0474     plat->mult_fact_100ns = 1;
0475 
0476     plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
0477 
0478     for (i = 0; i < plat->rx_queues_to_use; i++) {
0479         plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
0480         plat->rx_queues_cfg[i].chan = i;
0481 
0482         /* Disable Priority config by default */
0483         plat->rx_queues_cfg[i].use_prio = false;
0484 
0485         /* Disable RX queues routing by default */
0486         plat->rx_queues_cfg[i].pkt_route = 0x0;
0487     }
0488 
0489     for (i = 0; i < plat->tx_queues_to_use; i++) {
0490         plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
0491 
0492         /* Disable Priority config by default */
0493         plat->tx_queues_cfg[i].use_prio = false;
0494         /* Default TX Q0 to use TSO and rest TXQ for TBS */
0495         if (i > 0)
0496             plat->tx_queues_cfg[i].tbs_en = 1;
0497     }
0498 
0499     /* FIFO size is 4096 bytes for 1 tx/rx queue */
0500     plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
0501     plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
0502 
0503     plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
0504     plat->tx_queues_cfg[0].weight = 0x09;
0505     plat->tx_queues_cfg[1].weight = 0x0A;
0506     plat->tx_queues_cfg[2].weight = 0x0B;
0507     plat->tx_queues_cfg[3].weight = 0x0C;
0508     plat->tx_queues_cfg[4].weight = 0x0D;
0509     plat->tx_queues_cfg[5].weight = 0x0E;
0510     plat->tx_queues_cfg[6].weight = 0x0F;
0511     plat->tx_queues_cfg[7].weight = 0x10;
0512 
0513     plat->dma_cfg->pbl = 32;
0514     plat->dma_cfg->pblx8 = true;
0515     plat->dma_cfg->fixed_burst = 0;
0516     plat->dma_cfg->mixed_burst = 0;
0517     plat->dma_cfg->aal = 0;
0518     plat->dma_cfg->dche = true;
0519 
0520     plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
0521                  GFP_KERNEL);
0522     if (!plat->axi)
0523         return -ENOMEM;
0524 
0525     plat->axi->axi_lpi_en = 0;
0526     plat->axi->axi_xit_frm = 0;
0527     plat->axi->axi_wr_osr_lmt = 1;
0528     plat->axi->axi_rd_osr_lmt = 1;
0529     plat->axi->axi_blen[0] = 4;
0530     plat->axi->axi_blen[1] = 8;
0531     plat->axi->axi_blen[2] = 16;
0532 
0533     plat->ptp_max_adj = plat->clk_ptp_rate;
0534     plat->eee_usecs_rate = plat->clk_ptp_rate;
0535 
0536     /* Set system clock */
0537     sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev));
0538 
0539     plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
0540                            clk_name, NULL, 0,
0541                            plat->clk_ptp_rate);
0542 
0543     if (IS_ERR(plat->stmmac_clk)) {
0544         dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
0545         plat->stmmac_clk = NULL;
0546     }
0547 
0548     ret = clk_prepare_enable(plat->stmmac_clk);
0549     if (ret) {
0550         clk_unregister_fixed_rate(plat->stmmac_clk);
0551         return ret;
0552     }
0553 
0554     plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config;
0555 
0556     /* Set default value for multicast hash bins */
0557     plat->multicast_filter_bins = HASH_TABLE_SIZE;
0558 
0559     /* Set default value for unicast filter entries */
0560     plat->unicast_filter_entries = 1;
0561 
0562     /* Set the maxmtu to a default of JUMBO_LEN */
0563     plat->maxmtu = JUMBO_LEN;
0564 
0565     plat->vlan_fail_q_en = true;
0566 
0567     /* Use the last Rx queue */
0568     plat->vlan_fail_q = plat->rx_queues_to_use - 1;
0569 
0570     /* For fixed-link setup, we allow phy-mode setting */
0571     fwnode = dev_fwnode(&pdev->dev);
0572     if (fwnode) {
0573         int phy_mode;
0574 
0575         /* "phy-mode" setting is optional. If it is set,
0576          *  we allow either sgmii or 1000base-x for now.
0577          */
0578         phy_mode = fwnode_get_phy_mode(fwnode);
0579         if (phy_mode >= 0) {
0580             if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
0581                 phy_mode == PHY_INTERFACE_MODE_1000BASEX)
0582                 plat->phy_interface = phy_mode;
0583             else
0584                 dev_warn(&pdev->dev, "Invalid phy-mode\n");
0585         }
0586     }
0587 
0588     /* Intel mgbe SGMII interface uses pcs-xcps */
0589     if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII ||
0590         plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
0591         plat->mdio_bus_data->has_xpcs = true;
0592         plat->mdio_bus_data->xpcs_an_inband = true;
0593     }
0594 
0595     /* For fixed-link setup, we clear xpcs_an_inband */
0596     if (fwnode) {
0597         struct fwnode_handle *fixed_node;
0598 
0599         fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link");
0600         if (fixed_node)
0601             plat->mdio_bus_data->xpcs_an_inband = false;
0602 
0603         fwnode_handle_put(fixed_node);
0604     }
0605 
0606     /* Ensure mdio bus scan skips intel serdes and pcs-xpcs */
0607     plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR;
0608     plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR;
0609 
0610     plat->int_snapshot_num = AUX_SNAPSHOT1;
0611     plat->ext_snapshot_num = AUX_SNAPSHOT0;
0612 
0613     plat->has_crossts = true;
0614     plat->crosststamp = intel_crosststamp;
0615     plat->int_snapshot_en = 0;
0616 
0617     /* Setup MSI vector offset specific to Intel mGbE controller */
0618     plat->msi_mac_vec = 29;
0619     plat->msi_lpi_vec = 28;
0620     plat->msi_sfty_ce_vec = 27;
0621     plat->msi_sfty_ue_vec = 26;
0622     plat->msi_rx_base_vec = 0;
0623     plat->msi_tx_base_vec = 1;
0624 
0625     return 0;
0626 }
0627 
0628 static int ehl_common_data(struct pci_dev *pdev,
0629                struct plat_stmmacenet_data *plat)
0630 {
0631     plat->rx_queues_to_use = 8;
0632     plat->tx_queues_to_use = 8;
0633     plat->clk_ptp_rate = 200000000;
0634     plat->use_phy_wol = 1;
0635 
0636     plat->safety_feat_cfg->tsoee = 1;
0637     plat->safety_feat_cfg->mrxpee = 1;
0638     plat->safety_feat_cfg->mestee = 1;
0639     plat->safety_feat_cfg->mrxee = 1;
0640     plat->safety_feat_cfg->mtxee = 1;
0641     plat->safety_feat_cfg->epsi = 0;
0642     plat->safety_feat_cfg->edpp = 0;
0643     plat->safety_feat_cfg->prtyen = 0;
0644     plat->safety_feat_cfg->tmouten = 0;
0645 
0646     return intel_mgbe_common_data(pdev, plat);
0647 }
0648 
0649 static int ehl_sgmii_data(struct pci_dev *pdev,
0650               struct plat_stmmacenet_data *plat)
0651 {
0652     plat->bus_id = 1;
0653     plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
0654     plat->speed_mode_2500 = intel_speed_mode_2500;
0655     plat->serdes_powerup = intel_serdes_powerup;
0656     plat->serdes_powerdown = intel_serdes_powerdown;
0657 
0658     return ehl_common_data(pdev, plat);
0659 }
0660 
0661 static struct stmmac_pci_info ehl_sgmii1g_info = {
0662     .setup = ehl_sgmii_data,
0663 };
0664 
0665 static int ehl_rgmii_data(struct pci_dev *pdev,
0666               struct plat_stmmacenet_data *plat)
0667 {
0668     plat->bus_id = 1;
0669     plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
0670 
0671     return ehl_common_data(pdev, plat);
0672 }
0673 
0674 static struct stmmac_pci_info ehl_rgmii1g_info = {
0675     .setup = ehl_rgmii_data,
0676 };
0677 
0678 static int ehl_pse0_common_data(struct pci_dev *pdev,
0679                 struct plat_stmmacenet_data *plat)
0680 {
0681     struct intel_priv_data *intel_priv = plat->bsp_priv;
0682 
0683     intel_priv->is_pse = true;
0684     plat->bus_id = 2;
0685     plat->addr64 = 32;
0686 
0687     intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
0688 
0689     return ehl_common_data(pdev, plat);
0690 }
0691 
0692 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
0693                  struct plat_stmmacenet_data *plat)
0694 {
0695     plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
0696     return ehl_pse0_common_data(pdev, plat);
0697 }
0698 
0699 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = {
0700     .setup = ehl_pse0_rgmii1g_data,
0701 };
0702 
0703 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
0704                  struct plat_stmmacenet_data *plat)
0705 {
0706     plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
0707     plat->speed_mode_2500 = intel_speed_mode_2500;
0708     plat->serdes_powerup = intel_serdes_powerup;
0709     plat->serdes_powerdown = intel_serdes_powerdown;
0710     return ehl_pse0_common_data(pdev, plat);
0711 }
0712 
0713 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = {
0714     .setup = ehl_pse0_sgmii1g_data,
0715 };
0716 
0717 static int ehl_pse1_common_data(struct pci_dev *pdev,
0718                 struct plat_stmmacenet_data *plat)
0719 {
0720     struct intel_priv_data *intel_priv = plat->bsp_priv;
0721 
0722     intel_priv->is_pse = true;
0723     plat->bus_id = 3;
0724     plat->addr64 = 32;
0725 
0726     intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
0727 
0728     return ehl_common_data(pdev, plat);
0729 }
0730 
0731 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
0732                  struct plat_stmmacenet_data *plat)
0733 {
0734     plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
0735     return ehl_pse1_common_data(pdev, plat);
0736 }
0737 
0738 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = {
0739     .setup = ehl_pse1_rgmii1g_data,
0740 };
0741 
0742 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
0743                  struct plat_stmmacenet_data *plat)
0744 {
0745     plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
0746     plat->speed_mode_2500 = intel_speed_mode_2500;
0747     plat->serdes_powerup = intel_serdes_powerup;
0748     plat->serdes_powerdown = intel_serdes_powerdown;
0749     return ehl_pse1_common_data(pdev, plat);
0750 }
0751 
0752 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = {
0753     .setup = ehl_pse1_sgmii1g_data,
0754 };
0755 
0756 static int tgl_common_data(struct pci_dev *pdev,
0757                struct plat_stmmacenet_data *plat)
0758 {
0759     plat->rx_queues_to_use = 6;
0760     plat->tx_queues_to_use = 4;
0761     plat->clk_ptp_rate = 200000000;
0762     plat->speed_mode_2500 = intel_speed_mode_2500;
0763 
0764     plat->safety_feat_cfg->tsoee = 1;
0765     plat->safety_feat_cfg->mrxpee = 0;
0766     plat->safety_feat_cfg->mestee = 1;
0767     plat->safety_feat_cfg->mrxee = 1;
0768     plat->safety_feat_cfg->mtxee = 1;
0769     plat->safety_feat_cfg->epsi = 0;
0770     plat->safety_feat_cfg->edpp = 0;
0771     plat->safety_feat_cfg->prtyen = 0;
0772     plat->safety_feat_cfg->tmouten = 0;
0773 
0774     return intel_mgbe_common_data(pdev, plat);
0775 }
0776 
0777 static int tgl_sgmii_phy0_data(struct pci_dev *pdev,
0778                    struct plat_stmmacenet_data *plat)
0779 {
0780     plat->bus_id = 1;
0781     plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
0782     plat->serdes_powerup = intel_serdes_powerup;
0783     plat->serdes_powerdown = intel_serdes_powerdown;
0784     return tgl_common_data(pdev, plat);
0785 }
0786 
0787 static struct stmmac_pci_info tgl_sgmii1g_phy0_info = {
0788     .setup = tgl_sgmii_phy0_data,
0789 };
0790 
0791 static int tgl_sgmii_phy1_data(struct pci_dev *pdev,
0792                    struct plat_stmmacenet_data *plat)
0793 {
0794     plat->bus_id = 2;
0795     plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
0796     plat->serdes_powerup = intel_serdes_powerup;
0797     plat->serdes_powerdown = intel_serdes_powerdown;
0798     return tgl_common_data(pdev, plat);
0799 }
0800 
0801 static struct stmmac_pci_info tgl_sgmii1g_phy1_info = {
0802     .setup = tgl_sgmii_phy1_data,
0803 };
0804 
0805 static int adls_sgmii_phy0_data(struct pci_dev *pdev,
0806                 struct plat_stmmacenet_data *plat)
0807 {
0808     plat->bus_id = 1;
0809     plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
0810 
0811     /* SerDes power up and power down are done in BIOS for ADL */
0812 
0813     return tgl_common_data(pdev, plat);
0814 }
0815 
0816 static struct stmmac_pci_info adls_sgmii1g_phy0_info = {
0817     .setup = adls_sgmii_phy0_data,
0818 };
0819 
0820 static int adls_sgmii_phy1_data(struct pci_dev *pdev,
0821                 struct plat_stmmacenet_data *plat)
0822 {
0823     plat->bus_id = 2;
0824     plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
0825 
0826     /* SerDes power up and power down are done in BIOS for ADL */
0827 
0828     return tgl_common_data(pdev, plat);
0829 }
0830 
0831 static struct stmmac_pci_info adls_sgmii1g_phy1_info = {
0832     .setup = adls_sgmii_phy1_data,
0833 };
0834 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
0835     {
0836         .func = 6,
0837         .phy_addr = 1,
0838     },
0839 };
0840 
0841 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {
0842     .func = galileo_stmmac_func_data,
0843     .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data),
0844 };
0845 
0846 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {
0847     {
0848         .func = 6,
0849         .phy_addr = 1,
0850     },
0851     {
0852         .func = 7,
0853         .phy_addr = 1,
0854     },
0855 };
0856 
0857 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {
0858     .func = iot2040_stmmac_func_data,
0859     .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data),
0860 };
0861 
0862 static const struct dmi_system_id quark_pci_dmi[] = {
0863     {
0864         .matches = {
0865             DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
0866         },
0867         .driver_data = (void *)&galileo_stmmac_dmi_data,
0868     },
0869     {
0870         .matches = {
0871             DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
0872         },
0873         .driver_data = (void *)&galileo_stmmac_dmi_data,
0874     },
0875     /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040.
0876      * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
0877      * has only one pci network device while other asset tags are
0878      * for IOT2040 which has two.
0879      */
0880     {
0881         .matches = {
0882             DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
0883             DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
0884                     "6ES7647-0AA00-0YA2"),
0885         },
0886         .driver_data = (void *)&galileo_stmmac_dmi_data,
0887     },
0888     {
0889         .matches = {
0890             DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
0891         },
0892         .driver_data = (void *)&iot2040_stmmac_dmi_data,
0893     },
0894     {}
0895 };
0896 
0897 static int quark_default_data(struct pci_dev *pdev,
0898                   struct plat_stmmacenet_data *plat)
0899 {
0900     int ret;
0901 
0902     /* Set common default data first */
0903     common_default_data(plat);
0904 
0905     /* Refuse to load the driver and register net device if MAC controller
0906      * does not connect to any PHY interface.
0907      */
0908     ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi);
0909     if (ret < 0) {
0910         /* Return error to the caller on DMI enabled boards. */
0911         if (dmi_get_system_info(DMI_BOARD_NAME))
0912             return ret;
0913 
0914         /* Galileo boards with old firmware don't support DMI. We always
0915          * use 1 here as PHY address, so at least the first found MAC
0916          * controller would be probed.
0917          */
0918         ret = 1;
0919     }
0920 
0921     plat->bus_id = pci_dev_id(pdev);
0922     plat->phy_addr = ret;
0923     plat->phy_interface = PHY_INTERFACE_MODE_RMII;
0924 
0925     plat->dma_cfg->pbl = 16;
0926     plat->dma_cfg->pblx8 = true;
0927     plat->dma_cfg->fixed_burst = 1;
0928     /* AXI (TODO) */
0929 
0930     return 0;
0931 }
0932 
0933 static const struct stmmac_pci_info quark_info = {
0934     .setup = quark_default_data,
0935 };
0936 
0937 static int stmmac_config_single_msi(struct pci_dev *pdev,
0938                     struct plat_stmmacenet_data *plat,
0939                     struct stmmac_resources *res)
0940 {
0941     int ret;
0942 
0943     ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
0944     if (ret < 0) {
0945         dev_info(&pdev->dev, "%s: Single IRQ enablement failed\n",
0946              __func__);
0947         return ret;
0948     }
0949 
0950     res->irq = pci_irq_vector(pdev, 0);
0951     res->wol_irq = res->irq;
0952     plat->multi_msi_en = 0;
0953     dev_info(&pdev->dev, "%s: Single IRQ enablement successful\n",
0954          __func__);
0955 
0956     return 0;
0957 }
0958 
0959 static int stmmac_config_multi_msi(struct pci_dev *pdev,
0960                    struct plat_stmmacenet_data *plat,
0961                    struct stmmac_resources *res)
0962 {
0963     int ret;
0964     int i;
0965 
0966     if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX ||
0967         plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) {
0968         dev_info(&pdev->dev, "%s: Invalid RX & TX vector defined\n",
0969              __func__);
0970         return -1;
0971     }
0972 
0973     ret = pci_alloc_irq_vectors(pdev, 2, STMMAC_MSI_VEC_MAX,
0974                     PCI_IRQ_MSI | PCI_IRQ_MSIX);
0975     if (ret < 0) {
0976         dev_info(&pdev->dev, "%s: multi MSI enablement failed\n",
0977              __func__);
0978         return ret;
0979     }
0980 
0981     /* For RX MSI */
0982     for (i = 0; i < plat->rx_queues_to_use; i++) {
0983         res->rx_irq[i] = pci_irq_vector(pdev,
0984                         plat->msi_rx_base_vec + i * 2);
0985     }
0986 
0987     /* For TX MSI */
0988     for (i = 0; i < plat->tx_queues_to_use; i++) {
0989         res->tx_irq[i] = pci_irq_vector(pdev,
0990                         plat->msi_tx_base_vec + i * 2);
0991     }
0992 
0993     if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX)
0994         res->irq = pci_irq_vector(pdev, plat->msi_mac_vec);
0995     if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX)
0996         res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec);
0997     if (plat->msi_lpi_vec < STMMAC_MSI_VEC_MAX)
0998         res->lpi_irq = pci_irq_vector(pdev, plat->msi_lpi_vec);
0999     if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX)
1000         res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec);
1001     if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX)
1002         res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec);
1003 
1004     plat->multi_msi_en = 1;
1005     dev_info(&pdev->dev, "%s: multi MSI enablement successful\n", __func__);
1006 
1007     return 0;
1008 }
1009 
1010 /**
1011  * intel_eth_pci_probe
1012  *
1013  * @pdev: pci device pointer
1014  * @id: pointer to table of device id/id's.
1015  *
1016  * Description: This probing function gets called for all PCI devices which
1017  * match the ID table and are not "owned" by other driver yet. This function
1018  * gets passed a "struct pci_dev *" for each device whose entry in the ID table
1019  * matches the device. The probe functions returns zero when the driver choose
1020  * to take "ownership" of the device or an error code(-ve no) otherwise.
1021  */
1022 static int intel_eth_pci_probe(struct pci_dev *pdev,
1023                    const struct pci_device_id *id)
1024 {
1025     struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data;
1026     struct intel_priv_data *intel_priv;
1027     struct plat_stmmacenet_data *plat;
1028     struct stmmac_resources res;
1029     int ret;
1030 
1031     intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL);
1032     if (!intel_priv)
1033         return -ENOMEM;
1034 
1035     plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
1036     if (!plat)
1037         return -ENOMEM;
1038 
1039     plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
1040                        sizeof(*plat->mdio_bus_data),
1041                        GFP_KERNEL);
1042     if (!plat->mdio_bus_data)
1043         return -ENOMEM;
1044 
1045     plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
1046                      GFP_KERNEL);
1047     if (!plat->dma_cfg)
1048         return -ENOMEM;
1049 
1050     plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
1051                          sizeof(*plat->safety_feat_cfg),
1052                          GFP_KERNEL);
1053     if (!plat->safety_feat_cfg)
1054         return -ENOMEM;
1055 
1056     /* Enable pci device */
1057     ret = pcim_enable_device(pdev);
1058     if (ret) {
1059         dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
1060             __func__);
1061         return ret;
1062     }
1063 
1064     ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
1065     if (ret)
1066         return ret;
1067 
1068     pci_set_master(pdev);
1069 
1070     plat->bsp_priv = intel_priv;
1071     intel_priv->mdio_adhoc_addr = INTEL_MGBE_ADHOC_ADDR;
1072     intel_priv->crossts_adj = 1;
1073 
1074     /* Initialize all MSI vectors to invalid so that it can be set
1075      * according to platform data settings below.
1076      * Note: MSI vector takes value from 0 upto 31 (STMMAC_MSI_VEC_MAX)
1077      */
1078     plat->msi_mac_vec = STMMAC_MSI_VEC_MAX;
1079     plat->msi_wol_vec = STMMAC_MSI_VEC_MAX;
1080     plat->msi_lpi_vec = STMMAC_MSI_VEC_MAX;
1081     plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX;
1082     plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX;
1083     plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX;
1084     plat->msi_tx_base_vec = STMMAC_MSI_VEC_MAX;
1085 
1086     ret = info->setup(pdev, plat);
1087     if (ret)
1088         return ret;
1089 
1090     memset(&res, 0, sizeof(res));
1091     res.addr = pcim_iomap_table(pdev)[0];
1092 
1093     if (plat->eee_usecs_rate > 0) {
1094         u32 tx_lpi_usec;
1095 
1096         tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1;
1097         writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER);
1098     }
1099 
1100     ret = stmmac_config_multi_msi(pdev, plat, &res);
1101     if (ret) {
1102         ret = stmmac_config_single_msi(pdev, plat, &res);
1103         if (ret) {
1104             dev_err(&pdev->dev, "%s: ERROR: failed to enable IRQ\n",
1105                 __func__);
1106             goto err_alloc_irq;
1107         }
1108     }
1109 
1110     ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
1111     if (ret) {
1112         goto err_alloc_irq;
1113     }
1114 
1115     return 0;
1116 
1117 err_alloc_irq:
1118     clk_disable_unprepare(plat->stmmac_clk);
1119     clk_unregister_fixed_rate(plat->stmmac_clk);
1120     return ret;
1121 }
1122 
1123 /**
1124  * intel_eth_pci_remove
1125  *
1126  * @pdev: pci device pointer
1127  * Description: this function calls the main to free the net resources
1128  * and releases the PCI resources.
1129  */
1130 static void intel_eth_pci_remove(struct pci_dev *pdev)
1131 {
1132     struct net_device *ndev = dev_get_drvdata(&pdev->dev);
1133     struct stmmac_priv *priv = netdev_priv(ndev);
1134 
1135     stmmac_dvr_remove(&pdev->dev);
1136 
1137     clk_disable_unprepare(priv->plat->stmmac_clk);
1138     clk_unregister_fixed_rate(priv->plat->stmmac_clk);
1139 }
1140 
1141 static int __maybe_unused intel_eth_pci_suspend(struct device *dev)
1142 {
1143     struct pci_dev *pdev = to_pci_dev(dev);
1144     int ret;
1145 
1146     ret = stmmac_suspend(dev);
1147     if (ret)
1148         return ret;
1149 
1150     ret = pci_save_state(pdev);
1151     if (ret)
1152         return ret;
1153 
1154     pci_wake_from_d3(pdev, true);
1155     pci_set_power_state(pdev, PCI_D3hot);
1156     return 0;
1157 }
1158 
1159 static int __maybe_unused intel_eth_pci_resume(struct device *dev)
1160 {
1161     struct pci_dev *pdev = to_pci_dev(dev);
1162     int ret;
1163 
1164     pci_restore_state(pdev);
1165     pci_set_power_state(pdev, PCI_D0);
1166 
1167     ret = pcim_enable_device(pdev);
1168     if (ret)
1169         return ret;
1170 
1171     pci_set_master(pdev);
1172 
1173     return stmmac_resume(dev);
1174 }
1175 
1176 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
1177              intel_eth_pci_resume);
1178 
1179 #define PCI_DEVICE_ID_INTEL_QUARK       0x0937
1180 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G     0x4b30
1181 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G     0x4b31
1182 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5    0x4b32
1183 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
1184  * which are named PSE0 and PSE1
1185  */
1186 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G    0x4ba0
1187 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G    0x4ba1
1188 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5   0x4ba2
1189 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G    0x4bb0
1190 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G    0x4bb1
1191 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5   0x4bb2
1192 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0  0x43ac
1193 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1  0x43a2
1194 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G     0xa0ac
1195 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0  0x7aac
1196 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1  0x7aad
1197 #define PCI_DEVICE_ID_INTEL_ADLN_SGMII1G    0x54ac
1198 #define PCI_DEVICE_ID_INTEL_RPLP_SGMII1G    0x51ac
1199 
1200 static const struct pci_device_id intel_eth_pci_id_table[] = {
1201     { PCI_DEVICE_DATA(INTEL, QUARK, &quark_info) },
1202     { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G, &ehl_rgmii1g_info) },
1203     { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G, &ehl_sgmii1g_info) },
1204     { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5, &ehl_sgmii1g_info) },
1205     { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G, &ehl_pse0_rgmii1g_info) },
1206     { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G, &ehl_pse0_sgmii1g_info) },
1207     { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5, &ehl_pse0_sgmii1g_info) },
1208     { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G, &ehl_pse1_rgmii1g_info) },
1209     { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G, &ehl_pse1_sgmii1g_info) },
1210     { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5, &ehl_pse1_sgmii1g_info) },
1211     { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G, &tgl_sgmii1g_phy0_info) },
1212     { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0, &tgl_sgmii1g_phy0_info) },
1213     { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) },
1214     { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) },
1215     { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) },
1216     { PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &tgl_sgmii1g_phy0_info) },
1217     { PCI_DEVICE_DATA(INTEL, RPLP_SGMII1G, &tgl_sgmii1g_phy0_info) },
1218     {}
1219 };
1220 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
1221 
1222 static struct pci_driver intel_eth_pci_driver = {
1223     .name = "intel-eth-pci",
1224     .id_table = intel_eth_pci_id_table,
1225     .probe = intel_eth_pci_probe,
1226     .remove = intel_eth_pci_remove,
1227     .driver         = {
1228         .pm     = &intel_eth_pm_ops,
1229     },
1230 };
1231 
1232 module_pci_driver(intel_eth_pci_driver);
1233 
1234 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver");
1235 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>");
1236 MODULE_LICENSE("GPL v2");
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