stmicro/stmmac/dwmac-imx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * dwmac-imx.c - DWMAC Specific Glue layer for NXP imx8
0004  *
0005  * Copyright 2020 NXP
0006  *
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/gpio/consumer.h>
0011 #include <linux/kernel.h>
0012 #include <linux/mfd/syscon.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/of_device.h>
0016 #include <linux/of_net.h>
0017 #include <linux/phy.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/pm_wakeirq.h>
0020 #include <linux/regmap.h>
0021 #include <linux/slab.h>
0022 #include <linux/stmmac.h>
0023
0024 #include "stmmac_platform.h"
0025
0026 #define GPR_ENET_QOS_INTF_MODE_MASK GENMASK(21, 16)
0027 #define GPR_ENET_QOS_INTF_SEL_MII   (0x0 << 16)
0028 #define GPR_ENET_QOS_INTF_SEL_RMII  (0x4 << 16)
0029 #define GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 16)
0030 #define GPR_ENET_QOS_CLK_GEN_EN     (0x1 << 19)
0031 #define GPR_ENET_QOS_CLK_TX_CLK_SEL (0x1 << 20)
0032 #define GPR_ENET_QOS_RGMII_EN       (0x1 << 21)
0033
0034 struct imx_dwmac_ops {
0035     u32 addr_width;
0036     bool mac_rgmii_txclk_auto_adj;
0037
0038     int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat);
0039 };
0040
0041 struct imx_priv_data {
0042     struct device *dev;
0043     struct clk *clk_tx;
0044     struct clk *clk_mem;
0045     struct regmap *intf_regmap;
0046     u32 intf_reg_off;
0047     bool rmii_refclk_ext;
0048
0049     const struct imx_dwmac_ops *ops;
0050     struct plat_stmmacenet_data *plat_dat;
0051 };
0052
0053 static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
0054 {
0055     struct imx_priv_data *dwmac = plat_dat->bsp_priv;
0056     int val;
0057
0058     switch (plat_dat->interface) {
0059     case PHY_INTERFACE_MODE_MII:
0060         val = GPR_ENET_QOS_INTF_SEL_MII;
0061         break;
0062     case PHY_INTERFACE_MODE_RMII:
0063         val = GPR_ENET_QOS_INTF_SEL_RMII;
0064         val |= (dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL);
0065         break;
0066     case PHY_INTERFACE_MODE_RGMII:
0067     case PHY_INTERFACE_MODE_RGMII_ID:
0068     case PHY_INTERFACE_MODE_RGMII_RXID:
0069     case PHY_INTERFACE_MODE_RGMII_TXID:
0070         val = GPR_ENET_QOS_INTF_SEL_RGMII |
0071               GPR_ENET_QOS_RGMII_EN;
0072         break;
0073     default:
0074         pr_debug("imx dwmac doesn't support %d interface\n",
0075              plat_dat->interface);
0076         return -EINVAL;
0077     }
0078
0079     val |= GPR_ENET_QOS_CLK_GEN_EN;
0080     return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
0081                   GPR_ENET_QOS_INTF_MODE_MASK, val);
0082 };
0083
0084 static int
0085 imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
0086 {
0087     int ret = 0;
0088
0089     /* TBD: depends on imx8dxl scu interfaces to be upstreamed */
0090     return ret;
0091 }
0092
0093 static int imx_dwmac_clks_config(void *priv, bool enabled)
0094 {
0095     struct imx_priv_data *dwmac = priv;
0096     int ret = 0;
0097
0098     if (enabled) {
0099         ret = clk_prepare_enable(dwmac->clk_mem);
0100         if (ret) {
0101             dev_err(dwmac->dev, "mem clock enable failed\n");
0102             return ret;
0103         }
0104
0105         ret = clk_prepare_enable(dwmac->clk_tx);
0106         if (ret) {
0107             dev_err(dwmac->dev, "tx clock enable failed\n");
0108             clk_disable_unprepare(dwmac->clk_mem);
0109             return ret;
0110         }
0111     } else {
0112         clk_disable_unprepare(dwmac->clk_tx);
0113         clk_disable_unprepare(dwmac->clk_mem);
0114     }
0115
0116     return ret;
0117 }
0118
0119 static int imx_dwmac_init(struct platform_device *pdev, void *priv)
0120 {
0121     struct plat_stmmacenet_data *plat_dat;
0122     struct imx_priv_data *dwmac = priv;
0123     int ret;
0124
0125     plat_dat = dwmac->plat_dat;
0126
0127     if (dwmac->ops->set_intf_mode) {
0128         ret = dwmac->ops->set_intf_mode(plat_dat);
0129         if (ret)
0130             return ret;
0131     }
0132
0133     return 0;
0134 }
0135
0136 static void imx_dwmac_exit(struct platform_device *pdev, void *priv)
0137 {
0138     /* nothing to do now */
0139 }
0140
0141 static void imx_dwmac_fix_speed(void *priv, unsigned int speed)
0142 {
0143     struct plat_stmmacenet_data *plat_dat;
0144     struct imx_priv_data *dwmac = priv;
0145     unsigned long rate;
0146     int err;
0147
0148     plat_dat = dwmac->plat_dat;
0149
0150     if (dwmac->ops->mac_rgmii_txclk_auto_adj ||
0151         (plat_dat->interface == PHY_INTERFACE_MODE_RMII) ||
0152         (plat_dat->interface == PHY_INTERFACE_MODE_MII))
0153         return;
0154
0155     switch (speed) {
0156     case SPEED_1000:
0157         rate = 125000000;
0158         break;
0159     case SPEED_100:
0160         rate = 25000000;
0161         break;
0162     case SPEED_10:
0163         rate = 2500000;
0164         break;
0165     default:
0166         dev_err(dwmac->dev, "invalid speed %u\n", speed);
0167         return;
0168     }
0169
0170     err = clk_set_rate(dwmac->clk_tx, rate);
0171     if (err < 0)
0172         dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate);
0173 }
0174
0175 static int
0176 imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev)
0177 {
0178     struct device_node *np = dev->of_node;
0179     int err = 0;
0180
0181     if (of_get_property(np, "snps,rmii_refclk_ext", NULL))
0182         dwmac->rmii_refclk_ext = true;
0183
0184     dwmac->clk_tx = devm_clk_get(dev, "tx");
0185     if (IS_ERR(dwmac->clk_tx)) {
0186         dev_err(dev, "failed to get tx clock\n");
0187         return PTR_ERR(dwmac->clk_tx);
0188     }
0189
0190     dwmac->clk_mem = NULL;
0191     if (of_machine_is_compatible("fsl,imx8dxl")) {
0192         dwmac->clk_mem = devm_clk_get(dev, "mem");
0193         if (IS_ERR(dwmac->clk_mem)) {
0194             dev_err(dev, "failed to get mem clock\n");
0195             return PTR_ERR(dwmac->clk_mem);
0196         }
0197     }
0198
0199     if (of_machine_is_compatible("fsl,imx8mp")) {
0200         /* Binding doc describes the property:
0201            is required by i.MX8MP.
0202            is optional for i.MX8DXL.
0203          */
0204         dwmac->intf_regmap = syscon_regmap_lookup_by_phandle(np, "intf_mode");
0205         if (IS_ERR(dwmac->intf_regmap))
0206             return PTR_ERR(dwmac->intf_regmap);
0207
0208         err = of_property_read_u32_index(np, "intf_mode", 1, &dwmac->intf_reg_off);
0209         if (err) {
0210             dev_err(dev, "Can't get intf mode reg offset (%d)\n", err);
0211             return err;
0212         }
0213     }
0214
0215     return err;
0216 }
0217
0218 static int imx_dwmac_probe(struct platform_device *pdev)
0219 {
0220     struct plat_stmmacenet_data *plat_dat;
0221     struct stmmac_resources stmmac_res;
0222     struct imx_priv_data *dwmac;
0223     const struct imx_dwmac_ops *data;
0224     int ret;
0225
0226     ret = stmmac_get_platform_resources(pdev, &stmmac_res);
0227     if (ret)
0228         return ret;
0229
0230     dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
0231     if (!dwmac)
0232         return -ENOMEM;
0233
0234     plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
0235     if (IS_ERR(plat_dat))
0236         return PTR_ERR(plat_dat);
0237
0238     data = of_device_get_match_data(&pdev->dev);
0239     if (!data) {
0240         dev_err(&pdev->dev, "failed to get match data\n");
0241         ret = -EINVAL;
0242         goto err_match_data;
0243     }
0244
0245     dwmac->ops = data;
0246     dwmac->dev = &pdev->dev;
0247
0248     ret = imx_dwmac_parse_dt(dwmac, &pdev->dev);
0249     if (ret) {
0250         dev_err(&pdev->dev, "failed to parse OF data\n");
0251         goto err_parse_dt;
0252     }
0253
0254     plat_dat->addr64 = dwmac->ops->addr_width;
0255     plat_dat->init = imx_dwmac_init;
0256     plat_dat->exit = imx_dwmac_exit;
0257     plat_dat->clks_config = imx_dwmac_clks_config;
0258     plat_dat->fix_mac_speed = imx_dwmac_fix_speed;
0259     plat_dat->bsp_priv = dwmac;
0260     dwmac->plat_dat = plat_dat;
0261
0262     ret = imx_dwmac_clks_config(dwmac, true);
0263     if (ret)
0264         goto err_clks_config;
0265
0266     ret = imx_dwmac_init(pdev, dwmac);
0267     if (ret)
0268         goto err_dwmac_init;
0269
0270     ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
0271     if (ret)
0272         goto err_drv_probe;
0273
0274     return 0;
0275
0276 err_drv_probe:
0277     imx_dwmac_exit(pdev, plat_dat->bsp_priv);
0278 err_dwmac_init:
0279     imx_dwmac_clks_config(dwmac, false);
0280 err_clks_config:
0281 err_parse_dt:
0282 err_match_data:
0283     stmmac_remove_config_dt(pdev, plat_dat);
0284     return ret;
0285 }
0286
0287 static struct imx_dwmac_ops imx8mp_dwmac_data = {
0288     .addr_width = 34,
0289     .mac_rgmii_txclk_auto_adj = false,
0290     .set_intf_mode = imx8mp_set_intf_mode,
0291 };
0292
0293 static struct imx_dwmac_ops imx8dxl_dwmac_data = {
0294     .addr_width = 32,
0295     .mac_rgmii_txclk_auto_adj = true,
0296     .set_intf_mode = imx8dxl_set_intf_mode,
0297 };
0298
0299 static const struct of_device_id imx_dwmac_match[] = {
0300     { .compatible = "nxp,imx8mp-dwmac-eqos", .data = &imx8mp_dwmac_data },
0301     { .compatible = "nxp,imx8dxl-dwmac-eqos", .data = &imx8dxl_dwmac_data },
0302     { }
0303 };
0304 MODULE_DEVICE_TABLE(of, imx_dwmac_match);
0305
0306 static struct platform_driver imx_dwmac_driver = {
0307     .probe  = imx_dwmac_probe,
0308     .remove = stmmac_pltfr_remove,
0309     .driver = {
0310         .name           = "imx-dwmac",
0311         .pm     = &stmmac_pltfr_pm_ops,
0312         .of_match_table = imx_dwmac_match,
0313     },
0314 };
0315 module_platform_driver(imx_dwmac_driver);
0316
0317 MODULE_AUTHOR("NXP");
0318 MODULE_DESCRIPTION("NXP imx8 DWMAC Specific Glue layer");
0319 MODULE_LICENSE("GPL v2");