stmicro/stmmac/descs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*******************************************************************************
0003   Header File to describe the DMA descriptors and related definitions.
0004   This is for DWMAC100 and 1000 cores.
0005
0006
0007   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0008 *******************************************************************************/
0009
0010 #ifndef __DESCS_H__
0011 #define __DESCS_H__
0012
0013 #include <linux/bitops.h>
0014
0015 /* Normal receive descriptor defines */
0016
0017 /* RDES0 */
0018 #define RDES0_PAYLOAD_CSUM_ERR  BIT(0)
0019 #define RDES0_CRC_ERROR     BIT(1)
0020 #define RDES0_DRIBBLING     BIT(2)
0021 #define RDES0_MII_ERROR     BIT(3)
0022 #define RDES0_RECEIVE_WATCHDOG  BIT(4)
0023 #define RDES0_FRAME_TYPE    BIT(5)
0024 #define RDES0_COLLISION     BIT(6)
0025 #define RDES0_IPC_CSUM_ERROR    BIT(7)
0026 #define RDES0_LAST_DESCRIPTOR   BIT(8)
0027 #define RDES0_FIRST_DESCRIPTOR  BIT(9)
0028 #define RDES0_VLAN_TAG      BIT(10)
0029 #define RDES0_OVERFLOW_ERROR    BIT(11)
0030 #define RDES0_LENGTH_ERROR  BIT(12)
0031 #define RDES0_SA_FILTER_FAIL    BIT(13)
0032 #define RDES0_DESCRIPTOR_ERROR  BIT(14)
0033 #define RDES0_ERROR_SUMMARY BIT(15)
0034 #define RDES0_FRAME_LEN_MASK    GENMASK(29, 16)
0035 #define RDES0_FRAME_LEN_SHIFT   16
0036 #define RDES0_DA_FILTER_FAIL    BIT(30)
0037 #define RDES0_OWN       BIT(31)
0038             /* RDES1 */
0039 #define RDES1_BUFFER1_SIZE_MASK     GENMASK(10, 0)
0040 #define RDES1_BUFFER2_SIZE_MASK     GENMASK(21, 11)
0041 #define RDES1_BUFFER2_SIZE_SHIFT    11
0042 #define RDES1_SECOND_ADDRESS_CHAINED    BIT(24)
0043 #define RDES1_END_RING          BIT(25)
0044 #define RDES1_DISABLE_IC        BIT(31)
0045
0046 /* Enhanced receive descriptor defines */
0047
0048 /* RDES0 (similar to normal RDES) */
0049 #define  ERDES0_RX_MAC_ADDR BIT(0)
0050
0051 /* RDES1: completely differ from normal desc definitions */
0052 #define ERDES1_BUFFER1_SIZE_MASK    GENMASK(12, 0)
0053 #define ERDES1_SECOND_ADDRESS_CHAINED   BIT(14)
0054 #define ERDES1_END_RING         BIT(15)
0055 #define ERDES1_BUFFER2_SIZE_MASK    GENMASK(28, 16)
0056 #define ERDES1_BUFFER2_SIZE_SHIFT   16
0057 #define ERDES1_DISABLE_IC       BIT(31)
0058
0059 /* Normal transmit descriptor defines */
0060 /* TDES0 */
0061 #define TDES0_DEFERRED          BIT(0)
0062 #define TDES0_UNDERFLOW_ERROR       BIT(1)
0063 #define TDES0_EXCESSIVE_DEFERRAL    BIT(2)
0064 #define TDES0_COLLISION_COUNT_MASK  GENMASK(6, 3)
0065 #define TDES0_VLAN_FRAME        BIT(7)
0066 #define TDES0_EXCESSIVE_COLLISIONS  BIT(8)
0067 #define TDES0_LATE_COLLISION        BIT(9)
0068 #define TDES0_NO_CARRIER        BIT(10)
0069 #define TDES0_LOSS_CARRIER      BIT(11)
0070 #define TDES0_PAYLOAD_ERROR     BIT(12)
0071 #define TDES0_FRAME_FLUSHED     BIT(13)
0072 #define TDES0_JABBER_TIMEOUT        BIT(14)
0073 #define TDES0_ERROR_SUMMARY     BIT(15)
0074 #define TDES0_IP_HEADER_ERROR       BIT(16)
0075 #define TDES0_TIME_STAMP_STATUS     BIT(17)
0076 #define TDES0_OWN           ((u32)BIT(31))  /* silence sparse */
0077 /* TDES1 */
0078 #define TDES1_BUFFER1_SIZE_MASK     GENMASK(10, 0)
0079 #define TDES1_BUFFER2_SIZE_MASK     GENMASK(21, 11)
0080 #define TDES1_BUFFER2_SIZE_SHIFT    11
0081 #define TDES1_TIME_STAMP_ENABLE     BIT(22)
0082 #define TDES1_DISABLE_PADDING       BIT(23)
0083 #define TDES1_SECOND_ADDRESS_CHAINED    BIT(24)
0084 #define TDES1_END_RING          BIT(25)
0085 #define TDES1_CRC_DISABLE       BIT(26)
0086 #define TDES1_CHECKSUM_INSERTION_MASK   GENMASK(28, 27)
0087 #define TDES1_CHECKSUM_INSERTION_SHIFT  27
0088 #define TDES1_FIRST_SEGMENT     BIT(29)
0089 #define TDES1_LAST_SEGMENT      BIT(30)
0090 #define TDES1_INTERRUPT         BIT(31)
0091
0092 /* Enhanced transmit descriptor defines */
0093 /* TDES0 */
0094 #define ETDES0_DEFERRED         BIT(0)
0095 #define ETDES0_UNDERFLOW_ERROR      BIT(1)
0096 #define ETDES0_EXCESSIVE_DEFERRAL   BIT(2)
0097 #define ETDES0_COLLISION_COUNT_MASK GENMASK(6, 3)
0098 #define ETDES0_VLAN_FRAME       BIT(7)
0099 #define ETDES0_EXCESSIVE_COLLISIONS BIT(8)
0100 #define ETDES0_LATE_COLLISION       BIT(9)
0101 #define ETDES0_NO_CARRIER       BIT(10)
0102 #define ETDES0_LOSS_CARRIER     BIT(11)
0103 #define ETDES0_PAYLOAD_ERROR        BIT(12)
0104 #define ETDES0_FRAME_FLUSHED        BIT(13)
0105 #define ETDES0_JABBER_TIMEOUT       BIT(14)
0106 #define ETDES0_ERROR_SUMMARY        BIT(15)
0107 #define ETDES0_IP_HEADER_ERROR      BIT(16)
0108 #define ETDES0_TIME_STAMP_STATUS    BIT(17)
0109 #define ETDES0_SECOND_ADDRESS_CHAINED   BIT(20)
0110 #define ETDES0_END_RING         BIT(21)
0111 #define ETDES0_CHECKSUM_INSERTION_MASK  GENMASK(23, 22)
0112 #define ETDES0_CHECKSUM_INSERTION_SHIFT 22
0113 #define ETDES0_TIME_STAMP_ENABLE    BIT(25)
0114 #define ETDES0_DISABLE_PADDING      BIT(26)
0115 #define ETDES0_CRC_DISABLE      BIT(27)
0116 #define ETDES0_FIRST_SEGMENT        BIT(28)
0117 #define ETDES0_LAST_SEGMENT     BIT(29)
0118 #define ETDES0_INTERRUPT        BIT(30)
0119 #define ETDES0_OWN          ((u32)BIT(31))  /* silence sparse */
0120 /* TDES1 */
0121 #define ETDES1_BUFFER1_SIZE_MASK    GENMASK(12, 0)
0122 #define ETDES1_BUFFER2_SIZE_MASK    GENMASK(28, 16)
0123 #define ETDES1_BUFFER2_SIZE_SHIFT   16
0124
0125 /* Extended Receive descriptor definitions */
0126 #define ERDES4_IP_PAYLOAD_TYPE_MASK GENMASK(6, 2)
0127 #define ERDES4_IP_HDR_ERR       BIT(3)
0128 #define ERDES4_IP_PAYLOAD_ERR       BIT(4)
0129 #define ERDES4_IP_CSUM_BYPASSED     BIT(5)
0130 #define ERDES4_IPV4_PKT_RCVD        BIT(6)
0131 #define ERDES4_IPV6_PKT_RCVD        BIT(7)
0132 #define ERDES4_MSG_TYPE_MASK        GENMASK(11, 8)
0133 #define ERDES4_PTP_FRAME_TYPE       BIT(12)
0134 #define ERDES4_PTP_VER          BIT(13)
0135 #define ERDES4_TIMESTAMP_DROPPED    BIT(14)
0136 #define ERDES4_AV_PKT_RCVD      BIT(16)
0137 #define ERDES4_AV_TAGGED_PKT_RCVD   BIT(17)
0138 #define ERDES4_VLAN_TAG_PRI_VAL_MASK    GENMASK(20, 18)
0139 #define ERDES4_L3_FILTER_MATCH      BIT(24)
0140 #define ERDES4_L4_FILTER_MATCH      BIT(25)
0141 #define ERDES4_L3_L4_FILT_NO_MATCH_MASK GENMASK(27, 26)
0142
0143 /* Extended RDES4 message type definitions */
0144 #define RDES_EXT_NO_PTP         0x0
0145 #define RDES_EXT_SYNC           0x1
0146 #define RDES_EXT_FOLLOW_UP      0x2
0147 #define RDES_EXT_DELAY_REQ      0x3
0148 #define RDES_EXT_DELAY_RESP     0x4
0149 #define RDES_EXT_PDELAY_REQ     0x5
0150 #define RDES_EXT_PDELAY_RESP        0x6
0151 #define RDES_EXT_PDELAY_FOLLOW_UP   0x7
0152 #define RDES_PTP_ANNOUNCE       0x8
0153 #define RDES_PTP_MANAGEMENT     0x9
0154 #define RDES_PTP_SIGNALING      0xa
0155 #define RDES_PTP_PKT_RESERVED_TYPE  0xf
0156
0157 /* Basic descriptor structure for normal and alternate descriptors */
0158 struct dma_desc {
0159     __le32 des0;
0160     __le32 des1;
0161     __le32 des2;
0162     __le32 des3;
0163 };
0164
0165 /* Extended descriptor structure (e.g. >= databook 3.50a) */
0166 struct dma_extended_desc {
0167     struct dma_desc basic;  /* Basic descriptors */
0168     __le32 des4;    /* Extended Status */
0169     __le32 des5;    /* Reserved */
0170     __le32 des6;    /* Tx/Rx Timestamp Low */
0171     __le32 des7;    /* Tx/Rx Timestamp High */
0172 };
0173
0174 /* Enhanced descriptor for TBS */
0175 struct dma_edesc {
0176     __le32 des4;
0177     __le32 des5;
0178     __le32 des6;
0179     __le32 des7;
0180     struct dma_desc basic;
0181 };
0182
0183 /* Transmit checksum insertion control */
0184 #define TX_CIC_FULL 3   /* Include IP header and pseudoheader */
0185
0186 #endif /* __DESCS_H__ */