stmicro/stmmac/common.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*******************************************************************************
0003   STMMAC Common Header File
0004
0005   Copyright (C) 2007-2009  STMicroelectronics Ltd
0006
0007
0008   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0009 *******************************************************************************/
0010
0011 #ifndef __COMMON_H__
0012 #define __COMMON_H__
0013
0014 #include <linux/etherdevice.h>
0015 #include <linux/netdevice.h>
0016 #include <linux/stmmac.h>
0017 #include <linux/phy.h>
0018 #include <linux/pcs/pcs-xpcs.h>
0019 #include <linux/module.h>
0020 #if IS_ENABLED(CONFIG_VLAN_8021Q)
0021 #define STMMAC_VLAN_TAG_USED
0022 #include <linux/if_vlan.h>
0023 #endif
0024
0025 #include "descs.h"
0026 #include "hwif.h"
0027 #include "mmc.h"
0028
0029 /* Synopsys Core versions */
0030 #define DWMAC_CORE_3_40     0x34
0031 #define DWMAC_CORE_3_50     0x35
0032 #define DWMAC_CORE_4_00     0x40
0033 #define DWMAC_CORE_4_10     0x41
0034 #define DWMAC_CORE_5_00     0x50
0035 #define DWMAC_CORE_5_10     0x51
0036 #define DWMAC_CORE_5_20     0x52
0037 #define DWXGMAC_CORE_2_10   0x21
0038 #define DWXLGMAC_CORE_2_00  0x20
0039
0040 /* Device ID */
0041 #define DWXGMAC_ID      0x76
0042 #define DWXLGMAC_ID     0x27
0043
0044 #define STMMAC_CHAN0    0   /* Always supported and default for all chips */
0045
0046 /* TX and RX Descriptor Length, these need to be power of two.
0047  * TX descriptor length less than 64 may cause transmit queue timed out error.
0048  * RX descriptor length less than 64 may cause inconsistent Rx chain error.
0049  */
0050 #define DMA_MIN_TX_SIZE     64
0051 #define DMA_MAX_TX_SIZE     1024
0052 #define DMA_DEFAULT_TX_SIZE 512
0053 #define DMA_MIN_RX_SIZE     64
0054 #define DMA_MAX_RX_SIZE     1024
0055 #define DMA_DEFAULT_RX_SIZE 512
0056 #define STMMAC_GET_ENTRY(x, size)   ((x + 1) & (size - 1))
0057
0058 #undef FRAME_FILTER_DEBUG
0059 /* #define FRAME_FILTER_DEBUG */
0060
0061 struct stmmac_txq_stats {
0062     unsigned long tx_pkt_n;
0063     unsigned long tx_normal_irq_n;
0064 };
0065
0066 struct stmmac_rxq_stats {
0067     unsigned long rx_pkt_n;
0068     unsigned long rx_normal_irq_n;
0069 };
0070
0071 /* Extra statistic and debug information exposed by ethtool */
0072 struct stmmac_extra_stats {
0073     /* Transmit errors */
0074     unsigned long tx_underflow ____cacheline_aligned;
0075     unsigned long tx_carrier;
0076     unsigned long tx_losscarrier;
0077     unsigned long vlan_tag;
0078     unsigned long tx_deferred;
0079     unsigned long tx_vlan;
0080     unsigned long tx_jabber;
0081     unsigned long tx_frame_flushed;
0082     unsigned long tx_payload_error;
0083     unsigned long tx_ip_header_error;
0084     /* Receive errors */
0085     unsigned long rx_desc;
0086     unsigned long sa_filter_fail;
0087     unsigned long overflow_error;
0088     unsigned long ipc_csum_error;
0089     unsigned long rx_collision;
0090     unsigned long rx_crc_errors;
0091     unsigned long dribbling_bit;
0092     unsigned long rx_length;
0093     unsigned long rx_mii;
0094     unsigned long rx_multicast;
0095     unsigned long rx_gmac_overflow;
0096     unsigned long rx_watchdog;
0097     unsigned long da_rx_filter_fail;
0098     unsigned long sa_rx_filter_fail;
0099     unsigned long rx_missed_cntr;
0100     unsigned long rx_overflow_cntr;
0101     unsigned long rx_vlan;
0102     unsigned long rx_split_hdr_pkt_n;
0103     /* Tx/Rx IRQ error info */
0104     unsigned long tx_undeflow_irq;
0105     unsigned long tx_process_stopped_irq;
0106     unsigned long tx_jabber_irq;
0107     unsigned long rx_overflow_irq;
0108     unsigned long rx_buf_unav_irq;
0109     unsigned long rx_process_stopped_irq;
0110     unsigned long rx_watchdog_irq;
0111     unsigned long tx_early_irq;
0112     unsigned long fatal_bus_error_irq;
0113     /* Tx/Rx IRQ Events */
0114     unsigned long rx_early_irq;
0115     unsigned long threshold;
0116     unsigned long tx_pkt_n;
0117     unsigned long rx_pkt_n;
0118     unsigned long normal_irq_n;
0119     unsigned long rx_normal_irq_n;
0120     unsigned long napi_poll;
0121     unsigned long tx_normal_irq_n;
0122     unsigned long tx_clean;
0123     unsigned long tx_set_ic_bit;
0124     unsigned long irq_receive_pmt_irq_n;
0125     /* MMC info */
0126     unsigned long mmc_tx_irq_n;
0127     unsigned long mmc_rx_irq_n;
0128     unsigned long mmc_rx_csum_offload_irq_n;
0129     /* EEE */
0130     unsigned long irq_tx_path_in_lpi_mode_n;
0131     unsigned long irq_tx_path_exit_lpi_mode_n;
0132     unsigned long irq_rx_path_in_lpi_mode_n;
0133     unsigned long irq_rx_path_exit_lpi_mode_n;
0134     unsigned long phy_eee_wakeup_error_n;
0135     /* Extended RDES status */
0136     unsigned long ip_hdr_err;
0137     unsigned long ip_payload_err;
0138     unsigned long ip_csum_bypassed;
0139     unsigned long ipv4_pkt_rcvd;
0140     unsigned long ipv6_pkt_rcvd;
0141     unsigned long no_ptp_rx_msg_type_ext;
0142     unsigned long ptp_rx_msg_type_sync;
0143     unsigned long ptp_rx_msg_type_follow_up;
0144     unsigned long ptp_rx_msg_type_delay_req;
0145     unsigned long ptp_rx_msg_type_delay_resp;
0146     unsigned long ptp_rx_msg_type_pdelay_req;
0147     unsigned long ptp_rx_msg_type_pdelay_resp;
0148     unsigned long ptp_rx_msg_type_pdelay_follow_up;
0149     unsigned long ptp_rx_msg_type_announce;
0150     unsigned long ptp_rx_msg_type_management;
0151     unsigned long ptp_rx_msg_pkt_reserved_type;
0152     unsigned long ptp_frame_type;
0153     unsigned long ptp_ver;
0154     unsigned long timestamp_dropped;
0155     unsigned long av_pkt_rcvd;
0156     unsigned long av_tagged_pkt_rcvd;
0157     unsigned long vlan_tag_priority_val;
0158     unsigned long l3_filter_match;
0159     unsigned long l4_filter_match;
0160     unsigned long l3_l4_filter_no_match;
0161     /* PCS */
0162     unsigned long irq_pcs_ane_n;
0163     unsigned long irq_pcs_link_n;
0164     unsigned long irq_rgmii_n;
0165     unsigned long pcs_link;
0166     unsigned long pcs_duplex;
0167     unsigned long pcs_speed;
0168     /* debug register */
0169     unsigned long mtl_tx_status_fifo_full;
0170     unsigned long mtl_tx_fifo_not_empty;
0171     unsigned long mmtl_fifo_ctrl;
0172     unsigned long mtl_tx_fifo_read_ctrl_write;
0173     unsigned long mtl_tx_fifo_read_ctrl_wait;
0174     unsigned long mtl_tx_fifo_read_ctrl_read;
0175     unsigned long mtl_tx_fifo_read_ctrl_idle;
0176     unsigned long mac_tx_in_pause;
0177     unsigned long mac_tx_frame_ctrl_xfer;
0178     unsigned long mac_tx_frame_ctrl_idle;
0179     unsigned long mac_tx_frame_ctrl_wait;
0180     unsigned long mac_tx_frame_ctrl_pause;
0181     unsigned long mac_gmii_tx_proto_engine;
0182     unsigned long mtl_rx_fifo_fill_level_full;
0183     unsigned long mtl_rx_fifo_fill_above_thresh;
0184     unsigned long mtl_rx_fifo_fill_below_thresh;
0185     unsigned long mtl_rx_fifo_fill_level_empty;
0186     unsigned long mtl_rx_fifo_read_ctrl_flush;
0187     unsigned long mtl_rx_fifo_read_ctrl_read_data;
0188     unsigned long mtl_rx_fifo_read_ctrl_status;
0189     unsigned long mtl_rx_fifo_read_ctrl_idle;
0190     unsigned long mtl_rx_fifo_ctrl_active;
0191     unsigned long mac_rx_frame_ctrl_fifo;
0192     unsigned long mac_gmii_rx_proto_engine;
0193     /* TSO */
0194     unsigned long tx_tso_frames;
0195     unsigned long tx_tso_nfrags;
0196     /* EST */
0197     unsigned long mtl_est_cgce;
0198     unsigned long mtl_est_hlbs;
0199     unsigned long mtl_est_hlbf;
0200     unsigned long mtl_est_btre;
0201     unsigned long mtl_est_btrlm;
0202     /* per queue statistics */
0203     struct stmmac_txq_stats txq_stats[MTL_MAX_TX_QUEUES];
0204     struct stmmac_rxq_stats rxq_stats[MTL_MAX_RX_QUEUES];
0205 };
0206
0207 /* Safety Feature statistics exposed by ethtool */
0208 struct stmmac_safety_stats {
0209     unsigned long mac_errors[32];
0210     unsigned long mtl_errors[32];
0211     unsigned long dma_errors[32];
0212 };
0213
0214 /* Number of fields in Safety Stats */
0215 #define STMMAC_SAFETY_FEAT_SIZE \
0216     (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
0217
0218 /* CSR Frequency Access Defines*/
0219 #define CSR_F_35M   35000000
0220 #define CSR_F_60M   60000000
0221 #define CSR_F_100M  100000000
0222 #define CSR_F_150M  150000000
0223 #define CSR_F_250M  250000000
0224 #define CSR_F_300M  300000000
0225
0226 #define MAC_CSR_H_FRQ_MASK  0x20
0227
0228 #define HASH_TABLE_SIZE 64
0229 #define PAUSE_TIME 0xffff
0230
0231 /* Flow Control defines */
0232 #define FLOW_OFF    0
0233 #define FLOW_RX     1
0234 #define FLOW_TX     2
0235 #define FLOW_AUTO   (FLOW_TX | FLOW_RX)
0236
0237 /* PCS defines */
0238 #define STMMAC_PCS_RGMII    (1 << 0)
0239 #define STMMAC_PCS_SGMII    (1 << 1)
0240 #define STMMAC_PCS_TBI      (1 << 2)
0241 #define STMMAC_PCS_RTBI     (1 << 3)
0242
0243 #define SF_DMA_MODE 1       /* DMA STORE-AND-FORWARD Operation Mode */
0244
0245 /* DAM HW feature register fields */
0246 #define DMA_HW_FEAT_MIISEL  0x00000001  /* 10/100 Mbps Support */
0247 #define DMA_HW_FEAT_GMIISEL 0x00000002  /* 1000 Mbps Support */
0248 #define DMA_HW_FEAT_HDSEL   0x00000004  /* Half-Duplex Support */
0249 #define DMA_HW_FEAT_EXTHASHEN   0x00000008  /* Expanded DA Hash Filter */
0250 #define DMA_HW_FEAT_HASHSEL 0x00000010  /* HASH Filter */
0251 #define DMA_HW_FEAT_ADDMAC  0x00000020  /* Multiple MAC Addr Reg */
0252 #define DMA_HW_FEAT_PCSSEL  0x00000040  /* PCS registers */
0253 #define DMA_HW_FEAT_L3L4FLTREN  0x00000080  /* Layer 3 & Layer 4 Feature */
0254 #define DMA_HW_FEAT_SMASEL  0x00000100  /* SMA(MDIO) Interface */
0255 #define DMA_HW_FEAT_RWKSEL  0x00000200  /* PMT Remote Wakeup */
0256 #define DMA_HW_FEAT_MGKSEL  0x00000400  /* PMT Magic Packet */
0257 #define DMA_HW_FEAT_MMCSEL  0x00000800  /* RMON Module */
0258 #define DMA_HW_FEAT_TSVER1SEL   0x00001000  /* Only IEEE 1588-2002 */
0259 #define DMA_HW_FEAT_TSVER2SEL   0x00002000  /* IEEE 1588-2008 PTPv2 */
0260 #define DMA_HW_FEAT_EEESEL  0x00004000  /* Energy Efficient Ethernet */
0261 #define DMA_HW_FEAT_AVSEL   0x00008000  /* AV Feature */
0262 #define DMA_HW_FEAT_TXCOESEL    0x00010000  /* Checksum Offload in Tx */
0263 #define DMA_HW_FEAT_RXTYP1COE   0x00020000  /* IP COE (Type 1) in Rx */
0264 #define DMA_HW_FEAT_RXTYP2COE   0x00040000  /* IP COE (Type 2) in Rx */
0265 #define DMA_HW_FEAT_RXFIFOSIZE  0x00080000  /* Rx FIFO > 2048 Bytes */
0266 #define DMA_HW_FEAT_RXCHCNT 0x00300000  /* No. additional Rx Channels */
0267 #define DMA_HW_FEAT_TXCHCNT 0x00c00000  /* No. additional Tx Channels */
0268 #define DMA_HW_FEAT_ENHDESSEL   0x01000000  /* Alternate Descriptor */
0269 /* Timestamping with Internal System Time */
0270 #define DMA_HW_FEAT_INTTSEN 0x02000000
0271 #define DMA_HW_FEAT_FLEXIPPSEN  0x04000000  /* Flexible PPS Output */
0272 #define DMA_HW_FEAT_SAVLANINS   0x08000000  /* Source Addr or VLAN */
0273 #define DMA_HW_FEAT_ACTPHYIF    0x70000000  /* Active/selected PHY iface */
0274 #define DEFAULT_DMA_PBL     8
0275
0276 /* MSI defines */
0277 #define STMMAC_MSI_VEC_MAX  32
0278
0279 /* PCS status and mask defines */
0280 #define PCS_ANE_IRQ     BIT(2)  /* PCS Auto-Negotiation */
0281 #define PCS_LINK_IRQ        BIT(1)  /* PCS Link */
0282 #define PCS_RGSMIIIS_IRQ    BIT(0)  /* RGMII or SMII Interrupt */
0283
0284 /* Max/Min RI Watchdog Timer count value */
0285 #define MAX_DMA_RIWT        0xff
0286 #define MIN_DMA_RIWT        0x10
0287 #define DEF_DMA_RIWT        0xa0
0288 /* Tx coalesce parameters */
0289 #define STMMAC_COAL_TX_TIMER    1000
0290 #define STMMAC_MAX_COAL_TX_TICK 100000
0291 #define STMMAC_TX_MAX_FRAMES    256
0292 #define STMMAC_TX_FRAMES    25
0293 #define STMMAC_RX_FRAMES    0
0294
0295 /* Packets types */
0296 enum packets_types {
0297     PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
0298     PACKET_PTPQ = 0x2, /* PTP Packets */
0299     PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
0300     PACKET_UPQ = 0x4, /* Untagged Packets */
0301     PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
0302 };
0303
0304 /* Rx IPC status */
0305 enum rx_frame_status {
0306     good_frame = 0x0,
0307     discard_frame = 0x1,
0308     csum_none = 0x2,
0309     llc_snap = 0x4,
0310     dma_own = 0x8,
0311     rx_not_ls = 0x10,
0312 };
0313
0314 /* Tx status */
0315 enum tx_frame_status {
0316     tx_done = 0x0,
0317     tx_not_ls = 0x1,
0318     tx_err = 0x2,
0319     tx_dma_own = 0x4,
0320     tx_err_bump_tc = 0x8,
0321 };
0322
0323 enum dma_irq_status {
0324     tx_hard_error = 0x1,
0325     tx_hard_error_bump_tc = 0x2,
0326     handle_rx = 0x4,
0327     handle_tx = 0x8,
0328 };
0329
0330 enum dma_irq_dir {
0331     DMA_DIR_RX = 0x1,
0332     DMA_DIR_TX = 0x2,
0333     DMA_DIR_RXTX = 0x3,
0334 };
0335
0336 enum request_irq_err {
0337     REQ_IRQ_ERR_ALL,
0338     REQ_IRQ_ERR_TX,
0339     REQ_IRQ_ERR_RX,
0340     REQ_IRQ_ERR_SFTY_UE,
0341     REQ_IRQ_ERR_SFTY_CE,
0342     REQ_IRQ_ERR_LPI,
0343     REQ_IRQ_ERR_WOL,
0344     REQ_IRQ_ERR_MAC,
0345     REQ_IRQ_ERR_NO,
0346 };
0347
0348 /* EEE and LPI defines */
0349 #define CORE_IRQ_TX_PATH_IN_LPI_MODE    (1 << 0)
0350 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE  (1 << 1)
0351 #define CORE_IRQ_RX_PATH_IN_LPI_MODE    (1 << 2)
0352 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE  (1 << 3)
0353
0354 /* FPE defines */
0355 #define FPE_EVENT_UNKNOWN       0
0356 #define FPE_EVENT_TRSP          BIT(0)
0357 #define FPE_EVENT_TVER          BIT(1)
0358 #define FPE_EVENT_RRSP          BIT(2)
0359 #define FPE_EVENT_RVER          BIT(3)
0360
0361 #define CORE_IRQ_MTL_RX_OVERFLOW    BIT(8)
0362
0363 /* Physical Coding Sublayer */
0364 struct rgmii_adv {
0365     unsigned int pause;
0366     unsigned int duplex;
0367     unsigned int lp_pause;
0368     unsigned int lp_duplex;
0369 };
0370
0371 #define STMMAC_PCS_PAUSE    1
0372 #define STMMAC_PCS_ASYM_PAUSE   2
0373
0374 /* DMA HW capabilities */
0375 struct dma_features {
0376     unsigned int mbps_10_100;
0377     unsigned int mbps_1000;
0378     unsigned int half_duplex;
0379     unsigned int hash_filter;
0380     unsigned int multi_addr;
0381     unsigned int pcs;
0382     unsigned int sma_mdio;
0383     unsigned int pmt_remote_wake_up;
0384     unsigned int pmt_magic_frame;
0385     unsigned int rmon;
0386     /* IEEE 1588-2002 */
0387     unsigned int time_stamp;
0388     /* IEEE 1588-2008 */
0389     unsigned int atime_stamp;
0390     /* 802.3az - Energy-Efficient Ethernet (EEE) */
0391     unsigned int eee;
0392     unsigned int av;
0393     unsigned int hash_tb_sz;
0394     unsigned int tsoen;
0395     /* TX and RX csum */
0396     unsigned int tx_coe;
0397     unsigned int rx_coe;
0398     unsigned int rx_coe_type1;
0399     unsigned int rx_coe_type2;
0400     unsigned int rxfifo_over_2048;
0401     /* TX and RX number of channels */
0402     unsigned int number_rx_channel;
0403     unsigned int number_tx_channel;
0404     /* TX and RX number of queues */
0405     unsigned int number_rx_queues;
0406     unsigned int number_tx_queues;
0407     /* PPS output */
0408     unsigned int pps_out_num;
0409     /* Alternate (enhanced) DESC mode */
0410     unsigned int enh_desc;
0411     /* TX and RX FIFO sizes */
0412     unsigned int tx_fifo_size;
0413     unsigned int rx_fifo_size;
0414     /* Automotive Safety Package */
0415     unsigned int asp;
0416     /* RX Parser */
0417     unsigned int frpsel;
0418     unsigned int frpbs;
0419     unsigned int frpes;
0420     unsigned int addr64;
0421     unsigned int rssen;
0422     unsigned int vlhash;
0423     unsigned int sphen;
0424     unsigned int vlins;
0425     unsigned int dvlan;
0426     unsigned int l3l4fnum;
0427     unsigned int arpoffsel;
0428     /* TSN Features */
0429     unsigned int estwid;
0430     unsigned int estdep;
0431     unsigned int estsel;
0432     unsigned int fpesel;
0433     unsigned int tbssel;
0434     /* Numbers of Auxiliary Snapshot Inputs */
0435     unsigned int aux_snapshot_n;
0436 };
0437
0438 /* RX Buffer size must be multiple of 4/8/16 bytes */
0439 #define BUF_SIZE_16KiB 16368
0440 #define BUF_SIZE_8KiB 8188
0441 #define BUF_SIZE_4KiB 4096
0442 #define BUF_SIZE_2KiB 2048
0443
0444 /* Power Down and WOL */
0445 #define PMT_NOT_SUPPORTED 0
0446 #define PMT_SUPPORTED 1
0447
0448 /* Common MAC defines */
0449 #define MAC_CTRL_REG        0x00000000  /* MAC Control */
0450 #define MAC_ENABLE_TX       0x00000008  /* Transmitter Enable */
0451 #define MAC_ENABLE_RX       0x00000004  /* Receiver Enable */
0452
0453 /* Default LPI timers */
0454 #define STMMAC_DEFAULT_LIT_LS   0x3E8
0455 #define STMMAC_DEFAULT_TWT_LS   0x1E
0456 #define STMMAC_ET_MAX       0xFFFFF
0457
0458 #define STMMAC_CHAIN_MODE   0x1
0459 #define STMMAC_RING_MODE    0x2
0460
0461 #define JUMBO_LEN       9000
0462
0463 /* Receive Side Scaling */
0464 #define STMMAC_RSS_HASH_KEY_SIZE    40
0465 #define STMMAC_RSS_MAX_TABLE_SIZE   256
0466
0467 /* VLAN */
0468 #define STMMAC_VLAN_NONE    0x0
0469 #define STMMAC_VLAN_REMOVE  0x1
0470 #define STMMAC_VLAN_INSERT  0x2
0471 #define STMMAC_VLAN_REPLACE 0x3
0472
0473 extern const struct stmmac_desc_ops enh_desc_ops;
0474 extern const struct stmmac_desc_ops ndesc_ops;
0475
0476 struct mac_device_info;
0477
0478 extern const struct stmmac_hwtimestamp stmmac_ptp;
0479 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
0480
0481 struct mac_link {
0482     u32 speed_mask;
0483     u32 speed10;
0484     u32 speed100;
0485     u32 speed1000;
0486     u32 speed2500;
0487     u32 duplex;
0488     struct {
0489         u32 speed2500;
0490         u32 speed5000;
0491         u32 speed10000;
0492     } xgmii;
0493     struct {
0494         u32 speed25000;
0495         u32 speed40000;
0496         u32 speed50000;
0497         u32 speed100000;
0498     } xlgmii;
0499 };
0500
0501 struct mii_regs {
0502     unsigned int addr;  /* MII Address */
0503     unsigned int data;  /* MII Data */
0504     unsigned int addr_shift;    /* MII address shift */
0505     unsigned int reg_shift;     /* MII reg shift */
0506     unsigned int addr_mask;     /* MII address mask */
0507     unsigned int reg_mask;      /* MII reg mask */
0508     unsigned int clk_csr_shift;
0509     unsigned int clk_csr_mask;
0510 };
0511
0512 struct mac_device_info {
0513     const struct stmmac_ops *mac;
0514     const struct stmmac_desc_ops *desc;
0515     const struct stmmac_dma_ops *dma;
0516     const struct stmmac_mode_ops *mode;
0517     const struct stmmac_hwtimestamp *ptp;
0518     const struct stmmac_tc_ops *tc;
0519     const struct stmmac_mmc_ops *mmc;
0520     struct dw_xpcs *xpcs;
0521     struct mii_regs mii;    /* MII register Addresses */
0522     struct mac_link link;
0523     void __iomem *pcsr;     /* vpointer to device CSRs */
0524     unsigned int multicast_filter_bins;
0525     unsigned int unicast_filter_entries;
0526     unsigned int mcast_bits_log2;
0527     unsigned int rx_csum;
0528     unsigned int pcs;
0529     unsigned int pmt;
0530     unsigned int ps;
0531     unsigned int xlgmac;
0532     unsigned int num_vlan;
0533     u32 vlan_filter[32];
0534     unsigned int promisc;
0535     bool vlan_fail_q_en;
0536     u8 vlan_fail_q;
0537 };
0538
0539 struct stmmac_rx_routing {
0540     u32 reg_mask;
0541     u32 reg_shift;
0542 };
0543
0544 int dwmac100_setup(struct stmmac_priv *priv);
0545 int dwmac1000_setup(struct stmmac_priv *priv);
0546 int dwmac4_setup(struct stmmac_priv *priv);
0547 int dwxgmac2_setup(struct stmmac_priv *priv);
0548 int dwxlgmac2_setup(struct stmmac_priv *priv);
0549
0550 void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
0551              unsigned int high, unsigned int low);
0552 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
0553              unsigned int high, unsigned int low);
0554 void stmmac_set_mac(void __iomem *ioaddr, bool enable);
0555
0556 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
0557                 unsigned int high, unsigned int low);
0558 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
0559                 unsigned int high, unsigned int low);
0560 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
0561
0562 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
0563
0564 extern const struct stmmac_mode_ops ring_mode_ops;
0565 extern const struct stmmac_mode_ops chain_mode_ops;
0566 extern const struct stmmac_desc_ops dwmac4_desc_ops;
0567
0568 #endif /* __COMMON_H__ */