stmicro/stmmac/altr_tse_pcs.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright Altera Corporation (C) 2016. All rights reserved.
0003  *
0004  * Author: Tien Hock Loh <thloh@altera.com>
0005  */
0006
0007 #include <linux/mfd/syscon.h>
0008 #include <linux/of.h>
0009 #include <linux/of_address.h>
0010 #include <linux/of_net.h>
0011 #include <linux/phy.h>
0012 #include <linux/regmap.h>
0013 #include <linux/reset.h>
0014 #include <linux/stmmac.h>
0015
0016 #include "stmmac.h"
0017 #include "stmmac_platform.h"
0018 #include "altr_tse_pcs.h"
0019
0020 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII    0
0021 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII       BIT(1)
0022 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII        BIT(2)
0023 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH        2
0024 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK         GENMASK(1, 0)
0025
0026 #define TSE_PCS_CONTROL_AN_EN_MASK          BIT(12)
0027 #define TSE_PCS_CONTROL_REG             0x00
0028 #define TSE_PCS_CONTROL_RESTART_AN_MASK         BIT(9)
0029 #define TSE_PCS_CTRL_AUTONEG_SGMII          0x1140
0030 #define TSE_PCS_IF_MODE_REG             0x28
0031 #define TSE_PCS_LINK_TIMER_0_REG            0x24
0032 #define TSE_PCS_LINK_TIMER_1_REG            0x26
0033 #define TSE_PCS_SIZE                    0x40
0034 #define TSE_PCS_STATUS_AN_COMPLETED_MASK        BIT(5)
0035 #define TSE_PCS_STATUS_LINK_MASK            0x0004
0036 #define TSE_PCS_STATUS_REG              0x02
0037 #define TSE_PCS_SGMII_SPEED_1000            BIT(3)
0038 #define TSE_PCS_SGMII_SPEED_100             BIT(2)
0039 #define TSE_PCS_SGMII_SPEED_10              0x0
0040 #define TSE_PCS_SW_RST_MASK             0x8000
0041 #define TSE_PCS_PARTNER_ABILITY_REG         0x0A
0042 #define TSE_PCS_PARTNER_DUPLEX_FULL         0x1000
0043 #define TSE_PCS_PARTNER_DUPLEX_HALF         0x0000
0044 #define TSE_PCS_PARTNER_DUPLEX_MASK         0x1000
0045 #define TSE_PCS_PARTNER_SPEED_MASK          GENMASK(11, 10)
0046 #define TSE_PCS_PARTNER_SPEED_1000          BIT(11)
0047 #define TSE_PCS_PARTNER_SPEED_100           BIT(10)
0048 #define TSE_PCS_PARTNER_SPEED_10            0x0000
0049 #define TSE_PCS_PARTNER_SPEED_1000          BIT(11)
0050 #define TSE_PCS_PARTNER_SPEED_100           BIT(10)
0051 #define TSE_PCS_PARTNER_SPEED_10            0x0000
0052 #define TSE_PCS_SGMII_SPEED_MASK            GENMASK(3, 2)
0053 #define TSE_PCS_SGMII_LINK_TIMER_0          0x0D40
0054 #define TSE_PCS_SGMII_LINK_TIMER_1          0x0003
0055 #define TSE_PCS_SW_RESET_TIMEOUT            100
0056 #define TSE_PCS_USE_SGMII_AN_MASK           BIT(1)
0057 #define TSE_PCS_USE_SGMII_ENA               BIT(0)
0058 #define TSE_PCS_IF_USE_SGMII                0x03
0059
0060 #define AUTONEGO_LINK_TIMER             20
0061
0062 static int tse_pcs_reset(void __iomem *base, struct tse_pcs *pcs)
0063 {
0064     int counter = 0;
0065     u16 val;
0066
0067     val = readw(base + TSE_PCS_CONTROL_REG);
0068     val |= TSE_PCS_SW_RST_MASK;
0069     writew(val, base + TSE_PCS_CONTROL_REG);
0070
0071     while (counter < TSE_PCS_SW_RESET_TIMEOUT) {
0072         val = readw(base + TSE_PCS_CONTROL_REG);
0073         val &= TSE_PCS_SW_RST_MASK;
0074         if (val == 0)
0075             break;
0076         counter++;
0077         udelay(1);
0078     }
0079     if (counter >= TSE_PCS_SW_RESET_TIMEOUT) {
0080         dev_err(pcs->dev, "PCS could not get out of sw reset\n");
0081         return -ETIMEDOUT;
0082     }
0083
0084     return 0;
0085 }
0086
0087 int tse_pcs_init(void __iomem *base, struct tse_pcs *pcs)
0088 {
0089     int ret = 0;
0090
0091     writew(TSE_PCS_IF_USE_SGMII, base + TSE_PCS_IF_MODE_REG);
0092
0093     writew(TSE_PCS_CTRL_AUTONEG_SGMII, base + TSE_PCS_CONTROL_REG);
0094
0095     writew(TSE_PCS_SGMII_LINK_TIMER_0, base + TSE_PCS_LINK_TIMER_0_REG);
0096     writew(TSE_PCS_SGMII_LINK_TIMER_1, base + TSE_PCS_LINK_TIMER_1_REG);
0097
0098     ret = tse_pcs_reset(base, pcs);
0099     if (ret == 0)
0100         writew(SGMII_ADAPTER_ENABLE,
0101                pcs->sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
0102
0103     return ret;
0104 }
0105
0106 static void pcs_link_timer_callback(struct tse_pcs *pcs)
0107 {
0108     u16 val = 0;
0109     void __iomem *tse_pcs_base = pcs->tse_pcs_base;
0110     void __iomem *sgmii_adapter_base = pcs->sgmii_adapter_base;
0111
0112     val = readw(tse_pcs_base + TSE_PCS_STATUS_REG);
0113     val &= TSE_PCS_STATUS_LINK_MASK;
0114
0115     if (val != 0) {
0116         dev_dbg(pcs->dev, "Adapter: Link is established\n");
0117         writew(SGMII_ADAPTER_ENABLE,
0118                sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
0119     } else {
0120         mod_timer(&pcs->aneg_link_timer, jiffies +
0121               msecs_to_jiffies(AUTONEGO_LINK_TIMER));
0122     }
0123 }
0124
0125 static void auto_nego_timer_callback(struct tse_pcs *pcs)
0126 {
0127     u16 val = 0;
0128     u16 speed = 0;
0129     u16 duplex = 0;
0130     void __iomem *tse_pcs_base = pcs->tse_pcs_base;
0131     void __iomem *sgmii_adapter_base = pcs->sgmii_adapter_base;
0132
0133     val = readw(tse_pcs_base + TSE_PCS_STATUS_REG);
0134     val &= TSE_PCS_STATUS_AN_COMPLETED_MASK;
0135
0136     if (val != 0) {
0137         dev_dbg(pcs->dev, "Adapter: Auto Negotiation is completed\n");
0138         val = readw(tse_pcs_base + TSE_PCS_PARTNER_ABILITY_REG);
0139         speed = val & TSE_PCS_PARTNER_SPEED_MASK;
0140         duplex = val & TSE_PCS_PARTNER_DUPLEX_MASK;
0141
0142         if (speed == TSE_PCS_PARTNER_SPEED_10 &&
0143             duplex == TSE_PCS_PARTNER_DUPLEX_FULL)
0144             dev_dbg(pcs->dev,
0145                 "Adapter: Link Partner is Up - 10/Full\n");
0146         else if (speed == TSE_PCS_PARTNER_SPEED_100 &&
0147              duplex == TSE_PCS_PARTNER_DUPLEX_FULL)
0148             dev_dbg(pcs->dev,
0149                 "Adapter: Link Partner is Up - 100/Full\n");
0150         else if (speed == TSE_PCS_PARTNER_SPEED_1000 &&
0151              duplex == TSE_PCS_PARTNER_DUPLEX_FULL)
0152             dev_dbg(pcs->dev,
0153                 "Adapter: Link Partner is Up - 1000/Full\n");
0154         else if (speed == TSE_PCS_PARTNER_SPEED_10 &&
0155              duplex == TSE_PCS_PARTNER_DUPLEX_HALF)
0156             dev_err(pcs->dev,
0157                 "Adapter does not support Half Duplex\n");
0158         else if (speed == TSE_PCS_PARTNER_SPEED_100 &&
0159              duplex == TSE_PCS_PARTNER_DUPLEX_HALF)
0160             dev_err(pcs->dev,
0161                 "Adapter does not support Half Duplex\n");
0162         else if (speed == TSE_PCS_PARTNER_SPEED_1000 &&
0163              duplex == TSE_PCS_PARTNER_DUPLEX_HALF)
0164             dev_err(pcs->dev,
0165                 "Adapter does not support Half Duplex\n");
0166         else
0167             dev_err(pcs->dev,
0168                 "Adapter: Invalid Partner Speed and Duplex\n");
0169
0170         if (duplex == TSE_PCS_PARTNER_DUPLEX_FULL &&
0171             (speed == TSE_PCS_PARTNER_SPEED_10 ||
0172              speed == TSE_PCS_PARTNER_SPEED_100 ||
0173              speed == TSE_PCS_PARTNER_SPEED_1000))
0174             writew(SGMII_ADAPTER_ENABLE,
0175                    sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
0176     } else {
0177         val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG);
0178         val |= TSE_PCS_CONTROL_RESTART_AN_MASK;
0179         writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG);
0180
0181         tse_pcs_reset(tse_pcs_base, pcs);
0182         mod_timer(&pcs->aneg_link_timer, jiffies +
0183               msecs_to_jiffies(AUTONEGO_LINK_TIMER));
0184     }
0185 }
0186
0187 static void aneg_link_timer_callback(struct timer_list *t)
0188 {
0189     struct tse_pcs *pcs = from_timer(pcs, t, aneg_link_timer);
0190
0191     if (pcs->autoneg == AUTONEG_ENABLE)
0192         auto_nego_timer_callback(pcs);
0193     else if (pcs->autoneg == AUTONEG_DISABLE)
0194         pcs_link_timer_callback(pcs);
0195 }
0196
0197 void tse_pcs_fix_mac_speed(struct tse_pcs *pcs, struct phy_device *phy_dev,
0198                unsigned int speed)
0199 {
0200     void __iomem *tse_pcs_base = pcs->tse_pcs_base;
0201     u32 val;
0202
0203     pcs->autoneg = phy_dev->autoneg;
0204
0205     if (phy_dev->autoneg == AUTONEG_ENABLE) {
0206         val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG);
0207         val |= TSE_PCS_CONTROL_AN_EN_MASK;
0208         writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG);
0209
0210         val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG);
0211         val |= TSE_PCS_USE_SGMII_AN_MASK;
0212         writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG);
0213
0214         val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG);
0215         val |= TSE_PCS_CONTROL_RESTART_AN_MASK;
0216
0217         tse_pcs_reset(tse_pcs_base, pcs);
0218
0219         timer_setup(&pcs->aneg_link_timer, aneg_link_timer_callback,
0220                 0);
0221         mod_timer(&pcs->aneg_link_timer, jiffies +
0222               msecs_to_jiffies(AUTONEGO_LINK_TIMER));
0223     } else if (phy_dev->autoneg == AUTONEG_DISABLE) {
0224         val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG);
0225         val &= ~TSE_PCS_CONTROL_AN_EN_MASK;
0226         writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG);
0227
0228         val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG);
0229         val &= ~TSE_PCS_USE_SGMII_AN_MASK;
0230         writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG);
0231
0232         val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG);
0233         val &= ~TSE_PCS_SGMII_SPEED_MASK;
0234
0235         switch (speed) {
0236         case 1000:
0237             val |= TSE_PCS_SGMII_SPEED_1000;
0238             break;
0239         case 100:
0240             val |= TSE_PCS_SGMII_SPEED_100;
0241             break;
0242         case 10:
0243             val |= TSE_PCS_SGMII_SPEED_10;
0244             break;
0245         default:
0246             return;
0247         }
0248         writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG);
0249
0250         tse_pcs_reset(tse_pcs_base, pcs);
0251
0252         timer_setup(&pcs->aneg_link_timer, aneg_link_timer_callback,
0253                 0);
0254         mod_timer(&pcs->aneg_link_timer, jiffies +
0255               msecs_to_jiffies(AUTONEGO_LINK_TIMER));
0256     }
0257 }