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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002  /***************************************************************************
0003  *
0004  * Copyright (C) 2007,2008  SMSC
0005  *
0006  ***************************************************************************
0007  */
0008 
0009 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0010 
0011 #include <linux/interrupt.h>
0012 #include <linux/kernel.h>
0013 #include <linux/netdevice.h>
0014 #include <linux/phy.h>
0015 #include <linux/pci.h>
0016 #include <linux/if_vlan.h>
0017 #include <linux/dma-mapping.h>
0018 #include <linux/crc32.h>
0019 #include <linux/slab.h>
0020 #include <linux/module.h>
0021 #include <asm/unaligned.h>
0022 #include "smsc9420.h"
0023 
0024 #define DRV_NAME        "smsc9420"
0025 #define DRV_MDIONAME        "smsc9420-mdio"
0026 #define DRV_DESCRIPTION     "SMSC LAN9420 driver"
0027 #define DRV_VERSION     "1.01"
0028 
0029 MODULE_LICENSE("GPL");
0030 MODULE_VERSION(DRV_VERSION);
0031 
0032 struct smsc9420_dma_desc {
0033     u32 status;
0034     u32 length;
0035     u32 buffer1;
0036     u32 buffer2;
0037 };
0038 
0039 struct smsc9420_ring_info {
0040     struct sk_buff *skb;
0041     dma_addr_t mapping;
0042 };
0043 
0044 struct smsc9420_pdata {
0045     void __iomem *ioaddr;
0046     struct pci_dev *pdev;
0047     struct net_device *dev;
0048 
0049     struct smsc9420_dma_desc *rx_ring;
0050     struct smsc9420_dma_desc *tx_ring;
0051     struct smsc9420_ring_info *tx_buffers;
0052     struct smsc9420_ring_info *rx_buffers;
0053     dma_addr_t rx_dma_addr;
0054     dma_addr_t tx_dma_addr;
0055     int tx_ring_head, tx_ring_tail;
0056     int rx_ring_head, rx_ring_tail;
0057 
0058     spinlock_t int_lock;
0059     spinlock_t phy_lock;
0060 
0061     struct napi_struct napi;
0062 
0063     bool software_irq_signal;
0064     bool rx_csum;
0065     u32 msg_enable;
0066 
0067     struct mii_bus *mii_bus;
0068     int last_duplex;
0069     int last_carrier;
0070 };
0071 
0072 static const struct pci_device_id smsc9420_id_table[] = {
0073     { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
0074     { 0, }
0075 };
0076 
0077 MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
0078 
0079 #define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
0080 
0081 static uint smsc_debug;
0082 static uint debug = -1;
0083 module_param(debug, uint, 0);
0084 MODULE_PARM_DESC(debug, "debug level");
0085 
0086 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
0087 {
0088     return ioread32(pd->ioaddr + offset);
0089 }
0090 
0091 static inline void
0092 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
0093 {
0094     iowrite32(value, pd->ioaddr + offset);
0095 }
0096 
0097 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
0098 {
0099     /* to ensure PCI write completion, we must perform a PCI read */
0100     smsc9420_reg_read(pd, ID_REV);
0101 }
0102 
0103 static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
0104 {
0105     struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
0106     unsigned long flags;
0107     u32 addr;
0108     int i, reg = -EIO;
0109 
0110     spin_lock_irqsave(&pd->phy_lock, flags);
0111 
0112     /*  confirm MII not busy */
0113     if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
0114         netif_warn(pd, drv, pd->dev, "MII is busy???\n");
0115         goto out;
0116     }
0117 
0118     /* set the address, index & direction (read from PHY) */
0119     addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
0120         MII_ACCESS_MII_READ_;
0121     smsc9420_reg_write(pd, MII_ACCESS, addr);
0122 
0123     /* wait for read to complete with 50us timeout */
0124     for (i = 0; i < 5; i++) {
0125         if (!(smsc9420_reg_read(pd, MII_ACCESS) &
0126             MII_ACCESS_MII_BUSY_)) {
0127             reg = (u16)smsc9420_reg_read(pd, MII_DATA);
0128             goto out;
0129         }
0130         udelay(10);
0131     }
0132 
0133     netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
0134 
0135 out:
0136     spin_unlock_irqrestore(&pd->phy_lock, flags);
0137     return reg;
0138 }
0139 
0140 static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
0141                u16 val)
0142 {
0143     struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
0144     unsigned long flags;
0145     u32 addr;
0146     int i, reg = -EIO;
0147 
0148     spin_lock_irqsave(&pd->phy_lock, flags);
0149 
0150     /* confirm MII not busy */
0151     if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
0152         netif_warn(pd, drv, pd->dev, "MII is busy???\n");
0153         goto out;
0154     }
0155 
0156     /* put the data to write in the MAC */
0157     smsc9420_reg_write(pd, MII_DATA, (u32)val);
0158 
0159     /* set the address, index & direction (write to PHY) */
0160     addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
0161         MII_ACCESS_MII_WRITE_;
0162     smsc9420_reg_write(pd, MII_ACCESS, addr);
0163 
0164     /* wait for write to complete with 50us timeout */
0165     for (i = 0; i < 5; i++) {
0166         if (!(smsc9420_reg_read(pd, MII_ACCESS) &
0167             MII_ACCESS_MII_BUSY_)) {
0168             reg = 0;
0169             goto out;
0170         }
0171         udelay(10);
0172     }
0173 
0174     netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
0175 
0176 out:
0177     spin_unlock_irqrestore(&pd->phy_lock, flags);
0178     return reg;
0179 }
0180 
0181 /* Returns hash bit number for given MAC address
0182  * Example:
0183  * 01 00 5E 00 00 01 -> returns bit number 31 */
0184 static u32 smsc9420_hash(u8 addr[ETH_ALEN])
0185 {
0186     return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
0187 }
0188 
0189 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
0190 {
0191     int timeout = 100000;
0192 
0193     BUG_ON(!pd);
0194 
0195     if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
0196         netif_dbg(pd, drv, pd->dev, "%s: Eeprom busy\n", __func__);
0197         return -EIO;
0198     }
0199 
0200     smsc9420_reg_write(pd, E2P_CMD,
0201         (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
0202 
0203     do {
0204         udelay(10);
0205         if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
0206             return 0;
0207     } while (timeout--);
0208 
0209     netif_warn(pd, drv, pd->dev, "%s: Eeprom timed out\n", __func__);
0210     return -EIO;
0211 }
0212 
0213 static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
0214                      struct ethtool_drvinfo *drvinfo)
0215 {
0216     struct smsc9420_pdata *pd = netdev_priv(netdev);
0217 
0218     strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
0219     strlcpy(drvinfo->bus_info, pci_name(pd->pdev),
0220         sizeof(drvinfo->bus_info));
0221     strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
0222 }
0223 
0224 static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
0225 {
0226     struct smsc9420_pdata *pd = netdev_priv(netdev);
0227     return pd->msg_enable;
0228 }
0229 
0230 static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
0231 {
0232     struct smsc9420_pdata *pd = netdev_priv(netdev);
0233     pd->msg_enable = data;
0234 }
0235 
0236 static int smsc9420_ethtool_getregslen(struct net_device *dev)
0237 {
0238     /* all smsc9420 registers plus all phy registers */
0239     return 0x100 + (32 * sizeof(u32));
0240 }
0241 
0242 static void
0243 smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
0244              void *buf)
0245 {
0246     struct smsc9420_pdata *pd = netdev_priv(dev);
0247     struct phy_device *phy_dev = dev->phydev;
0248     unsigned int i, j = 0;
0249     u32 *data = buf;
0250 
0251     regs->version = smsc9420_reg_read(pd, ID_REV);
0252     for (i = 0; i < 0x100; i += (sizeof(u32)))
0253         data[j++] = smsc9420_reg_read(pd, i);
0254 
0255     // cannot read phy registers if the net device is down
0256     if (!phy_dev)
0257         return;
0258 
0259     for (i = 0; i <= 31; i++)
0260         data[j++] = smsc9420_mii_read(phy_dev->mdio.bus,
0261                           phy_dev->mdio.addr, i);
0262 }
0263 
0264 static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
0265 {
0266     unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
0267     temp &= ~GPIO_CFG_EEPR_EN_;
0268     smsc9420_reg_write(pd, GPIO_CFG, temp);
0269     msleep(1);
0270 }
0271 
0272 static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
0273 {
0274     int timeout = 100;
0275     u32 e2cmd;
0276 
0277     netif_dbg(pd, hw, pd->dev, "op 0x%08x\n", op);
0278     if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
0279         netif_warn(pd, hw, pd->dev, "Busy at start\n");
0280         return -EBUSY;
0281     }
0282 
0283     e2cmd = op | E2P_CMD_EPC_BUSY_;
0284     smsc9420_reg_write(pd, E2P_CMD, e2cmd);
0285 
0286     do {
0287         msleep(1);
0288         e2cmd = smsc9420_reg_read(pd, E2P_CMD);
0289     } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
0290 
0291     if (!timeout) {
0292         netif_info(pd, hw, pd->dev, "TIMED OUT\n");
0293         return -EAGAIN;
0294     }
0295 
0296     if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
0297         netif_info(pd, hw, pd->dev,
0298                "Error occurred during eeprom operation\n");
0299         return -EINVAL;
0300     }
0301 
0302     return 0;
0303 }
0304 
0305 static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
0306                      u8 address, u8 *data)
0307 {
0308     u32 op = E2P_CMD_EPC_CMD_READ_ | address;
0309     int ret;
0310 
0311     netif_dbg(pd, hw, pd->dev, "address 0x%x\n", address);
0312     ret = smsc9420_eeprom_send_cmd(pd, op);
0313 
0314     if (!ret)
0315         data[address] = smsc9420_reg_read(pd, E2P_DATA);
0316 
0317     return ret;
0318 }
0319 
0320 static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
0321                       u8 address, u8 data)
0322 {
0323     u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
0324     int ret;
0325 
0326     netif_dbg(pd, hw, pd->dev, "address 0x%x, data 0x%x\n", address, data);
0327     ret = smsc9420_eeprom_send_cmd(pd, op);
0328 
0329     if (!ret) {
0330         op = E2P_CMD_EPC_CMD_WRITE_ | address;
0331         smsc9420_reg_write(pd, E2P_DATA, (u32)data);
0332         ret = smsc9420_eeprom_send_cmd(pd, op);
0333     }
0334 
0335     return ret;
0336 }
0337 
0338 static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev)
0339 {
0340     return SMSC9420_EEPROM_SIZE;
0341 }
0342 
0343 static int smsc9420_ethtool_get_eeprom(struct net_device *dev,
0344                        struct ethtool_eeprom *eeprom, u8 *data)
0345 {
0346     struct smsc9420_pdata *pd = netdev_priv(dev);
0347     u8 eeprom_data[SMSC9420_EEPROM_SIZE];
0348     int len, i;
0349 
0350     smsc9420_eeprom_enable_access(pd);
0351 
0352     len = min(eeprom->len, SMSC9420_EEPROM_SIZE);
0353     for (i = 0; i < len; i++) {
0354         int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
0355         if (ret < 0) {
0356             eeprom->len = 0;
0357             return ret;
0358         }
0359     }
0360 
0361     memcpy(data, &eeprom_data[eeprom->offset], len);
0362     eeprom->magic = SMSC9420_EEPROM_MAGIC;
0363     eeprom->len = len;
0364     return 0;
0365 }
0366 
0367 static int smsc9420_ethtool_set_eeprom(struct net_device *dev,
0368                        struct ethtool_eeprom *eeprom, u8 *data)
0369 {
0370     struct smsc9420_pdata *pd = netdev_priv(dev);
0371     int ret;
0372 
0373     if (eeprom->magic != SMSC9420_EEPROM_MAGIC)
0374         return -EINVAL;
0375 
0376     smsc9420_eeprom_enable_access(pd);
0377     smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
0378     ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
0379     smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
0380 
0381     /* Single byte write, according to man page */
0382     eeprom->len = 1;
0383 
0384     return ret;
0385 }
0386 
0387 static const struct ethtool_ops smsc9420_ethtool_ops = {
0388     .get_drvinfo = smsc9420_ethtool_get_drvinfo,
0389     .get_msglevel = smsc9420_ethtool_get_msglevel,
0390     .set_msglevel = smsc9420_ethtool_set_msglevel,
0391     .nway_reset = phy_ethtool_nway_reset,
0392     .get_link = ethtool_op_get_link,
0393     .get_eeprom_len = smsc9420_ethtool_get_eeprom_len,
0394     .get_eeprom = smsc9420_ethtool_get_eeprom,
0395     .set_eeprom = smsc9420_ethtool_set_eeprom,
0396     .get_regs_len = smsc9420_ethtool_getregslen,
0397     .get_regs = smsc9420_ethtool_getregs,
0398     .get_ts_info = ethtool_op_get_ts_info,
0399     .get_link_ksettings = phy_ethtool_get_link_ksettings,
0400     .set_link_ksettings = phy_ethtool_set_link_ksettings,
0401 };
0402 
0403 /* Sets the device MAC address to dev_addr */
0404 static void smsc9420_set_mac_address(struct net_device *dev)
0405 {
0406     struct smsc9420_pdata *pd = netdev_priv(dev);
0407     const u8 *dev_addr = dev->dev_addr;
0408     u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
0409     u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
0410         (dev_addr[1] << 8) | dev_addr[0];
0411 
0412     smsc9420_reg_write(pd, ADDRH, mac_high16);
0413     smsc9420_reg_write(pd, ADDRL, mac_low32);
0414 }
0415 
0416 static void smsc9420_check_mac_address(struct net_device *dev)
0417 {
0418     struct smsc9420_pdata *pd = netdev_priv(dev);
0419     u8 addr[ETH_ALEN];
0420 
0421     /* Check if mac address has been specified when bringing interface up */
0422     if (is_valid_ether_addr(dev->dev_addr)) {
0423         smsc9420_set_mac_address(dev);
0424         netif_dbg(pd, probe, pd->dev,
0425               "MAC Address is specified by configuration\n");
0426     } else {
0427         /* Try reading mac address from device. if EEPROM is present
0428          * it will already have been set */
0429         u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
0430         u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
0431         addr[0] = (u8)(mac_low32);
0432         addr[1] = (u8)(mac_low32 >> 8);
0433         addr[2] = (u8)(mac_low32 >> 16);
0434         addr[3] = (u8)(mac_low32 >> 24);
0435         addr[4] = (u8)(mac_high16);
0436         addr[5] = (u8)(mac_high16 >> 8);
0437 
0438         if (is_valid_ether_addr(addr)) {
0439             /* eeprom values are valid  so use them */
0440             eth_hw_addr_set(dev, addr);
0441             netif_dbg(pd, probe, pd->dev,
0442                   "Mac Address is read from EEPROM\n");
0443         } else {
0444             /* eeprom values are invalid, generate random MAC */
0445             eth_hw_addr_random(dev);
0446             smsc9420_set_mac_address(dev);
0447             netif_dbg(pd, probe, pd->dev,
0448                   "MAC Address is set to random\n");
0449         }
0450     }
0451 }
0452 
0453 static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
0454 {
0455     u32 dmac_control, mac_cr, dma_intr_ena;
0456     int timeout = 1000;
0457 
0458     /* disable TX DMAC */
0459     dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
0460     dmac_control &= (~DMAC_CONTROL_ST_);
0461     smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
0462 
0463     /* Wait max 10ms for transmit process to stop */
0464     while (--timeout) {
0465         if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
0466             break;
0467         udelay(10);
0468     }
0469 
0470     if (!timeout)
0471         netif_warn(pd, ifdown, pd->dev, "TX DMAC failed to stop\n");
0472 
0473     /* ACK Tx DMAC stop bit */
0474     smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
0475 
0476     /* mask TX DMAC interrupts */
0477     dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
0478     dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
0479     smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
0480     smsc9420_pci_flush_write(pd);
0481 
0482     /* stop MAC TX */
0483     mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
0484     smsc9420_reg_write(pd, MAC_CR, mac_cr);
0485     smsc9420_pci_flush_write(pd);
0486 }
0487 
0488 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
0489 {
0490     int i;
0491 
0492     BUG_ON(!pd->tx_ring);
0493 
0494     if (!pd->tx_buffers)
0495         return;
0496 
0497     for (i = 0; i < TX_RING_SIZE; i++) {
0498         struct sk_buff *skb = pd->tx_buffers[i].skb;
0499 
0500         if (skb) {
0501             BUG_ON(!pd->tx_buffers[i].mapping);
0502             dma_unmap_single(&pd->pdev->dev,
0503                      pd->tx_buffers[i].mapping, skb->len,
0504                      DMA_TO_DEVICE);
0505             dev_kfree_skb_any(skb);
0506         }
0507 
0508         pd->tx_ring[i].status = 0;
0509         pd->tx_ring[i].length = 0;
0510         pd->tx_ring[i].buffer1 = 0;
0511         pd->tx_ring[i].buffer2 = 0;
0512     }
0513     wmb();
0514 
0515     kfree(pd->tx_buffers);
0516     pd->tx_buffers = NULL;
0517 
0518     pd->tx_ring_head = 0;
0519     pd->tx_ring_tail = 0;
0520 }
0521 
0522 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
0523 {
0524     int i;
0525 
0526     BUG_ON(!pd->rx_ring);
0527 
0528     if (!pd->rx_buffers)
0529         return;
0530 
0531     for (i = 0; i < RX_RING_SIZE; i++) {
0532         if (pd->rx_buffers[i].skb)
0533             dev_kfree_skb_any(pd->rx_buffers[i].skb);
0534 
0535         if (pd->rx_buffers[i].mapping)
0536             dma_unmap_single(&pd->pdev->dev,
0537                      pd->rx_buffers[i].mapping,
0538                      PKT_BUF_SZ, DMA_FROM_DEVICE);
0539 
0540         pd->rx_ring[i].status = 0;
0541         pd->rx_ring[i].length = 0;
0542         pd->rx_ring[i].buffer1 = 0;
0543         pd->rx_ring[i].buffer2 = 0;
0544     }
0545     wmb();
0546 
0547     kfree(pd->rx_buffers);
0548     pd->rx_buffers = NULL;
0549 
0550     pd->rx_ring_head = 0;
0551     pd->rx_ring_tail = 0;
0552 }
0553 
0554 static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
0555 {
0556     int timeout = 1000;
0557     u32 mac_cr, dmac_control, dma_intr_ena;
0558 
0559     /* mask RX DMAC interrupts */
0560     dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
0561     dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
0562     smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
0563     smsc9420_pci_flush_write(pd);
0564 
0565     /* stop RX MAC prior to stoping DMA */
0566     mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
0567     smsc9420_reg_write(pd, MAC_CR, mac_cr);
0568     smsc9420_pci_flush_write(pd);
0569 
0570     /* stop RX DMAC */
0571     dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
0572     dmac_control &= (~DMAC_CONTROL_SR_);
0573     smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
0574     smsc9420_pci_flush_write(pd);
0575 
0576     /* wait up to 10ms for receive to stop */
0577     while (--timeout) {
0578         if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
0579             break;
0580         udelay(10);
0581     }
0582 
0583     if (!timeout)
0584         netif_warn(pd, ifdown, pd->dev,
0585                "RX DMAC did not stop! timeout\n");
0586 
0587     /* ACK the Rx DMAC stop bit */
0588     smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
0589 }
0590 
0591 static irqreturn_t smsc9420_isr(int irq, void *dev_id)
0592 {
0593     struct smsc9420_pdata *pd = dev_id;
0594     u32 int_cfg, int_sts, int_ctl;
0595     irqreturn_t ret = IRQ_NONE;
0596     ulong flags;
0597 
0598     BUG_ON(!pd);
0599     BUG_ON(!pd->ioaddr);
0600 
0601     int_cfg = smsc9420_reg_read(pd, INT_CFG);
0602 
0603     /* check if it's our interrupt */
0604     if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
0605         (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
0606         return IRQ_NONE;
0607 
0608     int_sts = smsc9420_reg_read(pd, INT_STAT);
0609 
0610     if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
0611         u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
0612         u32 ints_to_clear = 0;
0613 
0614         if (status & DMAC_STS_TX_) {
0615             ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
0616             netif_wake_queue(pd->dev);
0617         }
0618 
0619         if (status & DMAC_STS_RX_) {
0620             /* mask RX DMAC interrupts */
0621             u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
0622             dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
0623             smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
0624             smsc9420_pci_flush_write(pd);
0625 
0626             ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
0627             napi_schedule(&pd->napi);
0628         }
0629 
0630         if (ints_to_clear)
0631             smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
0632 
0633         ret = IRQ_HANDLED;
0634     }
0635 
0636     if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
0637         /* mask software interrupt */
0638         spin_lock_irqsave(&pd->int_lock, flags);
0639         int_ctl = smsc9420_reg_read(pd, INT_CTL);
0640         int_ctl &= (~INT_CTL_SW_INT_EN_);
0641         smsc9420_reg_write(pd, INT_CTL, int_ctl);
0642         spin_unlock_irqrestore(&pd->int_lock, flags);
0643 
0644         smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
0645         pd->software_irq_signal = true;
0646         smp_wmb();
0647 
0648         ret = IRQ_HANDLED;
0649     }
0650 
0651     /* to ensure PCI write completion, we must perform a PCI read */
0652     smsc9420_pci_flush_write(pd);
0653 
0654     return ret;
0655 }
0656 
0657 #ifdef CONFIG_NET_POLL_CONTROLLER
0658 static void smsc9420_poll_controller(struct net_device *dev)
0659 {
0660     struct smsc9420_pdata *pd = netdev_priv(dev);
0661     const int irq = pd->pdev->irq;
0662 
0663     disable_irq(irq);
0664     smsc9420_isr(0, dev);
0665     enable_irq(irq);
0666 }
0667 #endif /* CONFIG_NET_POLL_CONTROLLER */
0668 
0669 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
0670 {
0671     smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
0672     smsc9420_reg_read(pd, BUS_MODE);
0673     udelay(2);
0674     if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
0675         netif_warn(pd, drv, pd->dev, "Software reset not cleared\n");
0676 }
0677 
0678 static int smsc9420_stop(struct net_device *dev)
0679 {
0680     struct smsc9420_pdata *pd = netdev_priv(dev);
0681     u32 int_cfg;
0682     ulong flags;
0683 
0684     BUG_ON(!pd);
0685     BUG_ON(!dev->phydev);
0686 
0687     /* disable master interrupt */
0688     spin_lock_irqsave(&pd->int_lock, flags);
0689     int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
0690     smsc9420_reg_write(pd, INT_CFG, int_cfg);
0691     spin_unlock_irqrestore(&pd->int_lock, flags);
0692 
0693     netif_tx_disable(dev);
0694     napi_disable(&pd->napi);
0695 
0696     smsc9420_stop_tx(pd);
0697     smsc9420_free_tx_ring(pd);
0698 
0699     smsc9420_stop_rx(pd);
0700     smsc9420_free_rx_ring(pd);
0701 
0702     free_irq(pd->pdev->irq, pd);
0703 
0704     smsc9420_dmac_soft_reset(pd);
0705 
0706     phy_stop(dev->phydev);
0707 
0708     phy_disconnect(dev->phydev);
0709     mdiobus_unregister(pd->mii_bus);
0710     mdiobus_free(pd->mii_bus);
0711 
0712     return 0;
0713 }
0714 
0715 static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
0716 {
0717     if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
0718         dev->stats.rx_errors++;
0719         if (desc_status & RDES0_DESCRIPTOR_ERROR_)
0720             dev->stats.rx_over_errors++;
0721         else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
0722             RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
0723             dev->stats.rx_frame_errors++;
0724         else if (desc_status & RDES0_CRC_ERROR_)
0725             dev->stats.rx_crc_errors++;
0726     }
0727 
0728     if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
0729         dev->stats.rx_length_errors++;
0730 
0731     if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
0732         (desc_status & RDES0_FIRST_DESCRIPTOR_))))
0733         dev->stats.rx_length_errors++;
0734 
0735     if (desc_status & RDES0_MULTICAST_FRAME_)
0736         dev->stats.multicast++;
0737 }
0738 
0739 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
0740                 const u32 status)
0741 {
0742     struct net_device *dev = pd->dev;
0743     struct sk_buff *skb;
0744     u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
0745         >> RDES0_FRAME_LENGTH_SHFT_;
0746 
0747     /* remove crc from packet lendth */
0748     packet_length -= 4;
0749 
0750     if (pd->rx_csum)
0751         packet_length -= 2;
0752 
0753     dev->stats.rx_packets++;
0754     dev->stats.rx_bytes += packet_length;
0755 
0756     dma_unmap_single(&pd->pdev->dev, pd->rx_buffers[index].mapping,
0757              PKT_BUF_SZ, DMA_FROM_DEVICE);
0758     pd->rx_buffers[index].mapping = 0;
0759 
0760     skb = pd->rx_buffers[index].skb;
0761     pd->rx_buffers[index].skb = NULL;
0762 
0763     if (pd->rx_csum) {
0764         u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
0765             NET_IP_ALIGN + packet_length + 4);
0766         put_unaligned_le16(hw_csum, &skb->csum);
0767         skb->ip_summed = CHECKSUM_COMPLETE;
0768     }
0769 
0770     skb_reserve(skb, NET_IP_ALIGN);
0771     skb_put(skb, packet_length);
0772 
0773     skb->protocol = eth_type_trans(skb, dev);
0774 
0775     netif_receive_skb(skb);
0776 }
0777 
0778 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
0779 {
0780     struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
0781     dma_addr_t mapping;
0782 
0783     BUG_ON(pd->rx_buffers[index].skb);
0784     BUG_ON(pd->rx_buffers[index].mapping);
0785 
0786     if (unlikely(!skb))
0787         return -ENOMEM;
0788 
0789     mapping = dma_map_single(&pd->pdev->dev, skb_tail_pointer(skb),
0790                  PKT_BUF_SZ, DMA_FROM_DEVICE);
0791     if (dma_mapping_error(&pd->pdev->dev, mapping)) {
0792         dev_kfree_skb_any(skb);
0793         netif_warn(pd, rx_err, pd->dev, "dma_map_single failed!\n");
0794         return -ENOMEM;
0795     }
0796 
0797     pd->rx_buffers[index].skb = skb;
0798     pd->rx_buffers[index].mapping = mapping;
0799     pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
0800     pd->rx_ring[index].status = RDES0_OWN_;
0801     wmb();
0802 
0803     return 0;
0804 }
0805 
0806 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
0807 {
0808     while (pd->rx_ring_tail != pd->rx_ring_head) {
0809         if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
0810             break;
0811 
0812         pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
0813     }
0814 }
0815 
0816 static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
0817 {
0818     struct smsc9420_pdata *pd =
0819         container_of(napi, struct smsc9420_pdata, napi);
0820     struct net_device *dev = pd->dev;
0821     u32 drop_frame_cnt, dma_intr_ena, status;
0822     int work_done;
0823 
0824     for (work_done = 0; work_done < budget; work_done++) {
0825         rmb();
0826         status = pd->rx_ring[pd->rx_ring_head].status;
0827 
0828         /* stop if DMAC owns this dma descriptor */
0829         if (status & RDES0_OWN_)
0830             break;
0831 
0832         smsc9420_rx_count_stats(dev, status);
0833         smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
0834         pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
0835         smsc9420_alloc_new_rx_buffers(pd);
0836     }
0837 
0838     drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
0839     dev->stats.rx_dropped +=
0840         (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
0841 
0842     /* Kick RXDMA */
0843     smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
0844     smsc9420_pci_flush_write(pd);
0845 
0846     if (work_done < budget) {
0847         napi_complete_done(&pd->napi, work_done);
0848 
0849         /* re-enable RX DMA interrupts */
0850         dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
0851         dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
0852         smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
0853         smsc9420_pci_flush_write(pd);
0854     }
0855     return work_done;
0856 }
0857 
0858 static void
0859 smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
0860 {
0861     if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
0862         dev->stats.tx_errors++;
0863         if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
0864             TDES0_EXCESSIVE_COLLISIONS_))
0865             dev->stats.tx_aborted_errors++;
0866 
0867         if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
0868             dev->stats.tx_carrier_errors++;
0869     } else {
0870         dev->stats.tx_packets++;
0871         dev->stats.tx_bytes += (length & 0x7FF);
0872     }
0873 
0874     if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
0875         dev->stats.collisions += 16;
0876     } else {
0877         dev->stats.collisions +=
0878             (status & TDES0_COLLISION_COUNT_MASK_) >>
0879             TDES0_COLLISION_COUNT_SHFT_;
0880     }
0881 
0882     if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
0883         dev->stats.tx_heartbeat_errors++;
0884 }
0885 
0886 /* Check for completed dma transfers, update stats and free skbs */
0887 static void smsc9420_complete_tx(struct net_device *dev)
0888 {
0889     struct smsc9420_pdata *pd = netdev_priv(dev);
0890 
0891     while (pd->tx_ring_tail != pd->tx_ring_head) {
0892         int index = pd->tx_ring_tail;
0893         u32 status, length;
0894 
0895         rmb();
0896         status = pd->tx_ring[index].status;
0897         length = pd->tx_ring[index].length;
0898 
0899         /* Check if DMA still owns this descriptor */
0900         if (unlikely(TDES0_OWN_ & status))
0901             break;
0902 
0903         smsc9420_tx_update_stats(dev, status, length);
0904 
0905         BUG_ON(!pd->tx_buffers[index].skb);
0906         BUG_ON(!pd->tx_buffers[index].mapping);
0907 
0908         dma_unmap_single(&pd->pdev->dev,
0909                  pd->tx_buffers[index].mapping,
0910                  pd->tx_buffers[index].skb->len,
0911                  DMA_TO_DEVICE);
0912         pd->tx_buffers[index].mapping = 0;
0913 
0914         dev_kfree_skb_any(pd->tx_buffers[index].skb);
0915         pd->tx_buffers[index].skb = NULL;
0916 
0917         pd->tx_ring[index].buffer1 = 0;
0918         wmb();
0919 
0920         pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
0921     }
0922 }
0923 
0924 static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb,
0925                         struct net_device *dev)
0926 {
0927     struct smsc9420_pdata *pd = netdev_priv(dev);
0928     dma_addr_t mapping;
0929     int index = pd->tx_ring_head;
0930     u32 tmp_desc1;
0931     bool about_to_take_last_desc =
0932         (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
0933 
0934     smsc9420_complete_tx(dev);
0935 
0936     rmb();
0937     BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
0938     BUG_ON(pd->tx_buffers[index].skb);
0939     BUG_ON(pd->tx_buffers[index].mapping);
0940 
0941     mapping = dma_map_single(&pd->pdev->dev, skb->data, skb->len,
0942                  DMA_TO_DEVICE);
0943     if (dma_mapping_error(&pd->pdev->dev, mapping)) {
0944         netif_warn(pd, tx_err, pd->dev,
0945                "dma_map_single failed, dropping packet\n");
0946         return NETDEV_TX_BUSY;
0947     }
0948 
0949     pd->tx_buffers[index].skb = skb;
0950     pd->tx_buffers[index].mapping = mapping;
0951 
0952     tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
0953     if (unlikely(about_to_take_last_desc)) {
0954         tmp_desc1 |= TDES1_IC_;
0955         netif_stop_queue(pd->dev);
0956     }
0957 
0958     /* check if we are at the last descriptor and need to set EOR */
0959     if (unlikely(index == (TX_RING_SIZE - 1)))
0960         tmp_desc1 |= TDES1_TER_;
0961 
0962     pd->tx_ring[index].buffer1 = mapping;
0963     pd->tx_ring[index].length = tmp_desc1;
0964     wmb();
0965 
0966     /* increment head */
0967     pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
0968 
0969     /* assign ownership to DMAC */
0970     pd->tx_ring[index].status = TDES0_OWN_;
0971     wmb();
0972 
0973     skb_tx_timestamp(skb);
0974 
0975     /* kick the DMA */
0976     smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
0977     smsc9420_pci_flush_write(pd);
0978 
0979     return NETDEV_TX_OK;
0980 }
0981 
0982 static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
0983 {
0984     struct smsc9420_pdata *pd = netdev_priv(dev);
0985     u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
0986     dev->stats.rx_dropped +=
0987         (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
0988     return &dev->stats;
0989 }
0990 
0991 static void smsc9420_set_multicast_list(struct net_device *dev)
0992 {
0993     struct smsc9420_pdata *pd = netdev_priv(dev);
0994     u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
0995 
0996     if (dev->flags & IFF_PROMISC) {
0997         netif_dbg(pd, hw, pd->dev, "Promiscuous Mode Enabled\n");
0998         mac_cr |= MAC_CR_PRMS_;
0999         mac_cr &= (~MAC_CR_MCPAS_);
1000         mac_cr &= (~MAC_CR_HPFILT_);
1001     } else if (dev->flags & IFF_ALLMULTI) {
1002         netif_dbg(pd, hw, pd->dev, "Receive all Multicast Enabled\n");
1003         mac_cr &= (~MAC_CR_PRMS_);
1004         mac_cr |= MAC_CR_MCPAS_;
1005         mac_cr &= (~MAC_CR_HPFILT_);
1006     } else if (!netdev_mc_empty(dev)) {
1007         struct netdev_hw_addr *ha;
1008         u32 hash_lo = 0, hash_hi = 0;
1009 
1010         netif_dbg(pd, hw, pd->dev, "Multicast filter enabled\n");
1011         netdev_for_each_mc_addr(ha, dev) {
1012             u32 bit_num = smsc9420_hash(ha->addr);
1013             u32 mask = 1 << (bit_num & 0x1F);
1014 
1015             if (bit_num & 0x20)
1016                 hash_hi |= mask;
1017             else
1018                 hash_lo |= mask;
1019 
1020         }
1021         smsc9420_reg_write(pd, HASHH, hash_hi);
1022         smsc9420_reg_write(pd, HASHL, hash_lo);
1023 
1024         mac_cr &= (~MAC_CR_PRMS_);
1025         mac_cr &= (~MAC_CR_MCPAS_);
1026         mac_cr |= MAC_CR_HPFILT_;
1027     } else {
1028         netif_dbg(pd, hw, pd->dev, "Receive own packets only\n");
1029         smsc9420_reg_write(pd, HASHH, 0);
1030         smsc9420_reg_write(pd, HASHL, 0);
1031 
1032         mac_cr &= (~MAC_CR_PRMS_);
1033         mac_cr &= (~MAC_CR_MCPAS_);
1034         mac_cr &= (~MAC_CR_HPFILT_);
1035     }
1036 
1037     smsc9420_reg_write(pd, MAC_CR, mac_cr);
1038     smsc9420_pci_flush_write(pd);
1039 }
1040 
1041 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1042 {
1043     struct net_device *dev = pd->dev;
1044     struct phy_device *phy_dev = dev->phydev;
1045     u32 flow;
1046 
1047     if (phy_dev->duplex == DUPLEX_FULL) {
1048         u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
1049         u16 rmtadv = phy_read(phy_dev, MII_LPA);
1050         u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1051 
1052         if (cap & FLOW_CTRL_RX)
1053             flow = 0xFFFF0002;
1054         else
1055             flow = 0;
1056 
1057         netif_info(pd, link, pd->dev, "rx pause %s, tx pause %s\n",
1058                cap & FLOW_CTRL_RX ? "enabled" : "disabled",
1059                cap & FLOW_CTRL_TX ? "enabled" : "disabled");
1060     } else {
1061         netif_info(pd, link, pd->dev, "half duplex\n");
1062         flow = 0;
1063     }
1064 
1065     smsc9420_reg_write(pd, FLOW, flow);
1066 }
1067 
1068 /* Update link mode if anything has changed.  Called periodically when the
1069  * PHY is in polling mode, even if nothing has changed. */
1070 static void smsc9420_phy_adjust_link(struct net_device *dev)
1071 {
1072     struct smsc9420_pdata *pd = netdev_priv(dev);
1073     struct phy_device *phy_dev = dev->phydev;
1074     int carrier;
1075 
1076     if (phy_dev->duplex != pd->last_duplex) {
1077         u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1078         if (phy_dev->duplex) {
1079             netif_dbg(pd, link, pd->dev, "full duplex mode\n");
1080             mac_cr |= MAC_CR_FDPX_;
1081         } else {
1082             netif_dbg(pd, link, pd->dev, "half duplex mode\n");
1083             mac_cr &= ~MAC_CR_FDPX_;
1084         }
1085         smsc9420_reg_write(pd, MAC_CR, mac_cr);
1086 
1087         smsc9420_phy_update_flowcontrol(pd);
1088         pd->last_duplex = phy_dev->duplex;
1089     }
1090 
1091     carrier = netif_carrier_ok(dev);
1092     if (carrier != pd->last_carrier) {
1093         if (carrier)
1094             netif_dbg(pd, link, pd->dev, "carrier OK\n");
1095         else
1096             netif_dbg(pd, link, pd->dev, "no carrier\n");
1097         pd->last_carrier = carrier;
1098     }
1099 }
1100 
1101 static int smsc9420_mii_probe(struct net_device *dev)
1102 {
1103     struct smsc9420_pdata *pd = netdev_priv(dev);
1104     struct phy_device *phydev = NULL;
1105 
1106     BUG_ON(dev->phydev);
1107 
1108     /* Device only supports internal PHY at address 1 */
1109     phydev = mdiobus_get_phy(pd->mii_bus, 1);
1110     if (!phydev) {
1111         netdev_err(dev, "no PHY found at address 1\n");
1112         return -ENODEV;
1113     }
1114 
1115     phydev = phy_connect(dev, phydev_name(phydev),
1116                  smsc9420_phy_adjust_link, PHY_INTERFACE_MODE_MII);
1117 
1118     if (IS_ERR(phydev)) {
1119         netdev_err(dev, "Could not attach to PHY\n");
1120         return PTR_ERR(phydev);
1121     }
1122 
1123     phy_set_max_speed(phydev, SPEED_100);
1124 
1125     /* mask with MAC supported features */
1126     phy_support_asym_pause(phydev);
1127 
1128     phy_attached_info(phydev);
1129 
1130     pd->last_duplex = -1;
1131     pd->last_carrier = -1;
1132 
1133     return 0;
1134 }
1135 
1136 static int smsc9420_mii_init(struct net_device *dev)
1137 {
1138     struct smsc9420_pdata *pd = netdev_priv(dev);
1139     int err = -ENXIO;
1140 
1141     pd->mii_bus = mdiobus_alloc();
1142     if (!pd->mii_bus) {
1143         err = -ENOMEM;
1144         goto err_out_1;
1145     }
1146     pd->mii_bus->name = DRV_MDIONAME;
1147     snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1148         (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1149     pd->mii_bus->priv = pd;
1150     pd->mii_bus->read = smsc9420_mii_read;
1151     pd->mii_bus->write = smsc9420_mii_write;
1152 
1153     /* Mask all PHYs except ID 1 (internal) */
1154     pd->mii_bus->phy_mask = ~(1 << 1);
1155 
1156     if (mdiobus_register(pd->mii_bus)) {
1157         netif_warn(pd, probe, pd->dev, "Error registering mii bus\n");
1158         goto err_out_free_bus_2;
1159     }
1160 
1161     if (smsc9420_mii_probe(dev) < 0) {
1162         netif_warn(pd, probe, pd->dev, "Error probing mii bus\n");
1163         goto err_out_unregister_bus_3;
1164     }
1165 
1166     return 0;
1167 
1168 err_out_unregister_bus_3:
1169     mdiobus_unregister(pd->mii_bus);
1170 err_out_free_bus_2:
1171     mdiobus_free(pd->mii_bus);
1172 err_out_1:
1173     return err;
1174 }
1175 
1176 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1177 {
1178     int i;
1179 
1180     BUG_ON(!pd->tx_ring);
1181 
1182     pd->tx_buffers = kmalloc_array(TX_RING_SIZE,
1183                        sizeof(struct smsc9420_ring_info),
1184                        GFP_KERNEL);
1185     if (!pd->tx_buffers)
1186         return -ENOMEM;
1187 
1188     /* Initialize the TX Ring */
1189     for (i = 0; i < TX_RING_SIZE; i++) {
1190         pd->tx_buffers[i].skb = NULL;
1191         pd->tx_buffers[i].mapping = 0;
1192         pd->tx_ring[i].status = 0;
1193         pd->tx_ring[i].length = 0;
1194         pd->tx_ring[i].buffer1 = 0;
1195         pd->tx_ring[i].buffer2 = 0;
1196     }
1197     pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1198     wmb();
1199 
1200     pd->tx_ring_head = 0;
1201     pd->tx_ring_tail = 0;
1202 
1203     smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1204     smsc9420_pci_flush_write(pd);
1205 
1206     return 0;
1207 }
1208 
1209 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1210 {
1211     int i;
1212 
1213     BUG_ON(!pd->rx_ring);
1214 
1215     pd->rx_buffers = kmalloc_array(RX_RING_SIZE,
1216                        sizeof(struct smsc9420_ring_info),
1217                        GFP_KERNEL);
1218     if (pd->rx_buffers == NULL)
1219         goto out;
1220 
1221     /* initialize the rx ring */
1222     for (i = 0; i < RX_RING_SIZE; i++) {
1223         pd->rx_ring[i].status = 0;
1224         pd->rx_ring[i].length = PKT_BUF_SZ;
1225         pd->rx_ring[i].buffer2 = 0;
1226         pd->rx_buffers[i].skb = NULL;
1227         pd->rx_buffers[i].mapping = 0;
1228     }
1229     pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1230 
1231     /* now allocate the entire ring of skbs */
1232     for (i = 0; i < RX_RING_SIZE; i++) {
1233         if (smsc9420_alloc_rx_buffer(pd, i)) {
1234             netif_warn(pd, ifup, pd->dev,
1235                    "failed to allocate rx skb %d\n", i);
1236             goto out_free_rx_skbs;
1237         }
1238     }
1239 
1240     pd->rx_ring_head = 0;
1241     pd->rx_ring_tail = 0;
1242 
1243     smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1244     netif_dbg(pd, ifup, pd->dev, "VLAN1 = 0x%08x\n",
1245           smsc9420_reg_read(pd, VLAN1));
1246 
1247     if (pd->rx_csum) {
1248         /* Enable RX COE */
1249         u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1250         smsc9420_reg_write(pd, COE_CR, coe);
1251         netif_dbg(pd, ifup, pd->dev, "COE_CR = 0x%08x\n", coe);
1252     }
1253 
1254     smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1255     smsc9420_pci_flush_write(pd);
1256 
1257     return 0;
1258 
1259 out_free_rx_skbs:
1260     smsc9420_free_rx_ring(pd);
1261 out:
1262     return -ENOMEM;
1263 }
1264 
1265 static int smsc9420_open(struct net_device *dev)
1266 {
1267     struct smsc9420_pdata *pd = netdev_priv(dev);
1268     u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
1269     const int irq = pd->pdev->irq;
1270     unsigned long flags;
1271     int result = 0, timeout;
1272 
1273     if (!is_valid_ether_addr(dev->dev_addr)) {
1274         netif_warn(pd, ifup, pd->dev,
1275                "dev_addr is not a valid MAC address\n");
1276         result = -EADDRNOTAVAIL;
1277         goto out_0;
1278     }
1279 
1280     netif_carrier_off(dev);
1281 
1282     /* disable, mask and acknowledge all interrupts */
1283     spin_lock_irqsave(&pd->int_lock, flags);
1284     int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1285     smsc9420_reg_write(pd, INT_CFG, int_cfg);
1286     smsc9420_reg_write(pd, INT_CTL, 0);
1287     spin_unlock_irqrestore(&pd->int_lock, flags);
1288     smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1289     smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1290     smsc9420_pci_flush_write(pd);
1291 
1292     result = request_irq(irq, smsc9420_isr, IRQF_SHARED, DRV_NAME, pd);
1293     if (result) {
1294         netif_warn(pd, ifup, pd->dev, "Unable to use IRQ = %d\n", irq);
1295         result = -ENODEV;
1296         goto out_0;
1297     }
1298 
1299     smsc9420_dmac_soft_reset(pd);
1300 
1301     /* make sure MAC_CR is sane */
1302     smsc9420_reg_write(pd, MAC_CR, 0);
1303 
1304     smsc9420_set_mac_address(dev);
1305 
1306     /* Configure GPIO pins to drive LEDs */
1307     smsc9420_reg_write(pd, GPIO_CFG,
1308         (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
1309 
1310     bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
1311 
1312 #ifdef __BIG_ENDIAN
1313     bus_mode |= BUS_MODE_DBO_;
1314 #endif
1315 
1316     smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1317 
1318     smsc9420_pci_flush_write(pd);
1319 
1320     /* set bus master bridge arbitration priority for Rx and TX DMA */
1321     smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1322 
1323     smsc9420_reg_write(pd, DMAC_CONTROL,
1324         (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
1325 
1326     smsc9420_pci_flush_write(pd);
1327 
1328     /* test the IRQ connection to the ISR */
1329     netif_dbg(pd, ifup, pd->dev, "Testing ISR using IRQ %d\n", irq);
1330     pd->software_irq_signal = false;
1331 
1332     spin_lock_irqsave(&pd->int_lock, flags);
1333     /* configure interrupt deassertion timer and enable interrupts */
1334     int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1335     int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
1336     int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
1337     smsc9420_reg_write(pd, INT_CFG, int_cfg);
1338 
1339     /* unmask software interrupt */
1340     int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1341     smsc9420_reg_write(pd, INT_CTL, int_ctl);
1342     spin_unlock_irqrestore(&pd->int_lock, flags);
1343     smsc9420_pci_flush_write(pd);
1344 
1345     timeout = 1000;
1346     while (timeout--) {
1347         if (pd->software_irq_signal)
1348             break;
1349         msleep(1);
1350     }
1351 
1352     /* disable interrupts */
1353     spin_lock_irqsave(&pd->int_lock, flags);
1354     int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1355     smsc9420_reg_write(pd, INT_CFG, int_cfg);
1356     spin_unlock_irqrestore(&pd->int_lock, flags);
1357 
1358     if (!pd->software_irq_signal) {
1359         netif_warn(pd, ifup, pd->dev, "ISR failed signaling test\n");
1360         result = -ENODEV;
1361         goto out_free_irq_1;
1362     }
1363 
1364     netif_dbg(pd, ifup, pd->dev, "ISR passed test using IRQ %d\n", irq);
1365 
1366     result = smsc9420_alloc_tx_ring(pd);
1367     if (result) {
1368         netif_warn(pd, ifup, pd->dev,
1369                "Failed to Initialize tx dma ring\n");
1370         result = -ENOMEM;
1371         goto out_free_irq_1;
1372     }
1373 
1374     result = smsc9420_alloc_rx_ring(pd);
1375     if (result) {
1376         netif_warn(pd, ifup, pd->dev,
1377                "Failed to Initialize rx dma ring\n");
1378         result = -ENOMEM;
1379         goto out_free_tx_ring_2;
1380     }
1381 
1382     result = smsc9420_mii_init(dev);
1383     if (result) {
1384         netif_warn(pd, ifup, pd->dev, "Failed to initialize Phy\n");
1385         result = -ENODEV;
1386         goto out_free_rx_ring_3;
1387     }
1388 
1389     /* Bring the PHY up */
1390     phy_start(dev->phydev);
1391 
1392     napi_enable(&pd->napi);
1393 
1394     /* start tx and rx */
1395     mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1396     smsc9420_reg_write(pd, MAC_CR, mac_cr);
1397 
1398     dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1399     dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
1400     smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1401     smsc9420_pci_flush_write(pd);
1402 
1403     dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1404     dma_intr_ena |=
1405         (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
1406     smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1407     smsc9420_pci_flush_write(pd);
1408 
1409     netif_wake_queue(dev);
1410 
1411     smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1412 
1413     /* enable interrupts */
1414     spin_lock_irqsave(&pd->int_lock, flags);
1415     int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1416     smsc9420_reg_write(pd, INT_CFG, int_cfg);
1417     spin_unlock_irqrestore(&pd->int_lock, flags);
1418 
1419     return 0;
1420 
1421 out_free_rx_ring_3:
1422     smsc9420_free_rx_ring(pd);
1423 out_free_tx_ring_2:
1424     smsc9420_free_tx_ring(pd);
1425 out_free_irq_1:
1426     free_irq(irq, pd);
1427 out_0:
1428     return result;
1429 }
1430 
1431 static int __maybe_unused smsc9420_suspend(struct device *dev_d)
1432 {
1433     struct net_device *dev = dev_get_drvdata(dev_d);
1434     struct smsc9420_pdata *pd = netdev_priv(dev);
1435     u32 int_cfg;
1436     ulong flags;
1437 
1438     /* disable interrupts */
1439     spin_lock_irqsave(&pd->int_lock, flags);
1440     int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1441     smsc9420_reg_write(pd, INT_CFG, int_cfg);
1442     spin_unlock_irqrestore(&pd->int_lock, flags);
1443 
1444     if (netif_running(dev)) {
1445         netif_tx_disable(dev);
1446         smsc9420_stop_tx(pd);
1447         smsc9420_free_tx_ring(pd);
1448 
1449         napi_disable(&pd->napi);
1450         smsc9420_stop_rx(pd);
1451         smsc9420_free_rx_ring(pd);
1452 
1453         free_irq(pd->pdev->irq, pd);
1454 
1455         netif_device_detach(dev);
1456     }
1457 
1458     device_wakeup_disable(dev_d);
1459 
1460     return 0;
1461 }
1462 
1463 static int __maybe_unused smsc9420_resume(struct device *dev_d)
1464 {
1465     struct net_device *dev = dev_get_drvdata(dev_d);
1466     int err;
1467 
1468     pci_set_master(to_pci_dev(dev_d));
1469 
1470     device_wakeup_disable(dev_d);
1471 
1472     err = 0;
1473     if (netif_running(dev)) {
1474         /* FIXME: gross. It looks like ancient PM relic.*/
1475         err = smsc9420_open(dev);
1476         netif_device_attach(dev);
1477     }
1478     return err;
1479 }
1480 
1481 static const struct net_device_ops smsc9420_netdev_ops = {
1482     .ndo_open       = smsc9420_open,
1483     .ndo_stop       = smsc9420_stop,
1484     .ndo_start_xmit     = smsc9420_hard_start_xmit,
1485     .ndo_get_stats      = smsc9420_get_stats,
1486     .ndo_set_rx_mode    = smsc9420_set_multicast_list,
1487     .ndo_eth_ioctl      = phy_do_ioctl_running,
1488     .ndo_validate_addr  = eth_validate_addr,
1489     .ndo_set_mac_address    = eth_mac_addr,
1490 #ifdef CONFIG_NET_POLL_CONTROLLER
1491     .ndo_poll_controller    = smsc9420_poll_controller,
1492 #endif /* CONFIG_NET_POLL_CONTROLLER */
1493 };
1494 
1495 static int
1496 smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1497 {
1498     struct net_device *dev;
1499     struct smsc9420_pdata *pd;
1500     void __iomem *virt_addr;
1501     int result = 0;
1502     u32 id_rev;
1503 
1504     pr_info("%s version %s\n", DRV_DESCRIPTION, DRV_VERSION);
1505 
1506     /* First do the PCI initialisation */
1507     result = pci_enable_device(pdev);
1508     if (unlikely(result)) {
1509         pr_err("Cannot enable smsc9420\n");
1510         goto out_0;
1511     }
1512 
1513     pci_set_master(pdev);
1514 
1515     dev = alloc_etherdev(sizeof(*pd));
1516     if (!dev)
1517         goto out_disable_pci_device_1;
1518 
1519     SET_NETDEV_DEV(dev, &pdev->dev);
1520 
1521     if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
1522         netdev_err(dev, "Cannot find PCI device base address\n");
1523         goto out_free_netdev_2;
1524     }
1525 
1526     if ((pci_request_regions(pdev, DRV_NAME))) {
1527         netdev_err(dev, "Cannot obtain PCI resources, aborting\n");
1528         goto out_free_netdev_2;
1529     }
1530 
1531     if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
1532         netdev_err(dev, "No usable DMA configuration, aborting\n");
1533         goto out_free_regions_3;
1534     }
1535 
1536     virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
1537         pci_resource_len(pdev, SMSC_BAR));
1538     if (!virt_addr) {
1539         netdev_err(dev, "Cannot map device registers, aborting\n");
1540         goto out_free_regions_3;
1541     }
1542 
1543     /* registers are double mapped with 0 offset for LE and 0x200 for BE */
1544     virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
1545 
1546     pd = netdev_priv(dev);
1547 
1548     /* pci descriptors are created in the PCI consistent area */
1549     pd->rx_ring = dma_alloc_coherent(&pdev->dev,
1550         sizeof(struct smsc9420_dma_desc) * (RX_RING_SIZE + TX_RING_SIZE),
1551         &pd->rx_dma_addr, GFP_KERNEL);
1552 
1553     if (!pd->rx_ring)
1554         goto out_free_io_4;
1555 
1556     /* descriptors are aligned due to the nature of dma_alloc_coherent */
1557     pd->tx_ring = (pd->rx_ring + RX_RING_SIZE);
1558     pd->tx_dma_addr = pd->rx_dma_addr +
1559         sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
1560 
1561     pd->pdev = pdev;
1562     pd->dev = dev;
1563     pd->ioaddr = virt_addr;
1564     pd->msg_enable = smsc_debug;
1565     pd->rx_csum = true;
1566 
1567     netif_dbg(pd, probe, pd->dev, "lan_base=0x%08lx\n", (ulong)virt_addr);
1568 
1569     id_rev = smsc9420_reg_read(pd, ID_REV);
1570     switch (id_rev & 0xFFFF0000) {
1571     case 0x94200000:
1572         netif_info(pd, probe, pd->dev,
1573                "LAN9420 identified, ID_REV=0x%08X\n", id_rev);
1574         break;
1575     default:
1576         netif_warn(pd, probe, pd->dev, "LAN9420 NOT identified\n");
1577         netif_warn(pd, probe, pd->dev, "ID_REV=0x%08X\n", id_rev);
1578         goto out_free_dmadesc_5;
1579     }
1580 
1581     smsc9420_dmac_soft_reset(pd);
1582     smsc9420_eeprom_reload(pd);
1583     smsc9420_check_mac_address(dev);
1584 
1585     dev->netdev_ops = &smsc9420_netdev_ops;
1586     dev->ethtool_ops = &smsc9420_ethtool_ops;
1587 
1588     netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_POLL_WEIGHT);
1589 
1590     result = register_netdev(dev);
1591     if (result) {
1592         netif_warn(pd, probe, pd->dev, "error %i registering device\n",
1593                result);
1594         goto out_free_dmadesc_5;
1595     }
1596 
1597     pci_set_drvdata(pdev, dev);
1598 
1599     spin_lock_init(&pd->int_lock);
1600     spin_lock_init(&pd->phy_lock);
1601 
1602     dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1603 
1604     return 0;
1605 
1606 out_free_dmadesc_5:
1607     dma_free_coherent(&pdev->dev,
1608               sizeof(struct smsc9420_dma_desc) * (RX_RING_SIZE + TX_RING_SIZE),
1609               pd->rx_ring, pd->rx_dma_addr);
1610 out_free_io_4:
1611     iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1612 out_free_regions_3:
1613     pci_release_regions(pdev);
1614 out_free_netdev_2:
1615     free_netdev(dev);
1616 out_disable_pci_device_1:
1617     pci_disable_device(pdev);
1618 out_0:
1619     return -ENODEV;
1620 }
1621 
1622 static void smsc9420_remove(struct pci_dev *pdev)
1623 {
1624     struct net_device *dev;
1625     struct smsc9420_pdata *pd;
1626 
1627     dev = pci_get_drvdata(pdev);
1628     if (!dev)
1629         return;
1630 
1631     pd = netdev_priv(dev);
1632     unregister_netdev(dev);
1633 
1634     /* tx_buffers and rx_buffers are freed in stop */
1635     BUG_ON(pd->tx_buffers);
1636     BUG_ON(pd->rx_buffers);
1637 
1638     BUG_ON(!pd->tx_ring);
1639     BUG_ON(!pd->rx_ring);
1640 
1641     dma_free_coherent(&pdev->dev,
1642               sizeof(struct smsc9420_dma_desc) * (RX_RING_SIZE + TX_RING_SIZE),
1643               pd->rx_ring, pd->rx_dma_addr);
1644 
1645     iounmap(pd->ioaddr - LAN9420_CPSR_ENDIAN_OFFSET);
1646     pci_release_regions(pdev);
1647     free_netdev(dev);
1648     pci_disable_device(pdev);
1649 }
1650 
1651 static SIMPLE_DEV_PM_OPS(smsc9420_pm_ops, smsc9420_suspend, smsc9420_resume);
1652 
1653 static struct pci_driver smsc9420_driver = {
1654     .name = DRV_NAME,
1655     .id_table = smsc9420_id_table,
1656     .probe = smsc9420_probe,
1657     .remove = smsc9420_remove,
1658     .driver.pm = &smsc9420_pm_ops,
1659 };
1660 
1661 static int __init smsc9420_init_module(void)
1662 {
1663     smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
1664 
1665     return pci_register_driver(&smsc9420_driver);
1666 }
1667 
1668 static void __exit smsc9420_exit_module(void)
1669 {
1670     pci_unregister_driver(&smsc9420_driver);
1671 }
1672 
1673 module_init(smsc9420_init_module);
1674 module_exit(smsc9420_exit_module);
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