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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*------------------------------------------------------------------------
0003  . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
0004  .
0005  . Copyright (C) 1996 by Erik Stahlman
0006  . Copyright (C) 2001 Standard Microsystems Corporation
0007  .  Developed by Simple Network Magic Corporation
0008  . Copyright (C) 2003 Monta Vista Software, Inc.
0009  .  Unified SMC91x driver by Nicolas Pitre
0010  .
0011  .
0012  . Information contained in this file was obtained from the LAN91C111
0013  . manual from SMC.  To get a copy, if you really want one, you can find
0014  . information under www.smsc.com.
0015  .
0016  . Authors
0017  .  Erik Stahlman       <erik@vt.edu>
0018  .  Daris A Nevil       <dnevil@snmc.com>
0019  .  Nicolas Pitre       <nico@fluxnic.net>
0020  .
0021  ---------------------------------------------------------------------------*/
0022 #ifndef _SMC91X_H_
0023 #define _SMC91X_H_
0024 
0025 #include <linux/dmaengine.h>
0026 #include <linux/smc91x.h>
0027 
0028 /*
0029  * Any 16-bit access is performed with two 8-bit accesses if the hardware
0030  * can't do it directly. Most registers are 16-bit so those are mandatory.
0031  */
0032 #define SMC_outw_b(x, a, r)                     \
0033     do {                                \
0034         unsigned int __val16 = (x);             \
0035         unsigned int __reg = (r);               \
0036         SMC_outb(__val16, a, __reg);                \
0037         SMC_outb(__val16 >> 8, a, __reg + (1 << SMC_IO_SHIFT)); \
0038     } while (0)
0039 
0040 #define SMC_inw_b(a, r)                         \
0041     ({                              \
0042         unsigned int __val16;                   \
0043         unsigned int __reg = r;                 \
0044         __val16  = SMC_inb(a, __reg);               \
0045         __val16 |= SMC_inb(a, __reg + (1 << SMC_IO_SHIFT)) << 8; \
0046         __val16;                        \
0047     })
0048 
0049 /*
0050  * Define your architecture specific bus configuration parameters here.
0051  */
0052 
0053 #if defined(CONFIG_ARM)
0054 
0055 #include <asm/mach-types.h>
0056 
0057 /* Now the bus width is specified in the platform data
0058  * pretend here to support all I/O access types
0059  */
0060 #define SMC_CAN_USE_8BIT    1
0061 #define SMC_CAN_USE_16BIT   1
0062 #define SMC_CAN_USE_32BIT   1
0063 #define SMC_NOWAIT      1
0064 
0065 #define SMC_IO_SHIFT        (lp->io_shift)
0066 
0067 #define SMC_inb(a, r)       readb((a) + (r))
0068 #define SMC_inw(a, r)                           \
0069     ({                              \
0070         unsigned int __smc_r = r;               \
0071         SMC_16BIT(lp) ? readw((a) + __smc_r) :          \
0072         SMC_8BIT(lp) ? SMC_inw_b(a, __smc_r) :          \
0073         ({ BUG(); 0; });                    \
0074     })
0075 
0076 #define SMC_inl(a, r)       readl((a) + (r))
0077 #define SMC_outb(v, a, r)   writeb(v, (a) + (r))
0078 #define SMC_outw(lp, v, a, r)                       \
0079     do {                                \
0080         unsigned int __v = v, __smc_r = r;          \
0081         if (SMC_16BIT(lp))                  \
0082             __SMC_outw(lp, __v, a, __smc_r);        \
0083         else if (SMC_8BIT(lp))                  \
0084             SMC_outw_b(__v, a, __smc_r);            \
0085         else                            \
0086             BUG();                      \
0087     } while (0)
0088 
0089 #define SMC_outl(v, a, r)   writel(v, (a) + (r))
0090 #define SMC_insb(a, r, p, l)    readsb((a) + (r), p, l)
0091 #define SMC_outsb(a, r, p, l)   writesb((a) + (r), p, l)
0092 #define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
0093 #define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
0094 #define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
0095 #define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
0096 #define SMC_IRQ_FLAGS       (-1)    /* from resource */
0097 
0098 /* We actually can't write halfwords properly if not word aligned */
0099 static inline void _SMC_outw_align4(u16 val, void __iomem *ioaddr, int reg,
0100                     bool use_align4_workaround)
0101 {
0102     if (use_align4_workaround) {
0103         unsigned int v = val << 16;
0104         v |= readl(ioaddr + (reg & ~2)) & 0xffff;
0105         writel(v, ioaddr + (reg & ~2));
0106     } else {
0107         writew(val, ioaddr + reg);
0108     }
0109 }
0110 
0111 #define __SMC_outw(lp, v, a, r)                     \
0112     _SMC_outw_align4((v), (a), (r),                 \
0113              IS_BUILTIN(CONFIG_ARCH_PXA) && ((r) & 2) &&    \
0114              (lp)->cfg.pxa_u16_align4)
0115 
0116 
0117 #elif   defined(CONFIG_SH_SH4202_MICRODEV)
0118 
0119 #define SMC_CAN_USE_8BIT    0
0120 #define SMC_CAN_USE_16BIT   1
0121 #define SMC_CAN_USE_32BIT   0
0122 
0123 #define SMC_inb(a, r)       inb((a) + (r) - 0xa0000000)
0124 #define SMC_inw(a, r)       inw((a) + (r) - 0xa0000000)
0125 #define SMC_inl(a, r)       inl((a) + (r) - 0xa0000000)
0126 #define SMC_outb(v, a, r)   outb(v, (a) + (r) - 0xa0000000)
0127 #define SMC_outw(lp, v, a, r)   outw(v, (a) + (r) - 0xa0000000)
0128 #define SMC_outl(v, a, r)   outl(v, (a) + (r) - 0xa0000000)
0129 #define SMC_insl(a, r, p, l)    insl((a) + (r) - 0xa0000000, p, l)
0130 #define SMC_outsl(a, r, p, l)   outsl((a) + (r) - 0xa0000000, p, l)
0131 #define SMC_insw(a, r, p, l)    insw((a) + (r) - 0xa0000000, p, l)
0132 #define SMC_outsw(a, r, p, l)   outsw((a) + (r) - 0xa0000000, p, l)
0133 
0134 #define SMC_IRQ_FLAGS       (0)
0135 
0136 #elif defined(CONFIG_ATARI)
0137 
0138 #define SMC_CAN_USE_8BIT        1
0139 #define SMC_CAN_USE_16BIT       1
0140 #define SMC_CAN_USE_32BIT       1
0141 #define SMC_NOWAIT              1
0142 
0143 #define SMC_inb(a, r)           readb((a) + (r))
0144 #define SMC_inw(a, r)           readw((a) + (r))
0145 #define SMC_inl(a, r)           readl((a) + (r))
0146 #define SMC_outb(v, a, r)       writeb(v, (a) + (r))
0147 #define SMC_outw(lp, v, a, r)   writew(v, (a) + (r))
0148 #define SMC_outl(v, a, r)       writel(v, (a) + (r))
0149 #define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
0150 #define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
0151 #define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
0152 #define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
0153 
0154 #define RPC_LSA_DEFAULT         RPC_LED_100_10
0155 #define RPC_LSB_DEFAULT         RPC_LED_TX_RX
0156 
0157 #elif defined(CONFIG_COLDFIRE)
0158 
0159 #define SMC_CAN_USE_8BIT    0
0160 #define SMC_CAN_USE_16BIT   1
0161 #define SMC_CAN_USE_32BIT   0
0162 #define SMC_NOWAIT      1
0163 
0164 static inline void mcf_insw(void *a, unsigned char *p, int l)
0165 {
0166     u16 *wp = (u16 *) p;
0167     while (l-- > 0)
0168         *wp++ = readw(a);
0169 }
0170 
0171 static inline void mcf_outsw(void *a, unsigned char *p, int l)
0172 {
0173     u16 *wp = (u16 *) p;
0174     while (l-- > 0)
0175         writew(*wp++, a);
0176 }
0177 
0178 #define SMC_inw(a, r)       _swapw(readw((a) + (r)))
0179 #define SMC_outw(lp, v, a, r)   writew(_swapw(v), (a) + (r))
0180 #define SMC_insw(a, r, p, l)    mcf_insw(a + r, p, l)
0181 #define SMC_outsw(a, r, p, l)   mcf_outsw(a + r, p, l)
0182 
0183 #define SMC_IRQ_FLAGS       0
0184 
0185 #else
0186 
0187 /*
0188  * Default configuration
0189  */
0190 
0191 #define SMC_CAN_USE_8BIT    1
0192 #define SMC_CAN_USE_16BIT   1
0193 #define SMC_CAN_USE_32BIT   1
0194 #define SMC_NOWAIT      1
0195 
0196 #define SMC_IO_SHIFT        (lp->io_shift)
0197 
0198 #define SMC_inb(a, r)       ioread8((a) + (r))
0199 #define SMC_inw(a, r)       ioread16((a) + (r))
0200 #define SMC_inl(a, r)       ioread32((a) + (r))
0201 #define SMC_outb(v, a, r)   iowrite8(v, (a) + (r))
0202 #define SMC_outw(lp, v, a, r)   iowrite16(v, (a) + (r))
0203 #define SMC_outl(v, a, r)   iowrite32(v, (a) + (r))
0204 #define SMC_insw(a, r, p, l)    ioread16_rep((a) + (r), p, l)
0205 #define SMC_outsw(a, r, p, l)   iowrite16_rep((a) + (r), p, l)
0206 #define SMC_insl(a, r, p, l)    ioread32_rep((a) + (r), p, l)
0207 #define SMC_outsl(a, r, p, l)   iowrite32_rep((a) + (r), p, l)
0208 
0209 #define RPC_LSA_DEFAULT     RPC_LED_100_10
0210 #define RPC_LSB_DEFAULT     RPC_LED_TX_RX
0211 
0212 #endif
0213 
0214 
0215 /* store this information for the driver.. */
0216 struct smc_local {
0217     /*
0218      * If I have to wait until memory is available to send a
0219      * packet, I will store the skbuff here, until I get the
0220      * desired memory.  Then, I'll send it out and free it.
0221      */
0222     struct sk_buff *pending_tx_skb;
0223     struct tasklet_struct tx_task;
0224 
0225     struct gpio_desc *power_gpio;
0226     struct gpio_desc *reset_gpio;
0227 
0228     /* version/revision of the SMC91x chip */
0229     int version;
0230 
0231     /* Contains the current active transmission mode */
0232     int tcr_cur_mode;
0233 
0234     /* Contains the current active receive mode */
0235     int rcr_cur_mode;
0236 
0237     /* Contains the current active receive/phy mode */
0238     int rpc_cur_mode;
0239     int ctl_rfduplx;
0240     int ctl_rspeed;
0241 
0242     u32 msg_enable;
0243     u32 phy_type;
0244     struct mii_if_info mii;
0245 
0246     /* work queue */
0247     struct work_struct phy_configure;
0248     struct net_device *dev;
0249     int work_pending;
0250 
0251     spinlock_t lock;
0252 
0253 #ifdef CONFIG_ARCH_PXA
0254     /* DMA needs the physical address of the chip */
0255     u_long physaddr;
0256     struct device *device;
0257 #endif
0258     struct dma_chan *dma_chan;
0259     void __iomem *base;
0260     void __iomem *datacs;
0261 
0262     /* the low address lines on some platforms aren't connected... */
0263     int io_shift;
0264     /* on some platforms a u16 write must be 4-bytes aligned */
0265     bool    half_word_align4;
0266 
0267     struct smc91x_platdata cfg;
0268 };
0269 
0270 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
0271 #define SMC_16BIT(p)    ((p)->cfg.flags & SMC91X_USE_16BIT)
0272 #define SMC_32BIT(p)    ((p)->cfg.flags & SMC91X_USE_32BIT)
0273 
0274 #ifdef CONFIG_ARCH_PXA
0275 /*
0276  * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
0277  * always happening in irq context so no need to worry about races.  TX is
0278  * different and probably not worth it for that reason, and not as critical
0279  * as RX which can overrun memory and lose packets.
0280  */
0281 #include <linux/dma-mapping.h>
0282 
0283 #ifdef SMC_insl
0284 #undef SMC_insl
0285 #define SMC_insl(a, r, p, l) \
0286     smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
0287 static inline void
0288 smc_pxa_dma_inpump(struct smc_local *lp, u_char *buf, int len)
0289 {
0290     dma_addr_t dmabuf;
0291     struct dma_async_tx_descriptor *tx;
0292     dma_cookie_t cookie;
0293     enum dma_status status;
0294     struct dma_tx_state state;
0295 
0296     dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
0297     tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len,
0298                      DMA_DEV_TO_MEM, 0);
0299     if (tx) {
0300         cookie = dmaengine_submit(tx);
0301         dma_async_issue_pending(lp->dma_chan);
0302         do {
0303             status = dmaengine_tx_status(lp->dma_chan, cookie,
0304                              &state);
0305             cpu_relax();
0306         } while (status != DMA_COMPLETE && status != DMA_ERROR &&
0307              state.residue);
0308         dmaengine_terminate_all(lp->dma_chan);
0309     }
0310     dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
0311 }
0312 
0313 static inline void
0314 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
0315          u_char *buf, int len)
0316 {
0317     struct dma_slave_config config;
0318     int ret;
0319 
0320     /* fallback if no DMA available */
0321     if (!lp->dma_chan) {
0322         readsl(ioaddr + reg, buf, len);
0323         return;
0324     }
0325 
0326     /* 64 bit alignment is required for memory to memory DMA */
0327     if ((long)buf & 4) {
0328         *((u32 *)buf) = SMC_inl(ioaddr, reg);
0329         buf += 4;
0330         len--;
0331     }
0332 
0333     memset(&config, 0, sizeof(config));
0334     config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0335     config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0336     config.src_addr = lp->physaddr + reg;
0337     config.dst_addr = lp->physaddr + reg;
0338     config.src_maxburst = 32;
0339     config.dst_maxburst = 32;
0340     ret = dmaengine_slave_config(lp->dma_chan, &config);
0341     if (ret) {
0342         dev_err(lp->device, "dma channel configuration failed: %d\n",
0343             ret);
0344         return;
0345     }
0346 
0347     len *= 4;
0348     smc_pxa_dma_inpump(lp, buf, len);
0349 }
0350 #endif
0351 
0352 #ifdef SMC_insw
0353 #undef SMC_insw
0354 #define SMC_insw(a, r, p, l) \
0355     smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
0356 static inline void
0357 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
0358          u_char *buf, int len)
0359 {
0360     struct dma_slave_config config;
0361     int ret;
0362 
0363     /* fallback if no DMA available */
0364     if (!lp->dma_chan) {
0365         readsw(ioaddr + reg, buf, len);
0366         return;
0367     }
0368 
0369     /* 64 bit alignment is required for memory to memory DMA */
0370     while ((long)buf & 6) {
0371         *((u16 *)buf) = SMC_inw(ioaddr, reg);
0372         buf += 2;
0373         len--;
0374     }
0375 
0376     memset(&config, 0, sizeof(config));
0377     config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
0378     config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
0379     config.src_addr = lp->physaddr + reg;
0380     config.dst_addr = lp->physaddr + reg;
0381     config.src_maxburst = 32;
0382     config.dst_maxburst = 32;
0383     ret = dmaengine_slave_config(lp->dma_chan, &config);
0384     if (ret) {
0385         dev_err(lp->device, "dma channel configuration failed: %d\n",
0386             ret);
0387         return;
0388     }
0389 
0390     len *= 2;
0391     smc_pxa_dma_inpump(lp, buf, len);
0392 }
0393 #endif
0394 
0395 #endif  /* CONFIG_ARCH_PXA */
0396 
0397 
0398 /*
0399  * Everything a particular hardware setup needs should have been defined
0400  * at this point.  Add stubs for the undefined cases, mainly to avoid
0401  * compilation warnings since they'll be optimized away, or to prevent buggy
0402  * use of them.
0403  */
0404 
0405 #if ! SMC_CAN_USE_32BIT
0406 #define SMC_inl(ioaddr, reg)        ({ BUG(); 0; })
0407 #define SMC_outl(x, ioaddr, reg)    BUG()
0408 #define SMC_insl(a, r, p, l)        BUG()
0409 #define SMC_outsl(a, r, p, l)       BUG()
0410 #endif
0411 
0412 #if !defined(SMC_insl) || !defined(SMC_outsl)
0413 #define SMC_insl(a, r, p, l)        BUG()
0414 #define SMC_outsl(a, r, p, l)       BUG()
0415 #endif
0416 
0417 #if ! SMC_CAN_USE_16BIT
0418 
0419 #define SMC_outw(lp, x, ioaddr, reg)    SMC_outw_b(x, ioaddr, reg)
0420 #define SMC_inw(ioaddr, reg)        SMC_inw_b(ioaddr, reg)
0421 #define SMC_insw(a, r, p, l)        BUG()
0422 #define SMC_outsw(a, r, p, l)       BUG()
0423 
0424 #endif
0425 
0426 #if !defined(SMC_insw) || !defined(SMC_outsw)
0427 #define SMC_insw(a, r, p, l)        BUG()
0428 #define SMC_outsw(a, r, p, l)       BUG()
0429 #endif
0430 
0431 #if ! SMC_CAN_USE_8BIT
0432 #undef SMC_inb
0433 #define SMC_inb(ioaddr, reg)        ({ BUG(); 0; })
0434 #undef SMC_outb
0435 #define SMC_outb(x, ioaddr, reg)    BUG()
0436 #define SMC_insb(a, r, p, l)        BUG()
0437 #define SMC_outsb(a, r, p, l)       BUG()
0438 #endif
0439 
0440 #if !defined(SMC_insb) || !defined(SMC_outsb)
0441 #define SMC_insb(a, r, p, l)        BUG()
0442 #define SMC_outsb(a, r, p, l)       BUG()
0443 #endif
0444 
0445 #ifndef SMC_CAN_USE_DATACS
0446 #define SMC_CAN_USE_DATACS  0
0447 #endif
0448 
0449 #ifndef SMC_IO_SHIFT
0450 #define SMC_IO_SHIFT    0
0451 #endif
0452 
0453 #ifndef SMC_IRQ_FLAGS
0454 #define SMC_IRQ_FLAGS       IRQF_TRIGGER_RISING
0455 #endif
0456 
0457 #ifndef SMC_INTERRUPT_PREAMBLE
0458 #define SMC_INTERRUPT_PREAMBLE
0459 #endif
0460 
0461 
0462 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
0463 #define SMC_IO_EXTENT   (16 << SMC_IO_SHIFT)
0464 #define SMC_DATA_EXTENT (4)
0465 
0466 /*
0467  . Bank Select Register:
0468  .
0469  .      yyyy yyyy 0000 00xx
0470  .      xx      = bank number
0471  .      yyyy yyyy   = 0x33, for identification purposes.
0472 */
0473 #define BANK_SELECT     (14 << SMC_IO_SHIFT)
0474 
0475 
0476 // Transmit Control Register
0477 /* BANK 0  */
0478 #define TCR_REG(lp)     SMC_REG(lp, 0x0000, 0)
0479 #define TCR_ENABLE  0x0001  // When 1 we can transmit
0480 #define TCR_LOOP    0x0002  // Controls output pin LBK
0481 #define TCR_FORCOL  0x0004  // When 1 will force a collision
0482 #define TCR_PAD_EN  0x0080  // When 1 will pad tx frames < 64 bytes w/0
0483 #define TCR_NOCRC   0x0100  // When 1 will not append CRC to tx frames
0484 #define TCR_MON_CSN 0x0400  // When 1 tx monitors carrier
0485 #define TCR_FDUPLX      0x0800  // When 1 enables full duplex operation
0486 #define TCR_STP_SQET    0x1000  // When 1 stops tx if Signal Quality Error
0487 #define TCR_EPH_LOOP    0x2000  // When 1 enables EPH block loopback
0488 #define TCR_SWFDUP  0x8000  // When 1 enables Switched Full Duplex mode
0489 
0490 #define TCR_CLEAR   0   /* do NOTHING */
0491 /* the default settings for the TCR register : */
0492 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
0493 
0494 
0495 // EPH Status Register
0496 /* BANK 0  */
0497 #define EPH_STATUS_REG(lp)  SMC_REG(lp, 0x0002, 0)
0498 #define ES_TX_SUC   0x0001  // Last TX was successful
0499 #define ES_SNGL_COL 0x0002  // Single collision detected for last tx
0500 #define ES_MUL_COL  0x0004  // Multiple collisions detected for last tx
0501 #define ES_LTX_MULT 0x0008  // Last tx was a multicast
0502 #define ES_16COL    0x0010  // 16 Collisions Reached
0503 #define ES_SQET     0x0020  // Signal Quality Error Test
0504 #define ES_LTXBRD   0x0040  // Last tx was a broadcast
0505 #define ES_TXDEFR   0x0080  // Transmit Deferred
0506 #define ES_LATCOL   0x0200  // Late collision detected on last tx
0507 #define ES_LOSTCARR 0x0400  // Lost Carrier Sense
0508 #define ES_EXC_DEF  0x0800  // Excessive Deferral
0509 #define ES_CTR_ROL  0x1000  // Counter Roll Over indication
0510 #define ES_LINK_OK  0x4000  // Driven by inverted value of nLNK pin
0511 #define ES_TXUNRN   0x8000  // Tx Underrun
0512 
0513 
0514 // Receive Control Register
0515 /* BANK 0  */
0516 #define RCR_REG(lp)     SMC_REG(lp, 0x0004, 0)
0517 #define RCR_RX_ABORT    0x0001  // Set if a rx frame was aborted
0518 #define RCR_PRMS    0x0002  // Enable promiscuous mode
0519 #define RCR_ALMUL   0x0004  // When set accepts all multicast frames
0520 #define RCR_RXEN    0x0100  // IFF this is set, we can receive packets
0521 #define RCR_STRIP_CRC   0x0200  // When set strips CRC from rx packets
0522 #define RCR_ABORT_ENB   0x0200  // When set will abort rx on collision
0523 #define RCR_FILT_CAR    0x0400  // When set filters leading 12 bit s of carrier
0524 #define RCR_SOFTRST 0x8000  // resets the chip
0525 
0526 /* the normal settings for the RCR register : */
0527 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
0528 #define RCR_CLEAR   0x0 // set it to a base state
0529 
0530 
0531 // Counter Register
0532 /* BANK 0  */
0533 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
0534 
0535 
0536 // Memory Information Register
0537 /* BANK 0  */
0538 #define MIR_REG(lp)     SMC_REG(lp, 0x0008, 0)
0539 
0540 
0541 // Receive/Phy Control Register
0542 /* BANK 0  */
0543 #define RPC_REG(lp)     SMC_REG(lp, 0x000A, 0)
0544 #define RPC_SPEED   0x2000  // When 1 PHY is in 100Mbps mode.
0545 #define RPC_DPLX    0x1000  // When 1 PHY is in Full-Duplex Mode
0546 #define RPC_ANEG    0x0800  // When 1 PHY is in Auto-Negotiate Mode
0547 #define RPC_LSXA_SHFT   5   // Bits to shift LS2A,LS1A,LS0A to lsb
0548 #define RPC_LSXB_SHFT   2   // Bits to get LS2B,LS1B,LS0B to lsb
0549 
0550 #ifndef RPC_LSA_DEFAULT
0551 #define RPC_LSA_DEFAULT RPC_LED_100
0552 #endif
0553 #ifndef RPC_LSB_DEFAULT
0554 #define RPC_LSB_DEFAULT RPC_LED_FD
0555 #endif
0556 
0557 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
0558 
0559 
0560 /* Bank 0 0x0C is reserved */
0561 
0562 // Bank Select Register
0563 /* All Banks */
0564 #define BSR_REG     0x000E
0565 
0566 
0567 // Configuration Reg
0568 /* BANK 1 */
0569 #define CONFIG_REG(lp)  SMC_REG(lp, 0x0000, 1)
0570 #define CONFIG_EXT_PHY  0x0200  // 1=external MII, 0=internal Phy
0571 #define CONFIG_GPCNTRL  0x0400  // Inverse value drives pin nCNTRL
0572 #define CONFIG_NO_WAIT  0x1000  // When 1 no extra wait states on ISA bus
0573 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
0574 
0575 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
0576 #define CONFIG_DEFAULT  (CONFIG_EPH_POWER_EN)
0577 
0578 
0579 // Base Address Register
0580 /* BANK 1 */
0581 #define BASE_REG(lp)    SMC_REG(lp, 0x0002, 1)
0582 
0583 
0584 // Individual Address Registers
0585 /* BANK 1 */
0586 #define ADDR0_REG(lp)   SMC_REG(lp, 0x0004, 1)
0587 #define ADDR1_REG(lp)   SMC_REG(lp, 0x0006, 1)
0588 #define ADDR2_REG(lp)   SMC_REG(lp, 0x0008, 1)
0589 
0590 
0591 // General Purpose Register
0592 /* BANK 1 */
0593 #define GP_REG(lp)      SMC_REG(lp, 0x000A, 1)
0594 
0595 
0596 // Control Register
0597 /* BANK 1 */
0598 #define CTL_REG(lp)     SMC_REG(lp, 0x000C, 1)
0599 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
0600 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
0601 #define CTL_LE_ENABLE   0x0080 // When 1 enables Link Error interrupt
0602 #define CTL_CR_ENABLE   0x0040 // When 1 enables Counter Rollover interrupt
0603 #define CTL_TE_ENABLE   0x0020 // When 1 enables Transmit Error interrupt
0604 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
0605 #define CTL_RELOAD  0x0002 // When set reads EEPROM into registers
0606 #define CTL_STORE   0x0001 // When set stores registers into EEPROM
0607 
0608 
0609 // MMU Command Register
0610 /* BANK 2 */
0611 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
0612 #define MC_BUSY     1   // When 1 the last release has not completed
0613 #define MC_NOP      (0<<5)  // No Op
0614 #define MC_ALLOC    (1<<5)  // OR with number of 256 byte packets
0615 #define MC_RESET    (2<<5)  // Reset MMU to initial state
0616 #define MC_REMOVE   (3<<5)  // Remove the current rx packet
0617 #define MC_RELEASE      (4<<5)  // Remove and release the current rx packet
0618 #define MC_FREEPKT      (5<<5)  // Release packet in PNR register
0619 #define MC_ENQUEUE  (6<<5)  // Enqueue the packet for transmit
0620 #define MC_RSTTXFIFO    (7<<5)  // Reset the TX FIFOs
0621 
0622 
0623 // Packet Number Register
0624 /* BANK 2 */
0625 #define PN_REG(lp)      SMC_REG(lp, 0x0002, 2)
0626 
0627 
0628 // Allocation Result Register
0629 /* BANK 2 */
0630 #define AR_REG(lp)      SMC_REG(lp, 0x0003, 2)
0631 #define AR_FAILED   0x80    // Alocation Failed
0632 
0633 
0634 // TX FIFO Ports Register
0635 /* BANK 2 */
0636 #define TXFIFO_REG(lp)  SMC_REG(lp, 0x0004, 2)
0637 #define TXFIFO_TEMPTY   0x80    // TX FIFO Empty
0638 
0639 // RX FIFO Ports Register
0640 /* BANK 2 */
0641 #define RXFIFO_REG(lp)  SMC_REG(lp, 0x0005, 2)
0642 #define RXFIFO_REMPTY   0x80    // RX FIFO Empty
0643 
0644 #define FIFO_REG(lp)    SMC_REG(lp, 0x0004, 2)
0645 
0646 // Pointer Register
0647 /* BANK 2 */
0648 #define PTR_REG(lp)     SMC_REG(lp, 0x0006, 2)
0649 #define PTR_RCV     0x8000 // 1=Receive area, 0=Transmit area
0650 #define PTR_AUTOINC     0x4000 // Auto increment the pointer on each access
0651 #define PTR_READ    0x2000 // When 1 the operation is a read
0652 
0653 
0654 // Data Register
0655 /* BANK 2 */
0656 #define DATA_REG(lp)    SMC_REG(lp, 0x0008, 2)
0657 
0658 
0659 // Interrupt Status/Acknowledge Register
0660 /* BANK 2 */
0661 #define INT_REG(lp)     SMC_REG(lp, 0x000C, 2)
0662 
0663 
0664 // Interrupt Mask Register
0665 /* BANK 2 */
0666 #define IM_REG(lp)      SMC_REG(lp, 0x000D, 2)
0667 #define IM_MDINT    0x80 // PHY MI Register 18 Interrupt
0668 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
0669 #define IM_EPH_INT  0x20 // Set by Ethernet Protocol Handler section
0670 #define IM_RX_OVRN_INT  0x10 // Set by Receiver Overruns
0671 #define IM_ALLOC_INT    0x08 // Set when allocation request is completed
0672 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
0673 #define IM_TX_INT   0x02 // Transmit Interrupt
0674 #define IM_RCV_INT  0x01 // Receive Interrupt
0675 
0676 
0677 // Multicast Table Registers
0678 /* BANK 3 */
0679 #define MCAST_REG1(lp)  SMC_REG(lp, 0x0000, 3)
0680 #define MCAST_REG2(lp)  SMC_REG(lp, 0x0002, 3)
0681 #define MCAST_REG3(lp)  SMC_REG(lp, 0x0004, 3)
0682 #define MCAST_REG4(lp)  SMC_REG(lp, 0x0006, 3)
0683 
0684 
0685 // Management Interface Register (MII)
0686 /* BANK 3 */
0687 #define MII_REG(lp)     SMC_REG(lp, 0x0008, 3)
0688 #define MII_MSK_CRS100  0x4000 // Disables CRS100 detection during tx half dup
0689 #define MII_MDOE    0x0008 // MII Output Enable
0690 #define MII_MCLK    0x0004 // MII Clock, pin MDCLK
0691 #define MII_MDI     0x0002 // MII Input, pin MDI
0692 #define MII_MDO     0x0001 // MII Output, pin MDO
0693 
0694 
0695 // Revision Register
0696 /* BANK 3 */
0697 /* ( hi: chip id   low: rev # ) */
0698 #define REV_REG(lp)     SMC_REG(lp, 0x000A, 3)
0699 
0700 
0701 // Early RCV Register
0702 /* BANK 3 */
0703 /* this is NOT on SMC9192 */
0704 #define ERCV_REG(lp)    SMC_REG(lp, 0x000C, 3)
0705 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
0706 #define ERCV_THRESHOLD  0x001F // ERCV Threshold Mask
0707 
0708 
0709 // External Register
0710 /* BANK 7 */
0711 #define EXT_REG(lp)     SMC_REG(lp, 0x0000, 7)
0712 
0713 
0714 #define CHIP_9192   3
0715 #define CHIP_9194   4
0716 #define CHIP_9195   5
0717 #define CHIP_9196   6
0718 #define CHIP_91100  7
0719 #define CHIP_91100FD    8
0720 #define CHIP_91111FD    9
0721 
0722 static const char * chip_ids[ 16 ] =  {
0723     NULL, NULL, NULL,
0724     /* 3 */ "SMC91C90/91C92",
0725     /* 4 */ "SMC91C94",
0726     /* 5 */ "SMC91C95",
0727     /* 6 */ "SMC91C96",
0728     /* 7 */ "SMC91C100",
0729     /* 8 */ "SMC91C100FD",
0730     /* 9 */ "SMC91C11xFD",
0731     NULL, NULL, NULL,
0732     NULL, NULL, NULL};
0733 
0734 
0735 /*
0736  . Receive status bits
0737 */
0738 #define RS_ALGNERR  0x8000
0739 #define RS_BRODCAST 0x4000
0740 #define RS_BADCRC   0x2000
0741 #define RS_ODDFRAME 0x1000
0742 #define RS_TOOLONG  0x0800
0743 #define RS_TOOSHORT 0x0400
0744 #define RS_MULTICAST    0x0001
0745 #define RS_ERRORS   (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
0746 
0747 
0748 /*
0749  * PHY IDs
0750  *  LAN83C183 == LAN91C111 Internal PHY
0751  */
0752 #define PHY_LAN83C183   0x0016f840
0753 #define PHY_LAN83C180   0x02821c50
0754 
0755 /*
0756  * PHY Register Addresses (LAN91C111 Internal PHY)
0757  *
0758  * Generic PHY registers can be found in <linux/mii.h>
0759  *
0760  * These phy registers are specific to our on-board phy.
0761  */
0762 
0763 // PHY Configuration Register 1
0764 #define PHY_CFG1_REG        0x10
0765 #define PHY_CFG1_LNKDIS     0x8000  // 1=Rx Link Detect Function disabled
0766 #define PHY_CFG1_XMTDIS     0x4000  // 1=TP Transmitter Disabled
0767 #define PHY_CFG1_XMTPDN     0x2000  // 1=TP Transmitter Powered Down
0768 #define PHY_CFG1_BYPSCR     0x0400  // 1=Bypass scrambler/descrambler
0769 #define PHY_CFG1_UNSCDS     0x0200  // 1=Unscramble Idle Reception Disable
0770 #define PHY_CFG1_EQLZR      0x0100  // 1=Rx Equalizer Disabled
0771 #define PHY_CFG1_CABLE      0x0080  // 1=STP(150ohm), 0=UTP(100ohm)
0772 #define PHY_CFG1_RLVL0      0x0040  // 1=Rx Squelch level reduced by 4.5db
0773 #define PHY_CFG1_TLVL_SHIFT 2   // Transmit Output Level Adjust
0774 #define PHY_CFG1_TLVL_MASK  0x003C
0775 #define PHY_CFG1_TRF_MASK   0x0003  // Transmitter Rise/Fall time
0776 
0777 
0778 // PHY Configuration Register 2
0779 #define PHY_CFG2_REG        0x11
0780 #define PHY_CFG2_APOLDIS    0x0020  // 1=Auto Polarity Correction disabled
0781 #define PHY_CFG2_JABDIS     0x0010  // 1=Jabber disabled
0782 #define PHY_CFG2_MREG       0x0008  // 1=Multiple register access (MII mgt)
0783 #define PHY_CFG2_INTMDIO    0x0004  // 1=Interrupt signaled with MDIO pulseo
0784 
0785 // PHY Status Output (and Interrupt status) Register
0786 #define PHY_INT_REG     0x12    // Status Output (Interrupt Status)
0787 #define PHY_INT_INT     0x8000  // 1=bits have changed since last read
0788 #define PHY_INT_LNKFAIL     0x4000  // 1=Link Not detected
0789 #define PHY_INT_LOSSSYNC    0x2000  // 1=Descrambler has lost sync
0790 #define PHY_INT_CWRD        0x1000  // 1=Invalid 4B5B code detected on rx
0791 #define PHY_INT_SSD     0x0800  // 1=No Start Of Stream detected on rx
0792 #define PHY_INT_ESD     0x0400  // 1=No End Of Stream detected on rx
0793 #define PHY_INT_RPOL        0x0200  // 1=Reverse Polarity detected
0794 #define PHY_INT_JAB     0x0100  // 1=Jabber detected
0795 #define PHY_INT_SPDDET      0x0080  // 1=100Base-TX mode, 0=10Base-T mode
0796 #define PHY_INT_DPLXDET     0x0040  // 1=Device in Full Duplex
0797 
0798 // PHY Interrupt/Status Mask Register
0799 #define PHY_MASK_REG        0x13    // Interrupt Mask
0800 // Uses the same bit definitions as PHY_INT_REG
0801 
0802 
0803 /*
0804  * SMC91C96 ethernet config and status registers.
0805  * These are in the "attribute" space.
0806  */
0807 #define ECOR            0x8000
0808 #define ECOR_RESET      0x80
0809 #define ECOR_LEVEL_IRQ      0x40
0810 #define ECOR_WR_ATTRIB      0x04
0811 #define ECOR_ENABLE     0x01
0812 
0813 #define ECSR            0x8002
0814 #define ECSR_IOIS8      0x20
0815 #define ECSR_PWRDWN     0x04
0816 #define ECSR_INT        0x02
0817 
0818 #define ATTRIB_SIZE     ((64*1024) << SMC_IO_SHIFT)
0819 
0820 
0821 /*
0822  * Macros to abstract register access according to the data bus
0823  * capabilities.  Please use those and not the in/out primitives.
0824  * Note: the following macros do *not* select the bank -- this must
0825  * be done separately as needed in the main code.  The SMC_REG() macro
0826  * only uses the bank argument for debugging purposes (when enabled).
0827  *
0828  * Note: despite inline functions being safer, everything leading to this
0829  * should preferably be macros to let BUG() display the line number in
0830  * the core source code since we're interested in the top call site
0831  * not in any inline function location.
0832  */
0833 
0834 #if SMC_DEBUG > 0
0835 #define SMC_REG(lp, reg, bank)                  \
0836     ({                              \
0837         int __b = SMC_CURRENT_BANK(lp);         \
0838         if (unlikely((__b & ~0xf0) != (0x3300 | bank))) {   \
0839             pr_err("%s: bank reg screwed (0x%04x)\n",   \
0840                    CARDNAME, __b);              \
0841             BUG();                      \
0842         }                           \
0843         reg<<SMC_IO_SHIFT;                  \
0844     })
0845 #else
0846 #define SMC_REG(lp, reg, bank)  (reg<<SMC_IO_SHIFT)
0847 #endif
0848 
0849 /*
0850  * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
0851  * aligned to a 32 bit boundary.  I tell you that does exist!
0852  * Fortunately the affected register accesses can be easily worked around
0853  * since we can write zeroes to the preceding 16 bits without adverse
0854  * effects and use a 32-bit access.
0855  *
0856  * Enforce it on any 32-bit capable setup for now.
0857  */
0858 #define SMC_MUST_ALIGN_WRITE(lp)    SMC_32BIT(lp)
0859 
0860 #define SMC_GET_PN(lp)                      \
0861     (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, PN_REG(lp))) \
0862                 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
0863 
0864 #define SMC_SET_PN(lp, x)                       \
0865     do {                                \
0866         if (SMC_MUST_ALIGN_WRITE(lp))               \
0867             SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2));   \
0868         else if (SMC_8BIT(lp))              \
0869             SMC_outb(x, ioaddr, PN_REG(lp));        \
0870         else                            \
0871             SMC_outw(lp, x, ioaddr, PN_REG(lp));        \
0872     } while (0)
0873 
0874 #define SMC_GET_AR(lp)                      \
0875     (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, AR_REG(lp))) \
0876                 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
0877 
0878 #define SMC_GET_TXFIFO(lp)                      \
0879     (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
0880                 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
0881 
0882 #define SMC_GET_RXFIFO(lp)                      \
0883     (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
0884                 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
0885 
0886 #define SMC_GET_INT(lp)                     \
0887     (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, INT_REG(lp)))    \
0888                 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
0889 
0890 #define SMC_ACK_INT(lp, x)                      \
0891     do {                                \
0892         if (SMC_8BIT(lp))                   \
0893             SMC_outb(x, ioaddr, INT_REG(lp));       \
0894         else {                          \
0895             unsigned long __flags;              \
0896             int __mask;                 \
0897             local_irq_save(__flags);            \
0898             __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
0899             SMC_outw(lp, __mask | (x), ioaddr, INT_REG(lp)); \
0900             local_irq_restore(__flags);         \
0901         }                           \
0902     } while (0)
0903 
0904 #define SMC_GET_INT_MASK(lp)                        \
0905     (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, IM_REG(lp))) \
0906                 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
0907 
0908 #define SMC_SET_INT_MASK(lp, x)                 \
0909     do {                                \
0910         if (SMC_8BIT(lp))                   \
0911             SMC_outb(x, ioaddr, IM_REG(lp));        \
0912         else                            \
0913             SMC_outw(lp, (x) << 8, ioaddr, INT_REG(lp));    \
0914     } while (0)
0915 
0916 #define SMC_CURRENT_BANK(lp)    SMC_inw(ioaddr, BANK_SELECT)
0917 
0918 #define SMC_SELECT_BANK(lp, x)                  \
0919     do {                                \
0920         if (SMC_MUST_ALIGN_WRITE(lp))               \
0921             SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT);    \
0922         else                            \
0923             SMC_outw(lp, x, ioaddr, BANK_SELECT);       \
0924     } while (0)
0925 
0926 #define SMC_GET_BASE(lp)        SMC_inw(ioaddr, BASE_REG(lp))
0927 
0928 #define SMC_SET_BASE(lp, x) SMC_outw(lp, x, ioaddr, BASE_REG(lp))
0929 
0930 #define SMC_GET_CONFIG(lp)  SMC_inw(ioaddr, CONFIG_REG(lp))
0931 
0932 #define SMC_SET_CONFIG(lp, x)   SMC_outw(lp, x, ioaddr, CONFIG_REG(lp))
0933 
0934 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
0935 
0936 #define SMC_GET_CTL(lp)     SMC_inw(ioaddr, CTL_REG(lp))
0937 
0938 #define SMC_SET_CTL(lp, x)  SMC_outw(lp, x, ioaddr, CTL_REG(lp))
0939 
0940 #define SMC_GET_MII(lp)     SMC_inw(ioaddr, MII_REG(lp))
0941 
0942 #define SMC_GET_GP(lp)      SMC_inw(ioaddr, GP_REG(lp))
0943 
0944 #define SMC_SET_GP(lp, x)                       \
0945     do {                                \
0946         if (SMC_MUST_ALIGN_WRITE(lp))               \
0947             SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1));   \
0948         else                            \
0949             SMC_outw(lp, x, ioaddr, GP_REG(lp));        \
0950     } while (0)
0951 
0952 #define SMC_SET_MII(lp, x)  SMC_outw(lp, x, ioaddr, MII_REG(lp))
0953 
0954 #define SMC_GET_MIR(lp)     SMC_inw(ioaddr, MIR_REG(lp))
0955 
0956 #define SMC_SET_MIR(lp, x)  SMC_outw(lp, x, ioaddr, MIR_REG(lp))
0957 
0958 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
0959 
0960 #define SMC_SET_MMU_CMD(lp, x)  SMC_outw(lp, x, ioaddr, MMU_CMD_REG(lp))
0961 
0962 #define SMC_GET_FIFO(lp)    SMC_inw(ioaddr, FIFO_REG(lp))
0963 
0964 #define SMC_GET_PTR(lp)     SMC_inw(ioaddr, PTR_REG(lp))
0965 
0966 #define SMC_SET_PTR(lp, x)                      \
0967     do {                                \
0968         if (SMC_MUST_ALIGN_WRITE(lp))               \
0969             SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2));   \
0970         else                            \
0971             SMC_outw(lp, x, ioaddr, PTR_REG(lp));       \
0972     } while (0)
0973 
0974 #define SMC_GET_EPH_STATUS(lp)  SMC_inw(ioaddr, EPH_STATUS_REG(lp))
0975 
0976 #define SMC_GET_RCR(lp)     SMC_inw(ioaddr, RCR_REG(lp))
0977 
0978 #define SMC_SET_RCR(lp, x)      SMC_outw(lp, x, ioaddr, RCR_REG(lp))
0979 
0980 #define SMC_GET_REV(lp)     SMC_inw(ioaddr, REV_REG(lp))
0981 
0982 #define SMC_GET_RPC(lp)     SMC_inw(ioaddr, RPC_REG(lp))
0983 
0984 #define SMC_SET_RPC(lp, x)                      \
0985     do {                                \
0986         if (SMC_MUST_ALIGN_WRITE(lp))               \
0987             SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0));   \
0988         else                            \
0989             SMC_outw(lp, x, ioaddr, RPC_REG(lp));       \
0990     } while (0)
0991 
0992 #define SMC_GET_TCR(lp)     SMC_inw(ioaddr, TCR_REG(lp))
0993 
0994 #define SMC_SET_TCR(lp, x)  SMC_outw(lp, x, ioaddr, TCR_REG(lp))
0995 
0996 #ifndef SMC_GET_MAC_ADDR
0997 #define SMC_GET_MAC_ADDR(lp, addr)                  \
0998     do {                                \
0999         unsigned int __v;                   \
1000         __v = SMC_inw(ioaddr, ADDR0_REG(lp));           \
1001         addr[0] = __v; addr[1] = __v >> 8;          \
1002         __v = SMC_inw(ioaddr, ADDR1_REG(lp));           \
1003         addr[2] = __v; addr[3] = __v >> 8;          \
1004         __v = SMC_inw(ioaddr, ADDR2_REG(lp));           \
1005         addr[4] = __v; addr[5] = __v >> 8;          \
1006     } while (0)
1007 #endif
1008 
1009 #define SMC_SET_MAC_ADDR(lp, addr)                  \
1010     do {                                \
1011         SMC_outw(lp, addr[0] | (addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1012         SMC_outw(lp, addr[2] | (addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1013         SMC_outw(lp, addr[4] | (addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1014     } while (0)
1015 
1016 #define SMC_SET_MCAST(lp, x)                        \
1017     do {                                \
1018         const unsigned char *mt = (x);              \
1019         SMC_outw(lp, mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1020         SMC_outw(lp, mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1021         SMC_outw(lp, mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1022         SMC_outw(lp, mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1023     } while (0)
1024 
1025 #define SMC_PUT_PKT_HDR(lp, status, length)             \
1026     do {                                \
1027         if (SMC_32BIT(lp))                  \
1028             SMC_outl((status) | (length)<<16, ioaddr,   \
1029                  DATA_REG(lp));         \
1030         else {                          \
1031             SMC_outw(lp, status, ioaddr, DATA_REG(lp)); \
1032             SMC_outw(lp, length, ioaddr, DATA_REG(lp)); \
1033         }                           \
1034     } while (0)
1035 
1036 #define SMC_GET_PKT_HDR(lp, status, length)             \
1037     do {                                \
1038         if (SMC_32BIT(lp)) {                \
1039             unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1040             (status) = __val & 0xffff;          \
1041             (length) = __val >> 16;             \
1042         } else {                        \
1043             (status) = SMC_inw(ioaddr, DATA_REG(lp));   \
1044             (length) = SMC_inw(ioaddr, DATA_REG(lp));   \
1045         }                           \
1046     } while (0)
1047 
1048 #define SMC_PUSH_DATA(lp, p, l)                 \
1049     do {                                \
1050         if (SMC_32BIT(lp)) {                \
1051             void *__ptr = (p);              \
1052             int __len = (l);                \
1053             void __iomem *__ioaddr = ioaddr;        \
1054             if (__len >= 2 && (unsigned long)__ptr & 2) {   \
1055                 __len -= 2;             \
1056                 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1057                 __ptr += 2;             \
1058             }                       \
1059             if (SMC_CAN_USE_DATACS && lp->datacs)       \
1060                 __ioaddr = lp->datacs;          \
1061             SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1062             if (__len & 2) {                \
1063                 __ptr += (__len & ~3);          \
1064                 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1065             }                       \
1066         } else if (SMC_16BIT(lp))               \
1067             SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1);   \
1068         else if (SMC_8BIT(lp))              \
1069             SMC_outsb(ioaddr, DATA_REG(lp), p, l);  \
1070     } while (0)
1071 
1072 #define SMC_PULL_DATA(lp, p, l)                 \
1073     do {                                \
1074         if (SMC_32BIT(lp)) {                \
1075             void *__ptr = (p);              \
1076             int __len = (l);                \
1077             void __iomem *__ioaddr = ioaddr;        \
1078             if ((unsigned long)__ptr & 2) {         \
1079                 /*                  \
1080                  * We want 32bit alignment here.    \
1081                  * Since some buses perform a full  \
1082                  * 32bit fetch even for 16bit data  \
1083                  * we can't use SMC_inw() here.     \
1084                  * Back both source (on-chip) and   \
1085                  * destination pointers of 2 bytes. \
1086                  * This is possible since the call to   \
1087                  * SMC_GET_PKT_HDR() already advanced   \
1088                  * the source pointer of 4 bytes, and   \
1089                  * the skb_reserve(skb, 2) advanced \
1090                  * the destination pointer of 2 bytes.  \
1091                  */                 \
1092                 __ptr -= 2;             \
1093                 __len += 2;             \
1094                 SMC_SET_PTR(lp,         \
1095                     2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1096             }                       \
1097             if (SMC_CAN_USE_DATACS && lp->datacs)       \
1098                 __ioaddr = lp->datacs;          \
1099             __len += 2;                 \
1100             SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1101         } else if (SMC_16BIT(lp))               \
1102             SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1);    \
1103         else if (SMC_8BIT(lp))              \
1104             SMC_insb(ioaddr, DATA_REG(lp), p, l);       \
1105     } while (0)
1106 
1107 #endif  /* _SMC91X_H_ */
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