ethernet/smsc/smc9194.h

0001 /*------------------------------------------------------------------------
0002  . smc9194.h
0003  . Copyright (C) 1996 by Erik Stahlman
0004  .
0005  . This software may be used and distributed according to the terms
0006  . of the GNU General Public License, incorporated herein by reference.
0007  .
0008  . This file contains register information and access macros for
0009  . the SMC91xxx chipset.
0010  .
0011  . Information contained in this file was obtained from the SMC91C94
0012  . manual from SMC.  To get a copy, if you really want one, you can find
0013  . information under www.smc.com in the components division.
0014  . ( this thanks to advice from Donald Becker ).
0015  .
0016  . Authors
0017  .  Erik Stahlman               ( erik@vt.edu )
0018  .
0019  . History
0020  . 01/06/96      Erik Stahlman   moved definitions here from main .c file
0021  . 01/19/96      Erik Stahlman    polished this up some, and added better
0022  .                                        error handling
0023  .
0024  ---------------------------------------------------------------------------*/
0025 #ifndef _SMC9194_H_
0026 #define _SMC9194_H_
0027
0028 /* I want some simple types */
0029
0030 typedef unsigned char           byte;
0031 typedef unsigned short          word;
0032 typedef unsigned long int       dword;
0033
0034
0035 /* Because of bank switching, the SMC91xxx uses only 16 I/O ports */
0036
0037 #define SMC_IO_EXTENT   16
0038
0039
0040 /*---------------------------------------------------------------
0041  .
0042  . A description of the SMC registers is probably in order here,
0043  . although for details, the SMC datasheet is invaluable.
0044  .
0045  . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
0046  . are accessed by writing a number into the BANK_SELECT register
0047  . ( I also use a SMC_SELECT_BANK macro for this ).
0048  .
0049  . The banks are configured so that for most purposes, bank 2 is all
0050  . that is needed for simple run time tasks.
0051  -----------------------------------------------------------------------*/
0052
0053 /*
0054  . Bank Select Register:
0055  .
0056  .      yyyy yyyy 0000 00xx
0057  .      xx      = bank number
0058  .      yyyy yyyy   = 0x33, for identification purposes.
0059 */
0060 #define BANK_SELECT     14
0061
0062 /* BANK 0  */
0063
0064 #define TCR         0       /* transmit control register */
0065 #define TCR_ENABLE  0x0001  /* if this is 1, we can transmit */
0066 #define TCR_FDUPLX      0x0800  /* receive packets sent out */
0067 #define TCR_STP_SQET    0x1000  /* stop transmitting if Signal quality error */
0068 #define TCR_MON_CNS 0x0400  /* monitors the carrier status */
0069 #define TCR_PAD_ENABLE  0x0080  /* pads short packets to 64 bytes */
0070
0071 #define TCR_CLEAR   0   /* do NOTHING */
0072 /* the normal settings for the TCR register : */
0073 /* QUESTION: do I want to enable padding of short packets ? */
0074 #define TCR_NORMAL      TCR_ENABLE
0075
0076
0077 #define EPH_STATUS  2
0078 #define ES_LINK_OK  0x4000  /* is the link integrity ok ? */
0079
0080 #define RCR     4
0081 #define RCR_SOFTRESET   0x8000  /* resets the chip */
0082 #define RCR_STRIP_CRC   0x200   /* strips CRC */
0083 #define RCR_ENABLE  0x100   /* IFF this is set, we can receive packets */
0084 #define RCR_ALMUL   0x4     /* receive all multicast packets */
0085 #define RCR_PROMISC 0x2 /* enable promiscuous mode */
0086
0087 /* the normal settings for the RCR register : */
0088 #define RCR_NORMAL  (RCR_STRIP_CRC | RCR_ENABLE)
0089 #define RCR_CLEAR   0x0     /* set it to a base state */
0090
0091 #define COUNTER     6
0092 #define MIR     8
0093 #define MCR     10
0094 /* 12 is reserved */
0095
0096 /* BANK 1 */
0097 #define CONFIG          0
0098 #define CFG_AUI_SELECT      0x100
0099 #define BASE            2
0100 #define ADDR0           4
0101 #define ADDR1           6
0102 #define ADDR2           8
0103 #define GENERAL         10
0104 #define CONTROL         12
0105 #define CTL_POWERDOWN       0x2000
0106 #define CTL_LE_ENABLE       0x80
0107 #define CTL_CR_ENABLE       0x40
0108 #define CTL_TE_ENABLE       0x0020
0109 #define CTL_AUTO_RELEASE    0x0800
0110 #define CTL_EPROM_ACCESS    0x0003 /* high if Eprom is being read */
0111
0112 /* BANK 2 */
0113 #define MMU_CMD     0
0114 #define MC_BUSY     1   /* only readable bit in the register */
0115 #define MC_NOP      0
0116 #define MC_ALLOC    0x20    /* or with number of 256 byte packets */
0117 #define MC_RESET    0x40
0118 #define MC_REMOVE   0x60    /* remove the current rx packet */
0119 #define MC_RELEASE      0x80    /* remove and release the current rx packet */
0120 #define MC_FREEPKT      0xA0    /* Release packet in PNR register */
0121 #define MC_ENQUEUE  0xC0    /* Enqueue the packet for transmit */
0122
0123 #define PNR_ARR     2
0124 #define FIFO_PORTS  4
0125
0126 #define FP_RXEMPTY  0x8000
0127 #define FP_TXEMPTY  0x80
0128
0129 #define POINTER     6
0130 #define PTR_READ    0x2000
0131 #define PTR_RCV     0x8000
0132 #define PTR_AUTOINC     0x4000
0133 #define PTR_AUTO_INC    0x0040
0134
0135 #define DATA_1      8
0136 #define DATA_2      10
0137 #define INTERRUPT   12
0138
0139 #define INT_MASK    13
0140 #define IM_RCV_INT  0x1
0141 #define IM_TX_INT   0x2
0142 #define IM_TX_EMPTY_INT 0x4
0143 #define IM_ALLOC_INT    0x8
0144 #define IM_RX_OVRN_INT  0x10
0145 #define IM_EPH_INT  0x20
0146 #define IM_ERCV_INT 0x40 /* not on SMC9192 */
0147
0148 /* BANK 3 */
0149 #define MULTICAST1  0
0150 #define MULTICAST2  2
0151 #define MULTICAST3  4
0152 #define MULTICAST4  6
0153 #define MGMT        8
0154 #define REVISION    10 /* ( hi: chip id   low: rev # ) */
0155
0156
0157 /* this is NOT on SMC9192 */
0158 #define ERCV        12
0159
0160 #define CHIP_9190   3
0161 #define CHIP_9194   4
0162 #define CHIP_9195   5
0163 #define CHIP_91100  7
0164
0165 static const char * chip_ids[ 15 ] =  {
0166     NULL, NULL, NULL,
0167     /* 3 */ "SMC91C90/91C92",
0168     /* 4 */ "SMC91C94",
0169     /* 5 */ "SMC91C95",
0170     NULL,
0171     /* 7 */ "SMC91C100",
0172     /* 8 */ "SMC91C100FD",
0173     NULL, NULL, NULL,
0174     NULL, NULL, NULL};
0175
0176 /*
0177  . Transmit status bits
0178 */
0179 #define TS_SUCCESS 0x0001
0180 #define TS_LOSTCAR 0x0400
0181 #define TS_LATCOL  0x0200
0182 #define TS_16COL   0x0010
0183
0184 /*
0185  . Receive status bits
0186 */
0187 #define RS_ALGNERR  0x8000
0188 #define RS_BADCRC   0x2000
0189 #define RS_ODDFRAME 0x1000
0190 #define RS_TOOLONG  0x0800
0191 #define RS_TOOSHORT 0x0400
0192 #define RS_MULTICAST    0x0001
0193 #define RS_ERRORS   (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
0194
0195 static const char * interfaces[ 2 ] = { "TP", "AUI" };
0196
0197 /*-------------------------------------------------------------------------
0198  .  I define some macros to make it easier to do somewhat common
0199  . or slightly complicated, repeated tasks.
0200  --------------------------------------------------------------------------*/
0201
0202 /* select a register bank, 0 to 3  */
0203
0204 #define SMC_SELECT_BANK(x)  { outw( x, ioaddr + BANK_SELECT ); }
0205
0206 /* define a small delay for the reset */
0207 #define SMC_DELAY() { inw( ioaddr + RCR );\
0208             inw( ioaddr + RCR );\
0209             inw( ioaddr + RCR );  }
0210
0211 /* this enables an interrupt in the interrupt mask register */
0212 #define SMC_ENABLE_INT(x) {\
0213         unsigned char mask;\
0214         SMC_SELECT_BANK(2);\
0215         mask = inb( ioaddr + INT_MASK );\
0216         mask |= (x);\
0217         outb( mask, ioaddr + INT_MASK ); \
0218 }
0219
0220 /* this disables an interrupt from the interrupt mask register */
0221
0222 #define SMC_DISABLE_INT(x) {\
0223         unsigned char mask;\
0224         SMC_SELECT_BANK(2);\
0225         mask = inb( ioaddr + INT_MASK );\
0226         mask &= ~(x);\
0227         outb( mask, ioaddr + INT_MASK ); \
0228 }
0229
0230 /*----------------------------------------------------------------------
0231  . Define the interrupts that I want to receive from the card
0232  .
0233  . I want:
0234  .  IM_EPH_INT, for nasty errors
0235  .  IM_RCV_INT, for happy received packets
0236  .  IM_RX_OVRN_INT, because I have to kick the receiver
0237  --------------------------------------------------------------------------*/
0238 #define SMC_INTERRUPT_MASK   (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT)
0239
0240 #endif  /* _SMC_9194_H_ */
0241