ethernet/smsc/smc911x.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*------------------------------------------------------------------------
0003  . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
0004  .
0005  . Copyright (C) 2005 Sensoria Corp.
0006  . Derived from the unified SMC91x driver by Nicolas Pitre
0007  .
0008  .
0009  . Information contained in this file was obtained from the LAN9118
0010  . manual from SMC.  To get a copy, if you really want one, you can find
0011  . information under www.smsc.com.
0012  .
0013  . Authors
0014  .   Dustin McIntire         <dustin@sensoria.com>
0015  .
0016  ---------------------------------------------------------------------------*/
0017 #ifndef _SMC911X_H_
0018 #define _SMC911X_H_
0019
0020 #include <linux/smc911x.h>
0021 /*
0022  * Use the DMA feature on PXA chips
0023  */
0024 #ifdef CONFIG_ARCH_PXA
0025   #define SMC_USE_PXA_DMA   1
0026   #define SMC_USE_16BIT     0
0027   #define SMC_USE_32BIT     1
0028   #define SMC_IRQ_SENSE     IRQF_TRIGGER_FALLING
0029 #elif defined(CONFIG_SH_MAGIC_PANEL_R2)
0030   #define SMC_USE_16BIT     0
0031   #define SMC_USE_32BIT     1
0032   #define SMC_IRQ_SENSE     IRQF_TRIGGER_LOW
0033 #elif defined(CONFIG_ARCH_OMAP3)
0034   #define SMC_USE_16BIT     0
0035   #define SMC_USE_32BIT     1
0036   #define SMC_IRQ_SENSE     IRQF_TRIGGER_LOW
0037   #define SMC_MEM_RESERVED  1
0038 #elif defined(CONFIG_ARCH_OMAP2)
0039   #define SMC_USE_16BIT     0
0040   #define SMC_USE_32BIT     1
0041   #define SMC_IRQ_SENSE     IRQF_TRIGGER_LOW
0042   #define SMC_MEM_RESERVED  1
0043 #else
0044 /*
0045  * Default configuration
0046  */
0047
0048 #define SMC_DYNAMIC_BUS_CONFIG
0049 #endif
0050
0051 #ifdef SMC_USE_PXA_DMA
0052 #define SMC_USE_DMA
0053 #endif
0054
0055 /* store this information for the driver.. */
0056 struct smc911x_local {
0057     /*
0058      * If I have to wait until the DMA is finished and ready to reload a
0059      * packet, I will store the skbuff here. Then, the DMA will send it
0060      * out and free it.
0061      */
0062     struct sk_buff *pending_tx_skb;
0063
0064     /* version/revision of the SMC911x chip */
0065     u16 version;
0066     u16 revision;
0067
0068     /* FIFO sizes */
0069     int tx_fifo_kb;
0070     int tx_fifo_size;
0071     int rx_fifo_size;
0072     int afc_cfg;
0073
0074     /* Contains the current active receive/phy mode */
0075     int ctl_rfduplx;
0076     int ctl_rspeed;
0077
0078     u32 msg_enable;
0079     u32 phy_type;
0080     struct mii_if_info mii;
0081
0082     /* work queue */
0083     struct work_struct phy_configure;
0084
0085     int tx_throttle;
0086     spinlock_t lock;
0087
0088     struct net_device *netdev;
0089
0090 #ifdef SMC_USE_DMA
0091     /* DMA needs the physical address of the chip */
0092     u_long physaddr;
0093     struct dma_chan *rxdma;
0094     struct dma_chan *txdma;
0095     int rxdma_active;
0096     int txdma_active;
0097     struct sk_buff *current_rx_skb;
0098     struct sk_buff *current_tx_skb;
0099     struct device *dev;
0100 #endif
0101     void __iomem *base;
0102 #ifdef SMC_DYNAMIC_BUS_CONFIG
0103     struct smc911x_platdata cfg;
0104 #endif
0105 };
0106
0107 /*
0108  * Define the bus width specific IO macros
0109  */
0110
0111 #ifdef SMC_DYNAMIC_BUS_CONFIG
0112 static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg)
0113 {
0114     void __iomem *ioaddr = lp->base + reg;
0115
0116     if (lp->cfg.flags & SMC911X_USE_32BIT)
0117         return readl(ioaddr);
0118
0119     if (lp->cfg.flags & SMC911X_USE_16BIT)
0120         return readw(ioaddr) | (readw(ioaddr + 2) << 16);
0121
0122     BUG();
0123 }
0124
0125 static inline void SMC_outl(unsigned int value, struct smc911x_local *lp,
0126                 int reg)
0127 {
0128     void __iomem *ioaddr = lp->base + reg;
0129
0130     if (lp->cfg.flags & SMC911X_USE_32BIT) {
0131         writel(value, ioaddr);
0132         return;
0133     }
0134
0135     if (lp->cfg.flags & SMC911X_USE_16BIT) {
0136         writew(value & 0xffff, ioaddr);
0137         writew(value >> 16, ioaddr + 2);
0138         return;
0139     }
0140
0141     BUG();
0142 }
0143
0144 static inline void SMC_insl(struct smc911x_local *lp, int reg,
0145                   void *addr, unsigned int count)
0146 {
0147     void __iomem *ioaddr = lp->base + reg;
0148
0149     if (lp->cfg.flags & SMC911X_USE_32BIT) {
0150         ioread32_rep(ioaddr, addr, count);
0151         return;
0152     }
0153
0154     if (lp->cfg.flags & SMC911X_USE_16BIT) {
0155         ioread16_rep(ioaddr, addr, count * 2);
0156         return;
0157     }
0158
0159     BUG();
0160 }
0161
0162 static inline void SMC_outsl(struct smc911x_local *lp, int reg,
0163                  void *addr, unsigned int count)
0164 {
0165     void __iomem *ioaddr = lp->base + reg;
0166
0167     if (lp->cfg.flags & SMC911X_USE_32BIT) {
0168         iowrite32_rep(ioaddr, addr, count);
0169         return;
0170     }
0171
0172     if (lp->cfg.flags & SMC911X_USE_16BIT) {
0173         iowrite16_rep(ioaddr, addr, count * 2);
0174         return;
0175     }
0176
0177     BUG();
0178 }
0179 #else
0180 #if SMC_USE_16BIT
0181 #define SMC_inl(lp, r)       ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
0182 #define SMC_outl(v, lp, r)           \
0183     do{                  \
0184          writew(v & 0xFFFF, (lp)->base + (r));   \
0185          writew(v >> 16, (lp)->base + (r) + 2); \
0186      } while (0)
0187 #define SMC_insl(lp, r, p, l)    ioread16_rep((short*)((lp)->base + (r)), p, l*2)
0188 #define SMC_outsl(lp, r, p, l)   iowrite16_rep((short*)((lp)->base + (r)), p, l*2)
0189
0190 #elif   SMC_USE_32BIT
0191 #define SMC_inl(lp, r)       readl((lp)->base + (r))
0192 #define SMC_outl(v, lp, r)   writel(v, (lp)->base + (r))
0193 #define SMC_insl(lp, r, p, l)    ioread32_rep((int*)((lp)->base + (r)), p, l)
0194 #define SMC_outsl(lp, r, p, l)   iowrite32_rep((int*)((lp)->base + (r)), p, l)
0195
0196 #endif /* SMC_USE_16BIT */
0197 #endif /* SMC_DYNAMIC_BUS_CONFIG */
0198
0199
0200 #ifdef SMC_USE_PXA_DMA
0201
0202 /*
0203  * Use a DMA for RX and TX packets.
0204  */
0205 #include <linux/dma-mapping.h>
0206
0207 static dma_addr_t rx_dmabuf, tx_dmabuf;
0208 static int rx_dmalen, tx_dmalen;
0209 static void smc911x_rx_dma_irq(void *data);
0210 static void smc911x_tx_dma_irq(void *data);
0211
0212 #ifdef SMC_insl
0213 #undef SMC_insl
0214 #define SMC_insl(lp, r, p, l) \
0215     smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
0216
0217 static inline void
0218 smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
0219         int reg, struct dma_chan *dma, u_char *buf, int len)
0220 {
0221     struct dma_async_tx_descriptor *tx;
0222
0223     /* 64 bit alignment is required for memory to memory DMA */
0224     if ((long)buf & 4) {
0225         *((u32 *)buf) = SMC_inl(lp, reg);
0226         buf += 4;
0227         len--;
0228     }
0229
0230     len *= 4;
0231     rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
0232     rx_dmalen = len;
0233     tx = dmaengine_prep_slave_single(dma, rx_dmabuf, rx_dmalen,
0234                      DMA_DEV_TO_MEM, 0);
0235     if (tx) {
0236         tx->callback = smc911x_rx_dma_irq;
0237         tx->callback_param = lp;
0238         dmaengine_submit(tx);
0239         dma_async_issue_pending(dma);
0240     }
0241 }
0242 #endif
0243
0244 #ifdef SMC_outsl
0245 #undef SMC_outsl
0246 #define SMC_outsl(lp, r, p, l) \
0247      smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
0248
0249 static inline void
0250 smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
0251         int reg, struct dma_chan *dma, u_char *buf, int len)
0252 {
0253     struct dma_async_tx_descriptor *tx;
0254
0255     /* 64 bit alignment is required for memory to memory DMA */
0256     if ((long)buf & 4) {
0257         SMC_outl(*((u32 *)buf), lp, reg);
0258         buf += 4;
0259         len--;
0260     }
0261
0262     len *= 4;
0263     tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
0264     tx_dmalen = len;
0265     tx = dmaengine_prep_slave_single(dma, tx_dmabuf, tx_dmalen,
0266                      DMA_DEV_TO_MEM, 0);
0267     if (tx) {
0268         tx->callback = smc911x_tx_dma_irq;
0269         tx->callback_param = lp;
0270         dmaengine_submit(tx);
0271         dma_async_issue_pending(dma);
0272     }
0273 }
0274 #endif
0275 #endif   /* SMC_USE_PXA_DMA */
0276
0277
0278 /* Chip Parameters and Register Definitions */
0279
0280 #define SMC911X_TX_FIFO_LOW_THRESHOLD   (1536*2)
0281
0282 #define SMC911X_IO_EXTENT    0x100
0283
0284 #define SMC911X_EEPROM_LEN   7
0285
0286 /* Below are the register offsets and bit definitions
0287  * of the Lan911x memory space
0288  */
0289 #define RX_DATA_FIFO         (0x00)
0290
0291 #define TX_DATA_FIFO         (0x20)
0292 #define TX_CMD_A_INT_ON_COMP_       (0x80000000)
0293 #define TX_CMD_A_INT_BUF_END_ALGN_  (0x03000000)
0294 #define TX_CMD_A_INT_4_BYTE_ALGN_   (0x00000000)
0295 #define TX_CMD_A_INT_16_BYTE_ALGN_  (0x01000000)
0296 #define TX_CMD_A_INT_32_BYTE_ALGN_  (0x02000000)
0297 #define TX_CMD_A_INT_DATA_OFFSET_   (0x001F0000)
0298 #define TX_CMD_A_INT_FIRST_SEG_     (0x00002000)
0299 #define TX_CMD_A_INT_LAST_SEG_      (0x00001000)
0300 #define TX_CMD_A_BUF_SIZE_      (0x000007FF)
0301 #define TX_CMD_B_PKT_TAG_       (0xFFFF0000)
0302 #define TX_CMD_B_ADD_CRC_DISABLE_   (0x00002000)
0303 #define TX_CMD_B_DISABLE_PADDING_   (0x00001000)
0304 #define TX_CMD_B_PKT_BYTE_LENGTH_   (0x000007FF)
0305
0306 #define RX_STATUS_FIFO      (0x40)
0307 #define RX_STS_PKT_LEN_         (0x3FFF0000)
0308 #define RX_STS_ES_          (0x00008000)
0309 #define RX_STS_BCST_            (0x00002000)
0310 #define RX_STS_LEN_ERR_         (0x00001000)
0311 #define RX_STS_RUNT_ERR_        (0x00000800)
0312 #define RX_STS_MCAST_           (0x00000400)
0313 #define RX_STS_TOO_LONG_        (0x00000080)
0314 #define RX_STS_COLL_            (0x00000040)
0315 #define RX_STS_ETH_TYPE_        (0x00000020)
0316 #define RX_STS_WDOG_TMT_        (0x00000010)
0317 #define RX_STS_MII_ERR_         (0x00000008)
0318 #define RX_STS_DRIBBLING_       (0x00000004)
0319 #define RX_STS_CRC_ERR_         (0x00000002)
0320 #define RX_STATUS_FIFO_PEEK     (0x44)
0321 #define TX_STATUS_FIFO      (0x48)
0322 #define TX_STS_TAG_         (0xFFFF0000)
0323 #define TX_STS_ES_          (0x00008000)
0324 #define TX_STS_LOC_         (0x00000800)
0325 #define TX_STS_NO_CARR_         (0x00000400)
0326 #define TX_STS_LATE_COLL_       (0x00000200)
0327 #define TX_STS_MANY_COLL_       (0x00000100)
0328 #define TX_STS_COLL_CNT_        (0x00000078)
0329 #define TX_STS_MANY_DEFER_      (0x00000004)
0330 #define TX_STS_UNDERRUN_        (0x00000002)
0331 #define TX_STS_DEFERRED_        (0x00000001)
0332 #define TX_STATUS_FIFO_PEEK (0x4C)
0333 #define ID_REV          (0x50)
0334 #define ID_REV_CHIP_ID_         (0xFFFF0000)  /* RO */
0335 #define ID_REV_REV_ID_          (0x0000FFFF)  /* RO */
0336
0337 #define INT_CFG         (0x54)
0338 #define INT_CFG_INT_DEAS_       (0xFF000000)  /* R/W */
0339 #define INT_CFG_INT_DEAS_CLR_       (0x00004000)
0340 #define INT_CFG_INT_DEAS_STS_       (0x00002000)
0341 #define INT_CFG_IRQ_INT_        (0x00001000)  /* RO */
0342 #define INT_CFG_IRQ_EN_         (0x00000100)  /* R/W */
0343 #define INT_CFG_IRQ_POL_        (0x00000010)  /* R/W Not Affected by SW Reset */
0344 #define INT_CFG_IRQ_TYPE_       (0x00000001)  /* R/W Not Affected by SW Reset */
0345
0346 #define INT_STS         (0x58)
0347 #define INT_STS_SW_INT_         (0x80000000)  /* R/WC */
0348 #define INT_STS_TXSTOP_INT_     (0x02000000)  /* R/WC */
0349 #define INT_STS_RXSTOP_INT_     (0x01000000)  /* R/WC */
0350 #define INT_STS_RXDFH_INT_      (0x00800000)  /* R/WC */
0351 #define INT_STS_RXDF_INT_       (0x00400000)  /* R/WC */
0352 #define INT_STS_TX_IOC_         (0x00200000)  /* R/WC */
0353 #define INT_STS_RXD_INT_        (0x00100000)  /* R/WC */
0354 #define INT_STS_GPT_INT_        (0x00080000)  /* R/WC */
0355 #define INT_STS_PHY_INT_        (0x00040000)  /* RO */
0356 #define INT_STS_PME_INT_        (0x00020000)  /* R/WC */
0357 #define INT_STS_TXSO_           (0x00010000)  /* R/WC */
0358 #define INT_STS_RWT_            (0x00008000)  /* R/WC */
0359 #define INT_STS_RXE_            (0x00004000)  /* R/WC */
0360 #define INT_STS_TXE_            (0x00002000)  /* R/WC */
0361 //#define   INT_STS_ERX_        (0x00001000)  /* R/WC */
0362 #define INT_STS_TDFU_           (0x00000800)  /* R/WC */
0363 #define INT_STS_TDFO_           (0x00000400)  /* R/WC */
0364 #define INT_STS_TDFA_           (0x00000200)  /* R/WC */
0365 #define INT_STS_TSFF_           (0x00000100)  /* R/WC */
0366 #define INT_STS_TSFL_           (0x00000080)  /* R/WC */
0367 //#define   INT_STS_RXDF_       (0x00000040)  /* R/WC */
0368 #define INT_STS_RDFO_           (0x00000040)  /* R/WC */
0369 #define INT_STS_RDFL_           (0x00000020)  /* R/WC */
0370 #define INT_STS_RSFF_           (0x00000010)  /* R/WC */
0371 #define INT_STS_RSFL_           (0x00000008)  /* R/WC */
0372 #define INT_STS_GPIO2_INT_      (0x00000004)  /* R/WC */
0373 #define INT_STS_GPIO1_INT_      (0x00000002)  /* R/WC */
0374 #define INT_STS_GPIO0_INT_      (0x00000001)  /* R/WC */
0375
0376 #define INT_EN          (0x5C)
0377 #define INT_EN_SW_INT_EN_       (0x80000000)  /* R/W */
0378 #define INT_EN_TXSTOP_INT_EN_       (0x02000000)  /* R/W */
0379 #define INT_EN_RXSTOP_INT_EN_       (0x01000000)  /* R/W */
0380 #define INT_EN_RXDFH_INT_EN_        (0x00800000)  /* R/W */
0381 //#define   INT_EN_RXDF_INT_EN_     (0x00400000)  /* R/W */
0382 #define INT_EN_TIOC_INT_EN_     (0x00200000)  /* R/W */
0383 #define INT_EN_RXD_INT_EN_      (0x00100000)  /* R/W */
0384 #define INT_EN_GPT_INT_EN_      (0x00080000)  /* R/W */
0385 #define INT_EN_PHY_INT_EN_      (0x00040000)  /* R/W */
0386 #define INT_EN_PME_INT_EN_      (0x00020000)  /* R/W */
0387 #define INT_EN_TXSO_EN_         (0x00010000)  /* R/W */
0388 #define INT_EN_RWT_EN_          (0x00008000)  /* R/W */
0389 #define INT_EN_RXE_EN_          (0x00004000)  /* R/W */
0390 #define INT_EN_TXE_EN_          (0x00002000)  /* R/W */
0391 //#define   INT_EN_ERX_EN_          (0x00001000)  /* R/W */
0392 #define INT_EN_TDFU_EN_         (0x00000800)  /* R/W */
0393 #define INT_EN_TDFO_EN_         (0x00000400)  /* R/W */
0394 #define INT_EN_TDFA_EN_         (0x00000200)  /* R/W */
0395 #define INT_EN_TSFF_EN_         (0x00000100)  /* R/W */
0396 #define INT_EN_TSFL_EN_         (0x00000080)  /* R/W */
0397 //#define   INT_EN_RXDF_EN_         (0x00000040)  /* R/W */
0398 #define INT_EN_RDFO_EN_         (0x00000040)  /* R/W */
0399 #define INT_EN_RDFL_EN_         (0x00000020)  /* R/W */
0400 #define INT_EN_RSFF_EN_         (0x00000010)  /* R/W */
0401 #define INT_EN_RSFL_EN_         (0x00000008)  /* R/W */
0402 #define INT_EN_GPIO2_INT_       (0x00000004)  /* R/W */
0403 #define INT_EN_GPIO1_INT_       (0x00000002)  /* R/W */
0404 #define INT_EN_GPIO0_INT_       (0x00000001)  /* R/W */
0405
0406 #define BYTE_TEST       (0x64)
0407 #define FIFO_INT        (0x68)
0408 #define FIFO_INT_TX_AVAIL_LEVEL_    (0xFF000000)  /* R/W */
0409 #define FIFO_INT_TX_STS_LEVEL_      (0x00FF0000)  /* R/W */
0410 #define FIFO_INT_RX_AVAIL_LEVEL_    (0x0000FF00)  /* R/W */
0411 #define FIFO_INT_RX_STS_LEVEL_      (0x000000FF)  /* R/W */
0412
0413 #define RX_CFG          (0x6C)
0414 #define RX_CFG_RX_END_ALGN_     (0xC0000000)  /* R/W */
0415 #define     RX_CFG_RX_END_ALGN4_        (0x00000000)  /* R/W */
0416 #define     RX_CFG_RX_END_ALGN16_       (0x40000000)  /* R/W */
0417 #define     RX_CFG_RX_END_ALGN32_       (0x80000000)  /* R/W */
0418 #define RX_CFG_RX_DMA_CNT_      (0x0FFF0000)  /* R/W */
0419 #define RX_CFG_RX_DUMP_         (0x00008000)  /* R/W */
0420 #define RX_CFG_RXDOFF_          (0x00001F00)  /* R/W */
0421 //#define   RX_CFG_RXBAD_           (0x00000001)  /* R/W */
0422
0423 #define TX_CFG          (0x70)
0424 //#define   TX_CFG_TX_DMA_LVL_      (0xE0000000)     /* R/W */
0425 //#define   TX_CFG_TX_DMA_CNT_      (0x0FFF0000)     /* R/W Self Clearing */
0426 #define TX_CFG_TXS_DUMP_        (0x00008000)  /* Self Clearing */
0427 #define TX_CFG_TXD_DUMP_        (0x00004000)  /* Self Clearing */
0428 #define TX_CFG_TXSAO_           (0x00000004)  /* R/W */
0429 #define TX_CFG_TX_ON_           (0x00000002)  /* R/W */
0430 #define TX_CFG_STOP_TX_         (0x00000001)  /* Self Clearing */
0431
0432 #define HW_CFG          (0x74)
0433 #define HW_CFG_TTM_         (0x00200000)  /* R/W */
0434 #define HW_CFG_SF_          (0x00100000)  /* R/W */
0435 #define HW_CFG_TX_FIF_SZ_       (0x000F0000)  /* R/W */
0436 #define HW_CFG_TR_          (0x00003000)  /* R/W */
0437 #define HW_CFG_PHY_CLK_SEL_     (0x00000060)  /* R/W */
0438 #define      HW_CFG_PHY_CLK_SEL_INT_PHY_    (0x00000000) /* R/W */
0439 #define      HW_CFG_PHY_CLK_SEL_EXT_PHY_    (0x00000020) /* R/W */
0440 #define      HW_CFG_PHY_CLK_SEL_CLK_DIS_    (0x00000040) /* R/W */
0441 #define HW_CFG_SMI_SEL_         (0x00000010)  /* R/W */
0442 #define HW_CFG_EXT_PHY_DET_     (0x00000008)  /* RO */
0443 #define HW_CFG_EXT_PHY_EN_      (0x00000004)  /* R/W */
0444 #define HW_CFG_32_16_BIT_MODE_      (0x00000004)  /* RO */
0445 #define HW_CFG_SRST_TO_         (0x00000002)  /* RO */
0446 #define HW_CFG_SRST_            (0x00000001)  /* Self Clearing */
0447
0448 #define RX_DP_CTRL      (0x78)
0449 #define RX_DP_CTRL_RX_FFWD_     (0x80000000)  /* R/W */
0450 #define RX_DP_CTRL_FFWD_BUSY_       (0x80000000)  /* RO */
0451
0452 #define RX_FIFO_INF     (0x7C)
0453 #define  RX_FIFO_INF_RXSUSED_       (0x00FF0000)  /* RO */
0454 #define  RX_FIFO_INF_RXDUSED_       (0x0000FFFF)  /* RO */
0455
0456 #define TX_FIFO_INF     (0x80)
0457 #define TX_FIFO_INF_TSUSED_     (0x00FF0000)  /* RO */
0458 #define TX_FIFO_INF_TDFREE_     (0x0000FFFF)  /* RO */
0459
0460 #define PMT_CTRL        (0x84)
0461 #define PMT_CTRL_PM_MODE_       (0x00003000)  /* Self Clearing */
0462 #define PMT_CTRL_PHY_RST_       (0x00000400)  /* Self Clearing */
0463 #define PMT_CTRL_WOL_EN_        (0x00000200)  /* R/W */
0464 #define PMT_CTRL_ED_EN_         (0x00000100)  /* R/W */
0465 #define PMT_CTRL_PME_TYPE_      (0x00000040)  /* R/W Not Affected by SW Reset */
0466 #define PMT_CTRL_WUPS_          (0x00000030)  /* R/WC */
0467 #define     PMT_CTRL_WUPS_NOWAKE_       (0x00000000)  /* R/WC */
0468 #define     PMT_CTRL_WUPS_ED_       (0x00000010)  /* R/WC */
0469 #define     PMT_CTRL_WUPS_WOL_      (0x00000020)  /* R/WC */
0470 #define     PMT_CTRL_WUPS_MULTI_        (0x00000030)  /* R/WC */
0471 #define PMT_CTRL_PME_IND_       (0x00000008)  /* R/W */
0472 #define PMT_CTRL_PME_POL_       (0x00000004)  /* R/W */
0473 #define PMT_CTRL_PME_EN_        (0x00000002)  /* R/W Not Affected by SW Reset */
0474 #define PMT_CTRL_READY_         (0x00000001)  /* RO */
0475
0476 #define GPIO_CFG        (0x88)
0477 #define GPIO_CFG_LED3_EN_       (0x40000000)  /* R/W */
0478 #define GPIO_CFG_LED2_EN_       (0x20000000)  /* R/W */
0479 #define GPIO_CFG_LED1_EN_       (0x10000000)  /* R/W */
0480 #define GPIO_CFG_GPIO2_INT_POL_     (0x04000000)  /* R/W */
0481 #define GPIO_CFG_GPIO1_INT_POL_     (0x02000000)  /* R/W */
0482 #define GPIO_CFG_GPIO0_INT_POL_     (0x01000000)  /* R/W */
0483 #define GPIO_CFG_EEPR_EN_       (0x00700000)  /* R/W */
0484 #define GPIO_CFG_GPIOBUF2_      (0x00040000)  /* R/W */
0485 #define GPIO_CFG_GPIOBUF1_      (0x00020000)  /* R/W */
0486 #define GPIO_CFG_GPIOBUF0_      (0x00010000)  /* R/W */
0487 #define GPIO_CFG_GPIODIR2_      (0x00000400)  /* R/W */
0488 #define GPIO_CFG_GPIODIR1_      (0x00000200)  /* R/W */
0489 #define GPIO_CFG_GPIODIR0_      (0x00000100)  /* R/W */
0490 #define GPIO_CFG_GPIOD4_        (0x00000010)  /* R/W */
0491 #define GPIO_CFG_GPIOD3_        (0x00000008)  /* R/W */
0492 #define GPIO_CFG_GPIOD2_        (0x00000004)  /* R/W */
0493 #define GPIO_CFG_GPIOD1_        (0x00000002)  /* R/W */
0494 #define GPIO_CFG_GPIOD0_        (0x00000001)  /* R/W */
0495
0496 #define GPT_CFG         (0x8C)
0497 #define GPT_CFG_TIMER_EN_       (0x20000000)  /* R/W */
0498 #define GPT_CFG_GPT_LOAD_       (0x0000FFFF)  /* R/W */
0499
0500 #define GPT_CNT         (0x90)
0501 #define GPT_CNT_GPT_CNT_        (0x0000FFFF)  /* RO */
0502
0503 #define ENDIAN          (0x98)
0504 #define FREE_RUN        (0x9C)
0505 #define RX_DROP         (0xA0)
0506 #define MAC_CSR_CMD     (0xA4)
0507 #define  MAC_CSR_CMD_CSR_BUSY_      (0x80000000)  /* Self Clearing */
0508 #define  MAC_CSR_CMD_R_NOT_W_       (0x40000000)  /* R/W */
0509 #define  MAC_CSR_CMD_CSR_ADDR_      (0x000000FF)  /* R/W */
0510
0511 #define MAC_CSR_DATA        (0xA8)
0512 #define AFC_CFG         (0xAC)
0513 #define     AFC_CFG_AFC_HI_         (0x00FF0000)  /* R/W */
0514 #define     AFC_CFG_AFC_LO_         (0x0000FF00)  /* R/W */
0515 #define     AFC_CFG_BACK_DUR_       (0x000000F0)  /* R/W */
0516 #define     AFC_CFG_FCMULT_         (0x00000008)  /* R/W */
0517 #define     AFC_CFG_FCBRD_          (0x00000004)  /* R/W */
0518 #define     AFC_CFG_FCADD_          (0x00000002)  /* R/W */
0519 #define     AFC_CFG_FCANY_          (0x00000001)  /* R/W */
0520
0521 #define E2P_CMD         (0xB0)
0522 #define E2P_CMD_EPC_BUSY_       (0x80000000)  /* Self Clearing */
0523 #define E2P_CMD_EPC_CMD_            (0x70000000)  /* R/W */
0524 #define     E2P_CMD_EPC_CMD_READ_       (0x00000000)  /* R/W */
0525 #define     E2P_CMD_EPC_CMD_EWDS_       (0x10000000)  /* R/W */
0526 #define     E2P_CMD_EPC_CMD_EWEN_       (0x20000000)  /* R/W */
0527 #define     E2P_CMD_EPC_CMD_WRITE_      (0x30000000)  /* R/W */
0528 #define     E2P_CMD_EPC_CMD_WRAL_       (0x40000000)  /* R/W */
0529 #define     E2P_CMD_EPC_CMD_ERASE_      (0x50000000)  /* R/W */
0530 #define     E2P_CMD_EPC_CMD_ERAL_       (0x60000000)  /* R/W */
0531 #define     E2P_CMD_EPC_CMD_RELOAD_     (0x70000000)  /* R/W */
0532 #define E2P_CMD_EPC_TIMEOUT_        (0x00000200)  /* RO */
0533 #define E2P_CMD_MAC_ADDR_LOADED_    (0x00000100)  /* RO */
0534 #define E2P_CMD_EPC_ADDR_       (0x000000FF)  /* R/W */
0535
0536 #define E2P_DATA        (0xB4)
0537 #define E2P_DATA_EEPROM_DATA_       (0x000000FF)  /* R/W */
0538 /* end of LAN register offsets and bit definitions */
0539
0540 /*
0541  ****************************************************************************
0542  ****************************************************************************
0543  * MAC Control and Status Register (Indirect Address)
0544  * Offset (through the MAC_CSR CMD and DATA port)
0545  ****************************************************************************
0546  ****************************************************************************
0547  *
0548  */
0549 #define MAC_CR          (0x01)  /* R/W */
0550
0551 /* MAC_CR - MAC Control Register */
0552 #define MAC_CR_RXALL_           (0x80000000)
0553 // TODO: delete this bit? It is not described in the data sheet.
0554 #define MAC_CR_HBDIS_           (0x10000000)
0555 #define MAC_CR_RCVOWN_          (0x00800000)
0556 #define MAC_CR_LOOPBK_          (0x00200000)
0557 #define MAC_CR_FDPX_            (0x00100000)
0558 #define MAC_CR_MCPAS_           (0x00080000)
0559 #define MAC_CR_PRMS_            (0x00040000)
0560 #define MAC_CR_INVFILT_         (0x00020000)
0561 #define MAC_CR_PASSBAD_         (0x00010000)
0562 #define MAC_CR_HFILT_           (0x00008000)
0563 #define MAC_CR_HPFILT_          (0x00002000)
0564 #define MAC_CR_LCOLL_           (0x00001000)
0565 #define MAC_CR_BCAST_           (0x00000800)
0566 #define MAC_CR_DISRTY_          (0x00000400)
0567 #define MAC_CR_PADSTR_          (0x00000100)
0568 #define MAC_CR_BOLMT_MASK_      (0x000000C0)
0569 #define MAC_CR_DFCHK_           (0x00000020)
0570 #define MAC_CR_TXEN_            (0x00000008)
0571 #define MAC_CR_RXEN_            (0x00000004)
0572
0573 #define ADDRH           (0x02)    /* R/W mask 0x0000FFFFUL */
0574 #define ADDRL           (0x03)    /* R/W mask 0xFFFFFFFFUL */
0575 #define HASHH           (0x04)    /* R/W */
0576 #define HASHL           (0x05)    /* R/W */
0577
0578 #define MII_ACC         (0x06)    /* R/W */
0579 #define MII_ACC_PHY_ADDR_       (0x0000F800)
0580 #define MII_ACC_MIIRINDA_       (0x000007C0)
0581 #define MII_ACC_MII_WRITE_      (0x00000002)
0582 #define MII_ACC_MII_BUSY_       (0x00000001)
0583
0584 #define MII_DATA        (0x07)    /* R/W mask 0x0000FFFFUL */
0585
0586 #define FLOW            (0x08)    /* R/W */
0587 #define FLOW_FCPT_          (0xFFFF0000)
0588 #define FLOW_FCPASS_            (0x00000004)
0589 #define FLOW_FCEN_          (0x00000002)
0590 #define FLOW_FCBSY_         (0x00000001)
0591
0592 #define VLAN1           (0x09)    /* R/W mask 0x0000FFFFUL */
0593 #define VLAN1_VTI1_         (0x0000ffff)
0594
0595 #define VLAN2           (0x0A)    /* R/W mask 0x0000FFFFUL */
0596 #define VLAN2_VTI2_         (0x0000ffff)
0597
0598 #define WUFF            (0x0B)    /* WO */
0599
0600 #define WUCSR           (0x0C)    /* R/W */
0601 #define WUCSR_GUE_          (0x00000200)
0602 #define WUCSR_WUFR_         (0x00000040)
0603 #define WUCSR_MPR_          (0x00000020)
0604 #define WUCSR_WAKE_EN_          (0x00000004)
0605 #define WUCSR_MPEN_         (0x00000002)
0606
0607 /*
0608  ****************************************************************************
0609  * Chip Specific MII Defines
0610  ****************************************************************************
0611  *
0612  * Phy register offsets and bit definitions
0613  *
0614  */
0615
0616 #define PHY_MODE_CTRL_STS   ((u32)17)   /* Mode Control/Status Register */
0617 //#define MODE_CTRL_STS_FASTRIP_      ((u16)0x4000)
0618 #define MODE_CTRL_STS_EDPWRDOWN_     ((u16)0x2000)
0619 //#define MODE_CTRL_STS_LOWSQEN_       ((u16)0x0800)
0620 //#define MODE_CTRL_STS_MDPREBP_       ((u16)0x0400)
0621 //#define MODE_CTRL_STS_FARLOOPBACK_  ((u16)0x0200)
0622 //#define MODE_CTRL_STS_FASTEST_       ((u16)0x0100)
0623 //#define MODE_CTRL_STS_REFCLKEN_      ((u16)0x0010)
0624 //#define MODE_CTRL_STS_PHYADBP_       ((u16)0x0008)
0625 //#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
0626 #define MODE_CTRL_STS_ENERGYON_     ((u16)0x0002)
0627
0628 #define PHY_INT_SRC         ((u32)29)
0629 #define PHY_INT_SRC_ENERGY_ON_          ((u16)0x0080)
0630 #define PHY_INT_SRC_ANEG_COMP_          ((u16)0x0040)
0631 #define PHY_INT_SRC_REMOTE_FAULT_       ((u16)0x0020)
0632 #define PHY_INT_SRC_LINK_DOWN_          ((u16)0x0010)
0633 #define PHY_INT_SRC_ANEG_LP_ACK_        ((u16)0x0008)
0634 #define PHY_INT_SRC_PAR_DET_FAULT_      ((u16)0x0004)
0635 #define PHY_INT_SRC_ANEG_PGRX_          ((u16)0x0002)
0636
0637 #define PHY_INT_MASK            ((u32)30)
0638 #define PHY_INT_MASK_ENERGY_ON_         ((u16)0x0080)
0639 #define PHY_INT_MASK_ANEG_COMP_         ((u16)0x0040)
0640 #define PHY_INT_MASK_REMOTE_FAULT_      ((u16)0x0020)
0641 #define PHY_INT_MASK_LINK_DOWN_         ((u16)0x0010)
0642 #define PHY_INT_MASK_ANEG_LP_ACK_       ((u16)0x0008)
0643 #define PHY_INT_MASK_PAR_DET_FAULT_     ((u16)0x0004)
0644 #define PHY_INT_MASK_ANEG_PGRX_         ((u16)0x0002)
0645
0646 #define PHY_SPECIAL         ((u32)31)
0647 #define PHY_SPECIAL_ANEG_DONE_          ((u16)0x1000)
0648 #define PHY_SPECIAL_RES_            ((u16)0x0040)
0649 #define PHY_SPECIAL_RES_MASK_           ((u16)0x0FE1)
0650 #define PHY_SPECIAL_SPD_            ((u16)0x001C)
0651 #define PHY_SPECIAL_SPD_10HALF_         ((u16)0x0004)
0652 #define PHY_SPECIAL_SPD_10FULL_         ((u16)0x0014)
0653 #define PHY_SPECIAL_SPD_100HALF_        ((u16)0x0008)
0654 #define PHY_SPECIAL_SPD_100FULL_        ((u16)0x0018)
0655
0656 #define LAN911X_INTERNAL_PHY_ID     (0x0007C000)
0657
0658 /* Chip ID values */
0659 #define CHIP_9115   0x0115
0660 #define CHIP_9116   0x0116
0661 #define CHIP_9117   0x0117
0662 #define CHIP_9118   0x0118
0663 #define CHIP_9211   0x9211
0664 #define CHIP_9215   0x115A
0665 #define CHIP_9217   0x117A
0666 #define CHIP_9218   0x118A
0667
0668 struct chip_id {
0669     u16 id;
0670     char *name;
0671 };
0672
0673 static const struct chip_id chip_ids[] =  {
0674     { CHIP_9115, "LAN9115" },
0675     { CHIP_9116, "LAN9116" },
0676     { CHIP_9117, "LAN9117" },
0677     { CHIP_9118, "LAN9118" },
0678     { CHIP_9211, "LAN9211" },
0679     { CHIP_9215, "LAN9215" },
0680     { CHIP_9217, "LAN9217" },
0681     { CHIP_9218, "LAN9218" },
0682     { 0, NULL },
0683 };
0684
0685 #define IS_REV_A(x) ((x & 0xFFFF)==0)
0686
0687 /*
0688  * Macros to abstract register access according to the data bus
0689  * capabilities.  Please use those and not the in/out primitives.
0690  */
0691 /* FIFO read/write macros */
0692 #define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
0693 #define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
0694 #define SMC_SET_TX_FIFO(lp, x)  SMC_outl( x, lp, TX_DATA_FIFO )
0695 #define SMC_GET_RX_FIFO(lp) SMC_inl( lp, RX_DATA_FIFO )
0696
0697
0698 /* I/O mapped register read/write macros */
0699 #define SMC_GET_TX_STS_FIFO(lp)     SMC_inl( lp, TX_STATUS_FIFO )
0700 #define SMC_GET_RX_STS_FIFO(lp)     SMC_inl( lp, RX_STATUS_FIFO )
0701 #define SMC_GET_RX_STS_FIFO_PEEK(lp)    SMC_inl( lp, RX_STATUS_FIFO_PEEK )
0702 #define SMC_GET_PN(lp)          (SMC_inl( lp, ID_REV ) >> 16)
0703 #define SMC_GET_REV(lp)         (SMC_inl( lp, ID_REV ) & 0xFFFF)
0704 #define SMC_GET_IRQ_CFG(lp)     SMC_inl( lp, INT_CFG )
0705 #define SMC_SET_IRQ_CFG(lp, x)      SMC_outl( x, lp, INT_CFG )
0706 #define SMC_GET_INT(lp)         SMC_inl( lp, INT_STS )
0707 #define SMC_ACK_INT(lp, x)          SMC_outl( x, lp, INT_STS )
0708 #define SMC_GET_INT_EN(lp)      SMC_inl( lp, INT_EN )
0709 #define SMC_SET_INT_EN(lp, x)       SMC_outl( x, lp, INT_EN )
0710 #define SMC_GET_BYTE_TEST(lp)       SMC_inl( lp, BYTE_TEST )
0711 #define SMC_SET_BYTE_TEST(lp, x)        SMC_outl( x, lp, BYTE_TEST )
0712 #define SMC_GET_FIFO_INT(lp)        SMC_inl( lp, FIFO_INT )
0713 #define SMC_SET_FIFO_INT(lp, x)     SMC_outl( x, lp, FIFO_INT )
0714 #define SMC_SET_FIFO_TDA(lp, x)                 \
0715     do {                            \
0716         unsigned long __flags;              \
0717         int __mask;                 \
0718         local_irq_save(__flags);            \
0719         __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24);  \
0720         SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 ); \
0721         local_irq_restore(__flags);         \
0722     } while (0)
0723 #define SMC_SET_FIFO_TSL(lp, x)                 \
0724     do {                            \
0725         unsigned long __flags;              \
0726         int __mask;                 \
0727         local_irq_save(__flags);            \
0728         __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16);  \
0729         SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16));   \
0730         local_irq_restore(__flags);         \
0731     } while (0)
0732 #define SMC_SET_FIFO_RSA(lp, x)                 \
0733     do {                            \
0734         unsigned long __flags;              \
0735         int __mask;                 \
0736         local_irq_save(__flags);            \
0737         __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8);   \
0738         SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8));    \
0739         local_irq_restore(__flags);         \
0740     } while (0)
0741 #define SMC_SET_FIFO_RSL(lp, x)                 \
0742     do {                            \
0743         unsigned long __flags;              \
0744         int __mask;                 \
0745         local_irq_save(__flags);            \
0746         __mask = SMC_GET_FIFO_INT((lp)) & ~0xFF;    \
0747         SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF));  \
0748         local_irq_restore(__flags);         \
0749     } while (0)
0750 #define SMC_GET_RX_CFG(lp)      SMC_inl( lp, RX_CFG )
0751 #define SMC_SET_RX_CFG(lp, x)       SMC_outl( x, lp, RX_CFG )
0752 #define SMC_GET_TX_CFG(lp)      SMC_inl( lp, TX_CFG )
0753 #define SMC_SET_TX_CFG(lp, x)       SMC_outl( x, lp, TX_CFG )
0754 #define SMC_GET_HW_CFG(lp)      SMC_inl( lp, HW_CFG )
0755 #define SMC_SET_HW_CFG(lp, x)       SMC_outl( x, lp, HW_CFG )
0756 #define SMC_GET_RX_DP_CTRL(lp)      SMC_inl( lp, RX_DP_CTRL )
0757 #define SMC_SET_RX_DP_CTRL(lp, x)       SMC_outl( x, lp, RX_DP_CTRL )
0758 #define SMC_GET_PMT_CTRL(lp)        SMC_inl( lp, PMT_CTRL )
0759 #define SMC_SET_PMT_CTRL(lp, x)     SMC_outl( x, lp, PMT_CTRL )
0760 #define SMC_GET_GPIO_CFG(lp)        SMC_inl( lp, GPIO_CFG )
0761 #define SMC_SET_GPIO_CFG(lp, x)     SMC_outl( x, lp, GPIO_CFG )
0762 #define SMC_GET_RX_FIFO_INF(lp)     SMC_inl( lp, RX_FIFO_INF )
0763 #define SMC_SET_RX_FIFO_INF(lp, x)      SMC_outl( x, lp, RX_FIFO_INF )
0764 #define SMC_GET_TX_FIFO_INF(lp)     SMC_inl( lp, TX_FIFO_INF )
0765 #define SMC_SET_TX_FIFO_INF(lp, x)      SMC_outl( x, lp, TX_FIFO_INF )
0766 #define SMC_GET_GPT_CFG(lp)     SMC_inl( lp, GPT_CFG )
0767 #define SMC_SET_GPT_CFG(lp, x)      SMC_outl( x, lp, GPT_CFG )
0768 #define SMC_GET_RX_DROP(lp)     SMC_inl( lp, RX_DROP )
0769 #define SMC_SET_RX_DROP(lp, x)      SMC_outl( x, lp, RX_DROP )
0770 #define SMC_GET_MAC_CMD(lp)     SMC_inl( lp, MAC_CSR_CMD )
0771 #define SMC_SET_MAC_CMD(lp, x)      SMC_outl( x, lp, MAC_CSR_CMD )
0772 #define SMC_GET_MAC_DATA(lp)        SMC_inl( lp, MAC_CSR_DATA )
0773 #define SMC_SET_MAC_DATA(lp, x)     SMC_outl( x, lp, MAC_CSR_DATA )
0774 #define SMC_GET_AFC_CFG(lp)     SMC_inl( lp, AFC_CFG )
0775 #define SMC_SET_AFC_CFG(lp, x)      SMC_outl( x, lp, AFC_CFG )
0776 #define SMC_GET_E2P_CMD(lp)     SMC_inl( lp, E2P_CMD )
0777 #define SMC_SET_E2P_CMD(lp, x)      SMC_outl( x, lp, E2P_CMD )
0778 #define SMC_GET_E2P_DATA(lp)        SMC_inl( lp, E2P_DATA )
0779 #define SMC_SET_E2P_DATA(lp, x)     SMC_outl( x, lp, E2P_DATA )
0780
0781 /* MAC register read/write macros */
0782 #define SMC_GET_MAC_CSR(lp,a,v)                     \
0783     do {                                \
0784         while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
0785         SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ |        \
0786             MAC_CSR_CMD_R_NOT_W_ | (a) );           \
0787         while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
0788         v = SMC_GET_MAC_DATA((lp));                 \
0789     } while (0)
0790 #define SMC_SET_MAC_CSR(lp,a,v)                     \
0791     do {                                \
0792         while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
0793         SMC_SET_MAC_DATA((lp), v);              \
0794         SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) );    \
0795         while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
0796     } while (0)
0797 #define SMC_GET_MAC_CR(lp, x)   SMC_GET_MAC_CSR( (lp), MAC_CR, x )
0798 #define SMC_SET_MAC_CR(lp, x)   SMC_SET_MAC_CSR( (lp), MAC_CR, x )
0799 #define SMC_GET_ADDRH(lp, x)    SMC_GET_MAC_CSR( (lp), ADDRH, x )
0800 #define SMC_SET_ADDRH(lp, x)    SMC_SET_MAC_CSR( (lp), ADDRH, x )
0801 #define SMC_GET_ADDRL(lp, x)    SMC_GET_MAC_CSR( (lp), ADDRL, x )
0802 #define SMC_SET_ADDRL(lp, x)    SMC_SET_MAC_CSR( (lp), ADDRL, x )
0803 #define SMC_GET_HASHH(lp, x)    SMC_GET_MAC_CSR( (lp), HASHH, x )
0804 #define SMC_SET_HASHH(lp, x)    SMC_SET_MAC_CSR( (lp), HASHH, x )
0805 #define SMC_GET_HASHL(lp, x)    SMC_GET_MAC_CSR( (lp), HASHL, x )
0806 #define SMC_SET_HASHL(lp, x)    SMC_SET_MAC_CSR( (lp), HASHL, x )
0807 #define SMC_GET_MII_ACC(lp, x)  SMC_GET_MAC_CSR( (lp), MII_ACC, x )
0808 #define SMC_SET_MII_ACC(lp, x)  SMC_SET_MAC_CSR( (lp), MII_ACC, x )
0809 #define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
0810 #define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
0811 #define SMC_GET_FLOW(lp, x)     SMC_GET_MAC_CSR( (lp), FLOW, x )
0812 #define SMC_SET_FLOW(lp, x)     SMC_SET_MAC_CSR( (lp), FLOW, x )
0813 #define SMC_GET_VLAN1(lp, x)    SMC_GET_MAC_CSR( (lp), VLAN1, x )
0814 #define SMC_SET_VLAN1(lp, x)    SMC_SET_MAC_CSR( (lp), VLAN1, x )
0815 #define SMC_GET_VLAN2(lp, x)    SMC_GET_MAC_CSR( (lp), VLAN2, x )
0816 #define SMC_SET_VLAN2(lp, x)    SMC_SET_MAC_CSR( (lp), VLAN2, x )
0817 #define SMC_SET_WUFF(lp, x)     SMC_SET_MAC_CSR( (lp), WUFF, x )
0818 #define SMC_GET_WUCSR(lp, x)    SMC_GET_MAC_CSR( (lp), WUCSR, x )
0819 #define SMC_SET_WUCSR(lp, x)    SMC_SET_MAC_CSR( (lp), WUCSR, x )
0820
0821 /* PHY register read/write macros */
0822 #define SMC_GET_MII(lp,a,phy,v)                 \
0823     do {                            \
0824         u32 __v;                    \
0825         do {                        \
0826             SMC_GET_MII_ACC((lp), __v);         \
0827         } while ( __v & MII_ACC_MII_BUSY_ );        \
0828         SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
0829             MII_ACC_MII_BUSY_);         \
0830         do {                        \
0831             SMC_GET_MII_ACC( (lp), __v);            \
0832         } while ( __v & MII_ACC_MII_BUSY_ );        \
0833         SMC_GET_MII_DATA((lp), v);              \
0834     } while (0)
0835 #define SMC_SET_MII(lp,a,phy,v)                 \
0836     do {                            \
0837         u32 __v;                    \
0838         do {                        \
0839             SMC_GET_MII_ACC((lp), __v);         \
0840         } while ( __v & MII_ACC_MII_BUSY_ );        \
0841         SMC_SET_MII_DATA((lp), v);              \
0842         SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
0843             MII_ACC_MII_BUSY_    |      \
0844             MII_ACC_MII_WRITE_  );          \
0845         do {                        \
0846             SMC_GET_MII_ACC((lp), __v);         \
0847         } while ( __v & MII_ACC_MII_BUSY_ );        \
0848     } while (0)
0849 #define SMC_GET_PHY_BMCR(lp,phy,x)      SMC_GET_MII( (lp), MII_BMCR, phy, x )
0850 #define SMC_SET_PHY_BMCR(lp,phy,x)      SMC_SET_MII( (lp), MII_BMCR, phy, x )
0851 #define SMC_GET_PHY_BMSR(lp,phy,x)      SMC_GET_MII( (lp), MII_BMSR, phy, x )
0852 #define SMC_GET_PHY_ID1(lp,phy,x)       SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
0853 #define SMC_GET_PHY_ID2(lp,phy,x)       SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
0854 #define SMC_GET_PHY_MII_ADV(lp,phy,x)   SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
0855 #define SMC_SET_PHY_MII_ADV(lp,phy,x)   SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
0856 #define SMC_GET_PHY_MII_LPA(lp,phy,x)   SMC_GET_MII( (lp), MII_LPA, phy, x )
0857 #define SMC_SET_PHY_MII_LPA(lp,phy,x)   SMC_SET_MII( (lp), MII_LPA, phy, x )
0858 #define SMC_GET_PHY_CTRL_STS(lp,phy,x)  SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
0859 #define SMC_SET_PHY_CTRL_STS(lp,phy,x)  SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
0860 #define SMC_GET_PHY_INT_SRC(lp,phy,x)   SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
0861 #define SMC_SET_PHY_INT_SRC(lp,phy,x)   SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
0862 #define SMC_GET_PHY_INT_MASK(lp,phy,x)  SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
0863 #define SMC_SET_PHY_INT_MASK(lp,phy,x)  SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
0864 #define SMC_GET_PHY_SPECIAL(lp,phy,x)   SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
0865
0866
0867
0868 /* Misc read/write macros */
0869
0870 #ifndef SMC_GET_MAC_ADDR
0871 #define SMC_GET_MAC_ADDR(lp, addr)              \
0872     do {                            \
0873         unsigned int __v;               \
0874                                 \
0875         SMC_GET_MAC_CSR((lp), ADDRL, __v);          \
0876         addr[0] = __v; addr[1] = __v >> 8;      \
0877         addr[2] = __v >> 16; addr[3] = __v >> 24;   \
0878         SMC_GET_MAC_CSR((lp), ADDRH, __v);          \
0879         addr[4] = __v; addr[5] = __v >> 8;      \
0880     } while (0)
0881 #endif
0882
0883 #define SMC_SET_MAC_ADDR(lp, addr)              \
0884     do {                            \
0885          SMC_SET_MAC_CSR((lp), ADDRL,               \
0886                  addr[0] |          \
0887                 (addr[1] << 8) |        \
0888                 (addr[2] << 16) |       \
0889                 (addr[3] << 24));       \
0890          SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
0891     } while (0)
0892
0893
0894 #define SMC_WRITE_EEPROM_CMD(lp, cmd, addr)             \
0895     do {                                \
0896         while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
0897         SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a );       \
0898         while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
0899     } while (0)
0900
0901 #endif   /* _SMC911X_H_ */