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0001 /*
0002    sis190.c: Silicon Integrated Systems SiS190 ethernet driver
0003 
0004    Copyright (c) 2003 K.M. Liu <kmliu@sis.com>
0005    Copyright (c) 2003, 2004 Jeff Garzik <jgarzik@pobox.com>
0006    Copyright (c) 2003, 2004, 2005 Francois Romieu <romieu@fr.zoreil.com>
0007 
0008    Based on r8169.c, tg3.c, 8139cp.c, skge.c, epic100.c and SiS 190/191
0009    genuine driver.
0010 
0011    This software may be used and distributed according to the terms of
0012    the GNU General Public License (GPL), incorporated herein by reference.
0013    Drivers based on or derived from this code fall under the GPL and must
0014    retain the authorship, copyright and license notice.  This file is not
0015    a complete program and may only be used when the entire operating
0016    system is licensed under the GPL.
0017 
0018    See the file COPYING in this distribution for more information.
0019 
0020 */
0021 
0022 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0023 
0024 #include <linux/interrupt.h>
0025 #include <linux/module.h>
0026 #include <linux/moduleparam.h>
0027 #include <linux/netdevice.h>
0028 #include <linux/rtnetlink.h>
0029 #include <linux/etherdevice.h>
0030 #include <linux/ethtool.h>
0031 #include <linux/pci.h>
0032 #include <linux/mii.h>
0033 #include <linux/delay.h>
0034 #include <linux/crc32.h>
0035 #include <linux/dma-mapping.h>
0036 #include <linux/slab.h>
0037 #include <asm/irq.h>
0038 
0039 #define PHY_MAX_ADDR        32
0040 #define PHY_ID_ANY      0x1f
0041 #define MII_REG_ANY     0x1f
0042 
0043 #define DRV_VERSION     "1.4"
0044 #define DRV_NAME        "sis190"
0045 #define SIS190_DRIVER_NAME  DRV_NAME " Gigabit Ethernet driver " DRV_VERSION
0046 
0047 #define sis190_rx_skb           netif_rx
0048 #define sis190_rx_quota(count, quota)   count
0049 
0050 #define NUM_TX_DESC     64  /* [8..1024] */
0051 #define NUM_RX_DESC     64  /* [8..8192] */
0052 #define TX_RING_BYTES       (NUM_TX_DESC * sizeof(struct TxDesc))
0053 #define RX_RING_BYTES       (NUM_RX_DESC * sizeof(struct RxDesc))
0054 #define RX_BUF_SIZE     1536
0055 #define RX_BUF_MASK     0xfff8
0056 
0057 #define SIS190_REGS_SIZE    0x80
0058 #define SIS190_TX_TIMEOUT   (6*HZ)
0059 #define SIS190_PHY_TIMEOUT  (10*HZ)
0060 #define SIS190_MSG_DEFAULT  (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
0061                  NETIF_MSG_LINK | NETIF_MSG_IFUP | \
0062                  NETIF_MSG_IFDOWN)
0063 
0064 /* Enhanced PHY access register bit definitions */
0065 #define EhnMIIread      0x0000
0066 #define EhnMIIwrite     0x0020
0067 #define EhnMIIdataShift     16
0068 #define EhnMIIpmdShift      6   /* 7016 only */
0069 #define EhnMIIregShift      11
0070 #define EhnMIIreq       0x0010
0071 #define EhnMIInotDone       0x0010
0072 
0073 /* Write/read MMIO register */
0074 #define SIS_W8(reg, val)    writeb ((val), ioaddr + (reg))
0075 #define SIS_W16(reg, val)   writew ((val), ioaddr + (reg))
0076 #define SIS_W32(reg, val)   writel ((val), ioaddr + (reg))
0077 #define SIS_R8(reg)     readb (ioaddr + (reg))
0078 #define SIS_R16(reg)        readw (ioaddr + (reg))
0079 #define SIS_R32(reg)        readl (ioaddr + (reg))
0080 
0081 #define SIS_PCI_COMMIT()    SIS_R32(IntrControl)
0082 
0083 enum sis190_registers {
0084     TxControl       = 0x00,
0085     TxDescStartAddr     = 0x04,
0086     rsv0            = 0x08, // reserved
0087     TxSts           = 0x0c, // unused (Control/Status)
0088     RxControl       = 0x10,
0089     RxDescStartAddr     = 0x14,
0090     rsv1            = 0x18, // reserved
0091     RxSts           = 0x1c, // unused
0092     IntrStatus      = 0x20,
0093     IntrMask        = 0x24,
0094     IntrControl     = 0x28,
0095     IntrTimer       = 0x2c, // unused (Interrupt Timer)
0096     PMControl       = 0x30, // unused (Power Mgmt Control/Status)
0097     rsv2            = 0x34, // reserved
0098     ROMControl      = 0x38,
0099     ROMInterface        = 0x3c,
0100     StationControl      = 0x40,
0101     GMIIControl     = 0x44,
0102     GIoCR           = 0x48, // unused (GMAC IO Compensation)
0103     GIoCtrl         = 0x4c, // unused (GMAC IO Control)
0104     TxMacControl        = 0x50,
0105     TxLimit         = 0x54, // unused (Tx MAC Timer/TryLimit)
0106     RGDelay         = 0x58, // unused (RGMII Tx Internal Delay)
0107     rsv3            = 0x5c, // reserved
0108     RxMacControl        = 0x60,
0109     RxMacAddr       = 0x62,
0110     RxHashTable     = 0x68,
0111     // Undocumented     = 0x6c,
0112     RxWolCtrl       = 0x70,
0113     RxWolData       = 0x74, // unused (Rx WOL Data Access)
0114     RxMPSControl        = 0x78, // unused (Rx MPS Control)
0115     rsv4            = 0x7c, // reserved
0116 };
0117 
0118 enum sis190_register_content {
0119     /* IntrStatus */
0120     SoftInt         = 0x40000000,   // unused
0121     Timeup          = 0x20000000,   // unused
0122     PauseFrame      = 0x00080000,   // unused
0123     MagicPacket     = 0x00040000,   // unused
0124     WakeupFrame     = 0x00020000,   // unused
0125     LinkChange      = 0x00010000,
0126     RxQEmpty        = 0x00000080,
0127     RxQInt          = 0x00000040,
0128     TxQ1Empty       = 0x00000020,   // unused
0129     TxQ1Int         = 0x00000010,
0130     TxQ0Empty       = 0x00000008,   // unused
0131     TxQ0Int         = 0x00000004,
0132     RxHalt          = 0x00000002,
0133     TxHalt          = 0x00000001,
0134 
0135     /* {Rx/Tx}CmdBits */
0136     CmdReset        = 0x10,
0137     CmdRxEnb        = 0x08,     // unused
0138     CmdTxEnb        = 0x01,
0139     RxBufEmpty      = 0x01,     // unused
0140 
0141     /* Cfg9346Bits */
0142     Cfg9346_Lock        = 0x00,     // unused
0143     Cfg9346_Unlock      = 0xc0,     // unused
0144 
0145     /* RxMacControl */
0146     AcceptErr       = 0x20,     // unused
0147     AcceptRunt      = 0x10,     // unused
0148     AcceptBroadcast     = 0x0800,
0149     AcceptMulticast     = 0x0400,
0150     AcceptMyPhys        = 0x0200,
0151     AcceptAllPhys       = 0x0100,
0152 
0153     /* RxConfigBits */
0154     RxCfgFIFOShift      = 13,
0155     RxCfgDMAShift       = 8,        // 0x1a in RxControl ?
0156 
0157     /* TxConfigBits */
0158     TxInterFrameGapShift    = 24,
0159     TxDMAShift      = 8, /* DMA burst value (0-7) is shift this many bits */
0160 
0161     LinkStatus      = 0x02,     // unused
0162     FullDup         = 0x01,     // unused
0163 
0164     /* TBICSRBit */
0165     TBILinkOK       = 0x02000000,   // unused
0166 };
0167 
0168 struct TxDesc {
0169     __le32 PSize;
0170     __le32 status;
0171     __le32 addr;
0172     __le32 size;
0173 };
0174 
0175 struct RxDesc {
0176     __le32 PSize;
0177     __le32 status;
0178     __le32 addr;
0179     __le32 size;
0180 };
0181 
0182 enum _DescStatusBit {
0183     /* _Desc.status */
0184     OWNbit      = 0x80000000, // RXOWN/TXOWN
0185     INTbit      = 0x40000000, // RXINT/TXINT
0186     CRCbit      = 0x00020000, // CRCOFF/CRCEN
0187     PADbit      = 0x00010000, // PREADD/PADEN
0188     /* _Desc.size */
0189     RingEnd     = 0x80000000,
0190     /* TxDesc.status */
0191     LSEN        = 0x08000000, // TSO ? -- FR
0192     IPCS        = 0x04000000,
0193     TCPCS       = 0x02000000,
0194     UDPCS       = 0x01000000,
0195     BSTEN       = 0x00800000,
0196     EXTEN       = 0x00400000,
0197     DEFEN       = 0x00200000,
0198     BKFEN       = 0x00100000,
0199     CRSEN       = 0x00080000,
0200     COLEN       = 0x00040000,
0201     THOL3       = 0x30000000,
0202     THOL2       = 0x20000000,
0203     THOL1       = 0x10000000,
0204     THOL0       = 0x00000000,
0205 
0206     WND     = 0x00080000,
0207     TABRT       = 0x00040000,
0208     FIFO        = 0x00020000,
0209     LINK        = 0x00010000,
0210     ColCountMask    = 0x0000ffff,
0211     /* RxDesc.status */
0212     IPON        = 0x20000000,
0213     TCPON       = 0x10000000,
0214     UDPON       = 0x08000000,
0215     Wakup       = 0x00400000,
0216     Magic       = 0x00200000,
0217     Pause       = 0x00100000,
0218     DEFbit      = 0x00200000,
0219     BCAST       = 0x000c0000,
0220     MCAST       = 0x00080000,
0221     UCAST       = 0x00040000,
0222     /* RxDesc.PSize */
0223     TAGON       = 0x80000000,
0224     RxDescCountMask = 0x7f000000, // multi-desc pkt when > 1 ? -- FR
0225     ABORT       = 0x00800000,
0226     SHORT       = 0x00400000,
0227     LIMIT       = 0x00200000,
0228     MIIER       = 0x00100000,
0229     OVRUN       = 0x00080000,
0230     NIBON       = 0x00040000,
0231     COLON       = 0x00020000,
0232     CRCOK       = 0x00010000,
0233     RxSizeMask  = 0x0000ffff
0234     /*
0235      * The asic could apparently do vlan, TSO, jumbo (sis191 only) and
0236      * provide two (unused with Linux) Tx queues. No publicly
0237      * available documentation alas.
0238      */
0239 };
0240 
0241 enum sis190_eeprom_access_register_bits {
0242     EECS    = 0x00000001,   // unused
0243     EECLK   = 0x00000002,   // unused
0244     EEDO    = 0x00000008,   // unused
0245     EEDI    = 0x00000004,   // unused
0246     EEREQ   = 0x00000080,
0247     EEROP   = 0x00000200,
0248     EEWOP   = 0x00000100    // unused
0249 };
0250 
0251 /* EEPROM Addresses */
0252 enum sis190_eeprom_address {
0253     EEPROMSignature = 0x00,
0254     EEPROMCLK   = 0x01, // unused
0255     EEPROMInfo  = 0x02,
0256     EEPROMMACAddr   = 0x03
0257 };
0258 
0259 enum sis190_feature {
0260     F_HAS_RGMII = 1,
0261     F_PHY_88E1111   = 2,
0262     F_PHY_BCM5461   = 4
0263 };
0264 
0265 struct sis190_private {
0266     void __iomem *mmio_addr;
0267     struct pci_dev *pci_dev;
0268     struct net_device *dev;
0269     spinlock_t lock;
0270     u32 rx_buf_sz;
0271     u32 cur_rx;
0272     u32 cur_tx;
0273     u32 dirty_rx;
0274     u32 dirty_tx;
0275     dma_addr_t rx_dma;
0276     dma_addr_t tx_dma;
0277     struct RxDesc *RxDescRing;
0278     struct TxDesc *TxDescRing;
0279     struct sk_buff *Rx_skbuff[NUM_RX_DESC];
0280     struct sk_buff *Tx_skbuff[NUM_TX_DESC];
0281     struct work_struct phy_task;
0282     struct timer_list timer;
0283     u32 msg_enable;
0284     struct mii_if_info mii_if;
0285     struct list_head first_phy;
0286     u32 features;
0287     u32 negotiated_lpa;
0288     enum {
0289         LNK_OFF,
0290         LNK_ON,
0291         LNK_AUTONEG,
0292     } link_status;
0293 };
0294 
0295 struct sis190_phy {
0296     struct list_head list;
0297     int phy_id;
0298     u16 id[2];
0299     u16 status;
0300     u8  type;
0301 };
0302 
0303 enum sis190_phy_type {
0304     UNKNOWN = 0x00,
0305     HOME    = 0x01,
0306     LAN = 0x02,
0307     MIX = 0x03
0308 };
0309 
0310 static struct mii_chip_info {
0311         const char *name;
0312         u16 id[2];
0313         unsigned int type;
0314     u32 feature;
0315 } mii_chip_table[] = {
0316     { "Atheros PHY",          { 0x004d, 0xd010 }, LAN, 0 },
0317     { "Atheros PHY AR8012",   { 0x004d, 0xd020 }, LAN, 0 },
0318     { "Broadcom PHY BCM5461", { 0x0020, 0x60c0 }, LAN, F_PHY_BCM5461 },
0319     { "Broadcom PHY AC131",   { 0x0143, 0xbc70 }, LAN, 0 },
0320     { "Agere PHY ET1101B",    { 0x0282, 0xf010 }, LAN, 0 },
0321     { "Marvell PHY 88E1111",  { 0x0141, 0x0cc0 }, LAN, F_PHY_88E1111 },
0322     { "Realtek PHY RTL8201",  { 0x0000, 0x8200 }, LAN, 0 },
0323     { NULL, }
0324 };
0325 
0326 static const struct {
0327     const char *name;
0328 } sis_chip_info[] = {
0329     { "SiS 190 PCI Fast Ethernet adapter" },
0330     { "SiS 191 PCI Gigabit Ethernet adapter" },
0331 };
0332 
0333 static const struct pci_device_id sis190_pci_tbl[] = {
0334     { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0190), 0, 0, 0 },
0335     { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0191), 0, 0, 1 },
0336     { 0, },
0337 };
0338 
0339 MODULE_DEVICE_TABLE(pci, sis190_pci_tbl);
0340 
0341 static int rx_copybreak = 200;
0342 
0343 static struct {
0344     u32 msg_enable;
0345 } debug = { -1 };
0346 
0347 MODULE_DESCRIPTION("SiS sis190/191 Gigabit Ethernet driver");
0348 module_param(rx_copybreak, int, 0);
0349 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
0350 module_param_named(debug, debug.msg_enable, int, 0);
0351 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
0352 MODULE_AUTHOR("K.M. Liu <kmliu@sis.com>, Ueimor <romieu@fr.zoreil.com>");
0353 MODULE_VERSION(DRV_VERSION);
0354 MODULE_LICENSE("GPL");
0355 
0356 static const u32 sis190_intr_mask =
0357     RxQEmpty | RxQInt | TxQ1Int | TxQ0Int | RxHalt | TxHalt | LinkChange;
0358 
0359 /*
0360  * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
0361  * The chips use a 64 element hash table based on the Ethernet CRC.
0362  */
0363 static const int multicast_filter_limit = 32;
0364 
0365 static void __mdio_cmd(void __iomem *ioaddr, u32 ctl)
0366 {
0367     unsigned int i;
0368 
0369     SIS_W32(GMIIControl, ctl);
0370 
0371     msleep(1);
0372 
0373     for (i = 0; i < 100; i++) {
0374         if (!(SIS_R32(GMIIControl) & EhnMIInotDone))
0375             break;
0376         msleep(1);
0377     }
0378 
0379     if (i > 99)
0380         pr_err("PHY command failed !\n");
0381 }
0382 
0383 static void mdio_write(void __iomem *ioaddr, int phy_id, int reg, int val)
0384 {
0385     __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIwrite |
0386         (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift) |
0387         (((u32) val) << EhnMIIdataShift));
0388 }
0389 
0390 static int mdio_read(void __iomem *ioaddr, int phy_id, int reg)
0391 {
0392     __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIread |
0393         (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift));
0394 
0395     return (u16) (SIS_R32(GMIIControl) >> EhnMIIdataShift);
0396 }
0397 
0398 static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val)
0399 {
0400     struct sis190_private *tp = netdev_priv(dev);
0401 
0402     mdio_write(tp->mmio_addr, phy_id, reg, val);
0403 }
0404 
0405 static int __mdio_read(struct net_device *dev, int phy_id, int reg)
0406 {
0407     struct sis190_private *tp = netdev_priv(dev);
0408 
0409     return mdio_read(tp->mmio_addr, phy_id, reg);
0410 }
0411 
0412 static u16 mdio_read_latched(void __iomem *ioaddr, int phy_id, int reg)
0413 {
0414     mdio_read(ioaddr, phy_id, reg);
0415     return mdio_read(ioaddr, phy_id, reg);
0416 }
0417 
0418 static u16 sis190_read_eeprom(void __iomem *ioaddr, u32 reg)
0419 {
0420     u16 data = 0xffff;
0421     unsigned int i;
0422 
0423     if (!(SIS_R32(ROMControl) & 0x0002))
0424         return 0;
0425 
0426     SIS_W32(ROMInterface, EEREQ | EEROP | (reg << 10));
0427 
0428     for (i = 0; i < 200; i++) {
0429         if (!(SIS_R32(ROMInterface) & EEREQ)) {
0430             data = (SIS_R32(ROMInterface) & 0xffff0000) >> 16;
0431             break;
0432         }
0433         msleep(1);
0434     }
0435 
0436     return data;
0437 }
0438 
0439 static void sis190_irq_mask_and_ack(void __iomem *ioaddr)
0440 {
0441     SIS_W32(IntrMask, 0x00);
0442     SIS_W32(IntrStatus, 0xffffffff);
0443     SIS_PCI_COMMIT();
0444 }
0445 
0446 static void sis190_asic_down(void __iomem *ioaddr)
0447 {
0448     /* Stop the chip's Tx and Rx DMA processes. */
0449 
0450     SIS_W32(TxControl, 0x1a00);
0451     SIS_W32(RxControl, 0x1a00);
0452 
0453     sis190_irq_mask_and_ack(ioaddr);
0454 }
0455 
0456 static void sis190_mark_as_last_descriptor(struct RxDesc *desc)
0457 {
0458     desc->size |= cpu_to_le32(RingEnd);
0459 }
0460 
0461 static inline void sis190_give_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
0462 {
0463     u32 eor = le32_to_cpu(desc->size) & RingEnd;
0464 
0465     desc->PSize = 0x0;
0466     desc->size = cpu_to_le32((rx_buf_sz & RX_BUF_MASK) | eor);
0467     wmb();
0468     desc->status = cpu_to_le32(OWNbit | INTbit);
0469 }
0470 
0471 static inline void sis190_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
0472                       u32 rx_buf_sz)
0473 {
0474     desc->addr = cpu_to_le32(mapping);
0475     sis190_give_to_asic(desc, rx_buf_sz);
0476 }
0477 
0478 static inline void sis190_make_unusable_by_asic(struct RxDesc *desc)
0479 {
0480     desc->PSize = 0x0;
0481     desc->addr = cpu_to_le32(0xdeadbeef);
0482     desc->size &= cpu_to_le32(RingEnd);
0483     wmb();
0484     desc->status = 0x0;
0485 }
0486 
0487 static struct sk_buff *sis190_alloc_rx_skb(struct sis190_private *tp,
0488                        struct RxDesc *desc)
0489 {
0490     u32 rx_buf_sz = tp->rx_buf_sz;
0491     struct sk_buff *skb;
0492     dma_addr_t mapping;
0493 
0494     skb = netdev_alloc_skb(tp->dev, rx_buf_sz);
0495     if (unlikely(!skb))
0496         goto skb_alloc_failed;
0497     mapping = dma_map_single(&tp->pci_dev->dev, skb->data, tp->rx_buf_sz,
0498                  DMA_FROM_DEVICE);
0499     if (dma_mapping_error(&tp->pci_dev->dev, mapping))
0500         goto out;
0501     sis190_map_to_asic(desc, mapping, rx_buf_sz);
0502 
0503     return skb;
0504 
0505 out:
0506     dev_kfree_skb_any(skb);
0507 skb_alloc_failed:
0508     sis190_make_unusable_by_asic(desc);
0509     return NULL;
0510 }
0511 
0512 static u32 sis190_rx_fill(struct sis190_private *tp, struct net_device *dev,
0513               u32 start, u32 end)
0514 {
0515     u32 cur;
0516 
0517     for (cur = start; cur < end; cur++) {
0518         unsigned int i = cur % NUM_RX_DESC;
0519 
0520         if (tp->Rx_skbuff[i])
0521             continue;
0522 
0523         tp->Rx_skbuff[i] = sis190_alloc_rx_skb(tp, tp->RxDescRing + i);
0524 
0525         if (!tp->Rx_skbuff[i])
0526             break;
0527     }
0528     return cur - start;
0529 }
0530 
0531 static bool sis190_try_rx_copy(struct sis190_private *tp,
0532                    struct sk_buff **sk_buff, int pkt_size,
0533                    dma_addr_t addr)
0534 {
0535     struct sk_buff *skb;
0536     bool done = false;
0537 
0538     if (pkt_size >= rx_copybreak)
0539         goto out;
0540 
0541     skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
0542     if (!skb)
0543         goto out;
0544 
0545     dma_sync_single_for_cpu(&tp->pci_dev->dev, addr, tp->rx_buf_sz,
0546                 DMA_FROM_DEVICE);
0547     skb_copy_to_linear_data(skb, sk_buff[0]->data, pkt_size);
0548     *sk_buff = skb;
0549     done = true;
0550 out:
0551     return done;
0552 }
0553 
0554 static inline int sis190_rx_pkt_err(u32 status, struct net_device_stats *stats)
0555 {
0556 #define ErrMask (OVRUN | SHORT | LIMIT | MIIER | NIBON | COLON | ABORT)
0557 
0558     if ((status & CRCOK) && !(status & ErrMask))
0559         return 0;
0560 
0561     if (!(status & CRCOK))
0562         stats->rx_crc_errors++;
0563     else if (status & OVRUN)
0564         stats->rx_over_errors++;
0565     else if (status & (SHORT | LIMIT))
0566         stats->rx_length_errors++;
0567     else if (status & (MIIER | NIBON | COLON))
0568         stats->rx_frame_errors++;
0569 
0570     stats->rx_errors++;
0571     return -1;
0572 }
0573 
0574 static int sis190_rx_interrupt(struct net_device *dev,
0575                    struct sis190_private *tp, void __iomem *ioaddr)
0576 {
0577     struct net_device_stats *stats = &dev->stats;
0578     u32 rx_left, cur_rx = tp->cur_rx;
0579     u32 delta, count;
0580 
0581     rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
0582     rx_left = sis190_rx_quota(rx_left, (u32) dev->quota);
0583 
0584     for (; rx_left > 0; rx_left--, cur_rx++) {
0585         unsigned int entry = cur_rx % NUM_RX_DESC;
0586         struct RxDesc *desc = tp->RxDescRing + entry;
0587         u32 status;
0588 
0589         if (le32_to_cpu(desc->status) & OWNbit)
0590             break;
0591 
0592         status = le32_to_cpu(desc->PSize);
0593 
0594         //netif_info(tp, intr, dev, "Rx PSize = %08x\n", status);
0595 
0596         if (sis190_rx_pkt_err(status, stats) < 0)
0597             sis190_give_to_asic(desc, tp->rx_buf_sz);
0598         else {
0599             struct sk_buff *skb = tp->Rx_skbuff[entry];
0600             dma_addr_t addr = le32_to_cpu(desc->addr);
0601             int pkt_size = (status & RxSizeMask) - 4;
0602             struct pci_dev *pdev = tp->pci_dev;
0603 
0604             if (unlikely(pkt_size > tp->rx_buf_sz)) {
0605                 netif_info(tp, intr, dev,
0606                        "(frag) status = %08x\n", status);
0607                 stats->rx_dropped++;
0608                 stats->rx_length_errors++;
0609                 sis190_give_to_asic(desc, tp->rx_buf_sz);
0610                 continue;
0611             }
0612 
0613 
0614             if (sis190_try_rx_copy(tp, &skb, pkt_size, addr)) {
0615                 dma_sync_single_for_device(&pdev->dev, addr,
0616                                tp->rx_buf_sz,
0617                                DMA_FROM_DEVICE);
0618                 sis190_give_to_asic(desc, tp->rx_buf_sz);
0619             } else {
0620                 dma_unmap_single(&pdev->dev, addr,
0621                          tp->rx_buf_sz,
0622                          DMA_FROM_DEVICE);
0623                 tp->Rx_skbuff[entry] = NULL;
0624                 sis190_make_unusable_by_asic(desc);
0625             }
0626 
0627             skb_put(skb, pkt_size);
0628             skb->protocol = eth_type_trans(skb, dev);
0629 
0630             sis190_rx_skb(skb);
0631 
0632             stats->rx_packets++;
0633             stats->rx_bytes += pkt_size;
0634             if ((status & BCAST) == MCAST)
0635                 stats->multicast++;
0636         }
0637     }
0638     count = cur_rx - tp->cur_rx;
0639     tp->cur_rx = cur_rx;
0640 
0641     delta = sis190_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
0642     if (!delta && count)
0643         netif_info(tp, intr, dev, "no Rx buffer allocated\n");
0644     tp->dirty_rx += delta;
0645 
0646     if ((tp->dirty_rx + NUM_RX_DESC) == tp->cur_rx)
0647         netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
0648 
0649     return count;
0650 }
0651 
0652 static void sis190_unmap_tx_skb(struct pci_dev *pdev, struct sk_buff *skb,
0653                 struct TxDesc *desc)
0654 {
0655     unsigned int len;
0656 
0657     len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
0658 
0659     dma_unmap_single(&pdev->dev, le32_to_cpu(desc->addr), len,
0660              DMA_TO_DEVICE);
0661 
0662     memset(desc, 0x00, sizeof(*desc));
0663 }
0664 
0665 static inline int sis190_tx_pkt_err(u32 status, struct net_device_stats *stats)
0666 {
0667 #define TxErrMask   (WND | TABRT | FIFO | LINK)
0668 
0669     if (!unlikely(status & TxErrMask))
0670         return 0;
0671 
0672     if (status & WND)
0673         stats->tx_window_errors++;
0674     if (status & TABRT)
0675         stats->tx_aborted_errors++;
0676     if (status & FIFO)
0677         stats->tx_fifo_errors++;
0678     if (status & LINK)
0679         stats->tx_carrier_errors++;
0680 
0681     stats->tx_errors++;
0682 
0683     return -1;
0684 }
0685 
0686 static void sis190_tx_interrupt(struct net_device *dev,
0687                 struct sis190_private *tp, void __iomem *ioaddr)
0688 {
0689     struct net_device_stats *stats = &dev->stats;
0690     u32 pending, dirty_tx = tp->dirty_tx;
0691     /*
0692      * It would not be needed if queueing was allowed to be enabled
0693      * again too early (hint: think preempt and unclocked smp systems).
0694      */
0695     unsigned int queue_stopped;
0696 
0697     smp_rmb();
0698     pending = tp->cur_tx - dirty_tx;
0699     queue_stopped = (pending == NUM_TX_DESC);
0700 
0701     for (; pending; pending--, dirty_tx++) {
0702         unsigned int entry = dirty_tx % NUM_TX_DESC;
0703         struct TxDesc *txd = tp->TxDescRing + entry;
0704         u32 status = le32_to_cpu(txd->status);
0705         struct sk_buff *skb;
0706 
0707         if (status & OWNbit)
0708             break;
0709 
0710         skb = tp->Tx_skbuff[entry];
0711 
0712         if (likely(sis190_tx_pkt_err(status, stats) == 0)) {
0713             stats->tx_packets++;
0714             stats->tx_bytes += skb->len;
0715             stats->collisions += ((status & ColCountMask) - 1);
0716         }
0717 
0718         sis190_unmap_tx_skb(tp->pci_dev, skb, txd);
0719         tp->Tx_skbuff[entry] = NULL;
0720         dev_consume_skb_irq(skb);
0721     }
0722 
0723     if (tp->dirty_tx != dirty_tx) {
0724         tp->dirty_tx = dirty_tx;
0725         smp_wmb();
0726         if (queue_stopped)
0727             netif_wake_queue(dev);
0728     }
0729 }
0730 
0731 /*
0732  * The interrupt handler does all of the Rx thread work and cleans up after
0733  * the Tx thread.
0734  */
0735 static irqreturn_t sis190_irq(int irq, void *__dev)
0736 {
0737     struct net_device *dev = __dev;
0738     struct sis190_private *tp = netdev_priv(dev);
0739     void __iomem *ioaddr = tp->mmio_addr;
0740     unsigned int handled = 0;
0741     u32 status;
0742 
0743     status = SIS_R32(IntrStatus);
0744 
0745     if ((status == 0xffffffff) || !status)
0746         goto out;
0747 
0748     handled = 1;
0749 
0750     if (unlikely(!netif_running(dev))) {
0751         sis190_asic_down(ioaddr);
0752         goto out;
0753     }
0754 
0755     SIS_W32(IntrStatus, status);
0756 
0757 //  netif_info(tp, intr, dev, "status = %08x\n", status);
0758 
0759     if (status & LinkChange) {
0760         netif_info(tp, intr, dev, "link change\n");
0761         del_timer(&tp->timer);
0762         schedule_work(&tp->phy_task);
0763     }
0764 
0765     if (status & RxQInt)
0766         sis190_rx_interrupt(dev, tp, ioaddr);
0767 
0768     if (status & TxQ0Int)
0769         sis190_tx_interrupt(dev, tp, ioaddr);
0770 out:
0771     return IRQ_RETVAL(handled);
0772 }
0773 
0774 #ifdef CONFIG_NET_POLL_CONTROLLER
0775 static void sis190_netpoll(struct net_device *dev)
0776 {
0777     struct sis190_private *tp = netdev_priv(dev);
0778     const int irq = tp->pci_dev->irq;
0779 
0780     disable_irq(irq);
0781     sis190_irq(irq, dev);
0782     enable_irq(irq);
0783 }
0784 #endif
0785 
0786 static void sis190_free_rx_skb(struct sis190_private *tp,
0787                    struct sk_buff **sk_buff, struct RxDesc *desc)
0788 {
0789     struct pci_dev *pdev = tp->pci_dev;
0790 
0791     dma_unmap_single(&pdev->dev, le32_to_cpu(desc->addr), tp->rx_buf_sz,
0792              DMA_FROM_DEVICE);
0793     dev_kfree_skb(*sk_buff);
0794     *sk_buff = NULL;
0795     sis190_make_unusable_by_asic(desc);
0796 }
0797 
0798 static void sis190_rx_clear(struct sis190_private *tp)
0799 {
0800     unsigned int i;
0801 
0802     for (i = 0; i < NUM_RX_DESC; i++) {
0803         if (!tp->Rx_skbuff[i])
0804             continue;
0805         sis190_free_rx_skb(tp, tp->Rx_skbuff + i, tp->RxDescRing + i);
0806     }
0807 }
0808 
0809 static void sis190_init_ring_indexes(struct sis190_private *tp)
0810 {
0811     tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
0812 }
0813 
0814 static int sis190_init_ring(struct net_device *dev)
0815 {
0816     struct sis190_private *tp = netdev_priv(dev);
0817 
0818     sis190_init_ring_indexes(tp);
0819 
0820     memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));
0821     memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
0822 
0823     if (sis190_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
0824         goto err_rx_clear;
0825 
0826     sis190_mark_as_last_descriptor(tp->RxDescRing + NUM_RX_DESC - 1);
0827 
0828     return 0;
0829 
0830 err_rx_clear:
0831     sis190_rx_clear(tp);
0832     return -ENOMEM;
0833 }
0834 
0835 static void sis190_set_rx_mode(struct net_device *dev)
0836 {
0837     struct sis190_private *tp = netdev_priv(dev);
0838     void __iomem *ioaddr = tp->mmio_addr;
0839     unsigned long flags;
0840     u32 mc_filter[2];   /* Multicast hash filter */
0841     u16 rx_mode;
0842 
0843     if (dev->flags & IFF_PROMISC) {
0844         rx_mode =
0845             AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
0846             AcceptAllPhys;
0847         mc_filter[1] = mc_filter[0] = 0xffffffff;
0848     } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
0849            (dev->flags & IFF_ALLMULTI)) {
0850         /* Too many to filter perfectly -- accept all multicasts. */
0851         rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
0852         mc_filter[1] = mc_filter[0] = 0xffffffff;
0853     } else {
0854         struct netdev_hw_addr *ha;
0855 
0856         rx_mode = AcceptBroadcast | AcceptMyPhys;
0857         mc_filter[1] = mc_filter[0] = 0;
0858         netdev_for_each_mc_addr(ha, dev) {
0859             int bit_nr =
0860                 ether_crc(ETH_ALEN, ha->addr) & 0x3f;
0861             mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
0862             rx_mode |= AcceptMulticast;
0863         }
0864     }
0865 
0866     spin_lock_irqsave(&tp->lock, flags);
0867 
0868     SIS_W16(RxMacControl, rx_mode | 0x2);
0869     SIS_W32(RxHashTable, mc_filter[0]);
0870     SIS_W32(RxHashTable + 4, mc_filter[1]);
0871 
0872     spin_unlock_irqrestore(&tp->lock, flags);
0873 }
0874 
0875 static void sis190_soft_reset(void __iomem *ioaddr)
0876 {
0877     SIS_W32(IntrControl, 0x8000);
0878     SIS_PCI_COMMIT();
0879     SIS_W32(IntrControl, 0x0);
0880     sis190_asic_down(ioaddr);
0881 }
0882 
0883 static void sis190_hw_start(struct net_device *dev)
0884 {
0885     struct sis190_private *tp = netdev_priv(dev);
0886     void __iomem *ioaddr = tp->mmio_addr;
0887 
0888     sis190_soft_reset(ioaddr);
0889 
0890     SIS_W32(TxDescStartAddr, tp->tx_dma);
0891     SIS_W32(RxDescStartAddr, tp->rx_dma);
0892 
0893     SIS_W32(IntrStatus, 0xffffffff);
0894     SIS_W32(IntrMask, 0x0);
0895     SIS_W32(GMIIControl, 0x0);
0896     SIS_W32(TxMacControl, 0x60);
0897     SIS_W16(RxMacControl, 0x02);
0898     SIS_W32(RxHashTable, 0x0);
0899     SIS_W32(0x6c, 0x0);
0900     SIS_W32(RxWolCtrl, 0x0);
0901     SIS_W32(RxWolData, 0x0);
0902 
0903     SIS_PCI_COMMIT();
0904 
0905     sis190_set_rx_mode(dev);
0906 
0907     /* Enable all known interrupts by setting the interrupt mask. */
0908     SIS_W32(IntrMask, sis190_intr_mask);
0909 
0910     SIS_W32(TxControl, 0x1a00 | CmdTxEnb);
0911     SIS_W32(RxControl, 0x1a1d);
0912 
0913     netif_start_queue(dev);
0914 }
0915 
0916 static void sis190_phy_task(struct work_struct *work)
0917 {
0918     struct sis190_private *tp =
0919         container_of(work, struct sis190_private, phy_task);
0920     struct net_device *dev = tp->dev;
0921     void __iomem *ioaddr = tp->mmio_addr;
0922     int phy_id = tp->mii_if.phy_id;
0923     u16 val;
0924 
0925     rtnl_lock();
0926 
0927     if (!netif_running(dev))
0928         goto out_unlock;
0929 
0930     val = mdio_read(ioaddr, phy_id, MII_BMCR);
0931     if (val & BMCR_RESET) {
0932         // FIXME: needlessly high ?  -- FR 02/07/2005
0933         mod_timer(&tp->timer, jiffies + HZ/10);
0934         goto out_unlock;
0935     }
0936 
0937     val = mdio_read_latched(ioaddr, phy_id, MII_BMSR);
0938     if (!(val & BMSR_ANEGCOMPLETE) && tp->link_status != LNK_AUTONEG) {
0939         netif_carrier_off(dev);
0940         netif_warn(tp, link, dev, "auto-negotiating...\n");
0941         tp->link_status = LNK_AUTONEG;
0942     } else if ((val & BMSR_LSTATUS) && tp->link_status != LNK_ON) {
0943         /* Rejoice ! */
0944         struct {
0945             int val;
0946             u32 ctl;
0947             const char *msg;
0948         } reg31[] = {
0949             { LPA_1000FULL, 0x07000c00 | 0x00001000,
0950                 "1000 Mbps Full Duplex" },
0951             { LPA_1000HALF, 0x07000c00,
0952                 "1000 Mbps Half Duplex" },
0953             { LPA_100FULL, 0x04000800 | 0x00001000,
0954                 "100 Mbps Full Duplex" },
0955             { LPA_100HALF, 0x04000800,
0956                 "100 Mbps Half Duplex" },
0957             { LPA_10FULL, 0x04000400 | 0x00001000,
0958                 "10 Mbps Full Duplex" },
0959             { LPA_10HALF, 0x04000400,
0960                 "10 Mbps Half Duplex" },
0961             { 0, 0x04000400, "unknown" }
0962         }, *p = NULL;
0963         u16 adv, autoexp, gigadv, gigrec;
0964 
0965         val = mdio_read(ioaddr, phy_id, 0x1f);
0966         netif_info(tp, link, dev, "mii ext = %04x\n", val);
0967 
0968         val = mdio_read(ioaddr, phy_id, MII_LPA);
0969         adv = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
0970         autoexp = mdio_read(ioaddr, phy_id, MII_EXPANSION);
0971         netif_info(tp, link, dev, "mii lpa=%04x adv=%04x exp=%04x\n",
0972                val, adv, autoexp);
0973 
0974         if (val & LPA_NPAGE && autoexp & EXPANSION_NWAY) {
0975             /* check for gigabit speed */
0976             gigadv = mdio_read(ioaddr, phy_id, MII_CTRL1000);
0977             gigrec = mdio_read(ioaddr, phy_id, MII_STAT1000);
0978             val = (gigadv & (gigrec >> 2));
0979             if (val & ADVERTISE_1000FULL)
0980                 p = reg31;
0981             else if (val & ADVERTISE_1000HALF)
0982                 p = reg31 + 1;
0983         }
0984         if (!p) {
0985             val &= adv;
0986 
0987             for (p = reg31; p->val; p++) {
0988                 if ((val & p->val) == p->val)
0989                     break;
0990             }
0991         }
0992 
0993         p->ctl |= SIS_R32(StationControl) & ~0x0f001c00;
0994 
0995         if ((tp->features & F_HAS_RGMII) &&
0996             (tp->features & F_PHY_BCM5461)) {
0997             // Set Tx Delay in RGMII mode.
0998             mdio_write(ioaddr, phy_id, 0x18, 0xf1c7);
0999             udelay(200);
1000             mdio_write(ioaddr, phy_id, 0x1c, 0x8c00);
1001             p->ctl |= 0x03000000;
1002         }
1003 
1004         SIS_W32(StationControl, p->ctl);
1005 
1006         if (tp->features & F_HAS_RGMII) {
1007             SIS_W32(RGDelay, 0x0441);
1008             SIS_W32(RGDelay, 0x0440);
1009         }
1010 
1011         tp->negotiated_lpa = p->val;
1012 
1013         netif_info(tp, link, dev, "link on %s mode\n", p->msg);
1014         netif_carrier_on(dev);
1015         tp->link_status = LNK_ON;
1016     } else if (!(val & BMSR_LSTATUS) && tp->link_status != LNK_AUTONEG)
1017         tp->link_status = LNK_OFF;
1018     mod_timer(&tp->timer, jiffies + SIS190_PHY_TIMEOUT);
1019 
1020 out_unlock:
1021     rtnl_unlock();
1022 }
1023 
1024 static void sis190_phy_timer(struct timer_list *t)
1025 {
1026     struct sis190_private *tp = from_timer(tp, t, timer);
1027     struct net_device *dev = tp->dev;
1028 
1029     if (likely(netif_running(dev)))
1030         schedule_work(&tp->phy_task);
1031 }
1032 
1033 static inline void sis190_delete_timer(struct net_device *dev)
1034 {
1035     struct sis190_private *tp = netdev_priv(dev);
1036 
1037     del_timer_sync(&tp->timer);
1038 }
1039 
1040 static inline void sis190_request_timer(struct net_device *dev)
1041 {
1042     struct sis190_private *tp = netdev_priv(dev);
1043     struct timer_list *timer = &tp->timer;
1044 
1045     timer_setup(timer, sis190_phy_timer, 0);
1046     timer->expires = jiffies + SIS190_PHY_TIMEOUT;
1047     add_timer(timer);
1048 }
1049 
1050 static void sis190_set_rxbufsize(struct sis190_private *tp,
1051                  struct net_device *dev)
1052 {
1053     unsigned int mtu = dev->mtu;
1054 
1055     tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1056     /* RxDesc->size has a licence to kill the lower bits */
1057     if (tp->rx_buf_sz & 0x07) {
1058         tp->rx_buf_sz += 8;
1059         tp->rx_buf_sz &= RX_BUF_MASK;
1060     }
1061 }
1062 
1063 static int sis190_open(struct net_device *dev)
1064 {
1065     struct sis190_private *tp = netdev_priv(dev);
1066     struct pci_dev *pdev = tp->pci_dev;
1067     int rc = -ENOMEM;
1068 
1069     sis190_set_rxbufsize(tp, dev);
1070 
1071     /*
1072      * Rx and Tx descriptors need 256 bytes alignment.
1073      * dma_alloc_coherent() guarantees a stronger alignment.
1074      */
1075     tp->TxDescRing = dma_alloc_coherent(&pdev->dev, TX_RING_BYTES,
1076                         &tp->tx_dma, GFP_KERNEL);
1077     if (!tp->TxDescRing)
1078         goto out;
1079 
1080     tp->RxDescRing = dma_alloc_coherent(&pdev->dev, RX_RING_BYTES,
1081                         &tp->rx_dma, GFP_KERNEL);
1082     if (!tp->RxDescRing)
1083         goto err_free_tx_0;
1084 
1085     rc = sis190_init_ring(dev);
1086     if (rc < 0)
1087         goto err_free_rx_1;
1088 
1089     sis190_request_timer(dev);
1090 
1091     rc = request_irq(pdev->irq, sis190_irq, IRQF_SHARED, dev->name, dev);
1092     if (rc < 0)
1093         goto err_release_timer_2;
1094 
1095     sis190_hw_start(dev);
1096 out:
1097     return rc;
1098 
1099 err_release_timer_2:
1100     sis190_delete_timer(dev);
1101     sis190_rx_clear(tp);
1102 err_free_rx_1:
1103     dma_free_coherent(&pdev->dev, RX_RING_BYTES, tp->RxDescRing,
1104               tp->rx_dma);
1105 err_free_tx_0:
1106     dma_free_coherent(&pdev->dev, TX_RING_BYTES, tp->TxDescRing,
1107               tp->tx_dma);
1108     goto out;
1109 }
1110 
1111 static void sis190_tx_clear(struct sis190_private *tp)
1112 {
1113     unsigned int i;
1114 
1115     for (i = 0; i < NUM_TX_DESC; i++) {
1116         struct sk_buff *skb = tp->Tx_skbuff[i];
1117 
1118         if (!skb)
1119             continue;
1120 
1121         sis190_unmap_tx_skb(tp->pci_dev, skb, tp->TxDescRing + i);
1122         tp->Tx_skbuff[i] = NULL;
1123         dev_kfree_skb(skb);
1124 
1125         tp->dev->stats.tx_dropped++;
1126     }
1127     tp->cur_tx = tp->dirty_tx = 0;
1128 }
1129 
1130 static void sis190_down(struct net_device *dev)
1131 {
1132     struct sis190_private *tp = netdev_priv(dev);
1133     void __iomem *ioaddr = tp->mmio_addr;
1134     unsigned int poll_locked = 0;
1135 
1136     sis190_delete_timer(dev);
1137 
1138     netif_stop_queue(dev);
1139 
1140     do {
1141         spin_lock_irq(&tp->lock);
1142 
1143         sis190_asic_down(ioaddr);
1144 
1145         spin_unlock_irq(&tp->lock);
1146 
1147         synchronize_irq(tp->pci_dev->irq);
1148 
1149         if (!poll_locked)
1150             poll_locked++;
1151 
1152         synchronize_rcu();
1153 
1154     } while (SIS_R32(IntrMask));
1155 
1156     sis190_tx_clear(tp);
1157     sis190_rx_clear(tp);
1158 }
1159 
1160 static int sis190_close(struct net_device *dev)
1161 {
1162     struct sis190_private *tp = netdev_priv(dev);
1163     struct pci_dev *pdev = tp->pci_dev;
1164 
1165     sis190_down(dev);
1166 
1167     free_irq(pdev->irq, dev);
1168 
1169     dma_free_coherent(&pdev->dev, TX_RING_BYTES, tp->TxDescRing,
1170               tp->tx_dma);
1171     dma_free_coherent(&pdev->dev, RX_RING_BYTES, tp->RxDescRing,
1172               tp->rx_dma);
1173 
1174     tp->TxDescRing = NULL;
1175     tp->RxDescRing = NULL;
1176 
1177     return 0;
1178 }
1179 
1180 static netdev_tx_t sis190_start_xmit(struct sk_buff *skb,
1181                      struct net_device *dev)
1182 {
1183     struct sis190_private *tp = netdev_priv(dev);
1184     void __iomem *ioaddr = tp->mmio_addr;
1185     u32 len, entry, dirty_tx;
1186     struct TxDesc *desc;
1187     dma_addr_t mapping;
1188 
1189     if (unlikely(skb->len < ETH_ZLEN)) {
1190         if (skb_padto(skb, ETH_ZLEN)) {
1191             dev->stats.tx_dropped++;
1192             goto out;
1193         }
1194         len = ETH_ZLEN;
1195     } else {
1196         len = skb->len;
1197     }
1198 
1199     entry = tp->cur_tx % NUM_TX_DESC;
1200     desc = tp->TxDescRing + entry;
1201 
1202     if (unlikely(le32_to_cpu(desc->status) & OWNbit)) {
1203         netif_stop_queue(dev);
1204         netif_err(tp, tx_err, dev,
1205               "BUG! Tx Ring full when queue awake!\n");
1206         return NETDEV_TX_BUSY;
1207     }
1208 
1209     mapping = dma_map_single(&tp->pci_dev->dev, skb->data, len,
1210                  DMA_TO_DEVICE);
1211     if (dma_mapping_error(&tp->pci_dev->dev, mapping)) {
1212         netif_err(tp, tx_err, dev,
1213                 "PCI mapping failed, dropping packet");
1214         return NETDEV_TX_BUSY;
1215     }
1216 
1217     tp->Tx_skbuff[entry] = skb;
1218 
1219     desc->PSize = cpu_to_le32(len);
1220     desc->addr = cpu_to_le32(mapping);
1221 
1222     desc->size = cpu_to_le32(len);
1223     if (entry == (NUM_TX_DESC - 1))
1224         desc->size |= cpu_to_le32(RingEnd);
1225 
1226     wmb();
1227 
1228     desc->status = cpu_to_le32(OWNbit | INTbit | DEFbit | CRCbit | PADbit);
1229     if (tp->negotiated_lpa & (LPA_1000HALF | LPA_100HALF | LPA_10HALF)) {
1230         /* Half Duplex */
1231         desc->status |= cpu_to_le32(COLEN | CRSEN | BKFEN);
1232         if (tp->negotiated_lpa & (LPA_1000HALF | LPA_1000FULL))
1233             desc->status |= cpu_to_le32(EXTEN | BSTEN); /* gigabit HD */
1234     }
1235 
1236     tp->cur_tx++;
1237 
1238     smp_wmb();
1239 
1240     SIS_W32(TxControl, 0x1a00 | CmdReset | CmdTxEnb);
1241 
1242     dirty_tx = tp->dirty_tx;
1243     if ((tp->cur_tx - NUM_TX_DESC) == dirty_tx) {
1244         netif_stop_queue(dev);
1245         smp_rmb();
1246         if (dirty_tx != tp->dirty_tx)
1247             netif_wake_queue(dev);
1248     }
1249 out:
1250     return NETDEV_TX_OK;
1251 }
1252 
1253 static void sis190_free_phy(struct list_head *first_phy)
1254 {
1255     struct sis190_phy *cur, *next;
1256 
1257     list_for_each_entry_safe(cur, next, first_phy, list) {
1258         kfree(cur);
1259     }
1260 }
1261 
1262 /**
1263  *  sis190_default_phy - Select default PHY for sis190 mac.
1264  *  @dev: the net device to probe for
1265  *
1266  *  Select first detected PHY with link as default.
1267  *  If no one is link on, select PHY whose types is HOME as default.
1268  *  If HOME doesn't exist, select LAN.
1269  */
1270 static u16 sis190_default_phy(struct net_device *dev)
1271 {
1272     struct sis190_phy *phy, *phy_home, *phy_default, *phy_lan;
1273     struct sis190_private *tp = netdev_priv(dev);
1274     struct mii_if_info *mii_if = &tp->mii_if;
1275     void __iomem *ioaddr = tp->mmio_addr;
1276     u16 status;
1277 
1278     phy_home = phy_default = phy_lan = NULL;
1279 
1280     list_for_each_entry(phy, &tp->first_phy, list) {
1281         status = mdio_read_latched(ioaddr, phy->phy_id, MII_BMSR);
1282 
1283         // Link ON & Not select default PHY & not ghost PHY.
1284         if ((status & BMSR_LSTATUS) &&
1285             !phy_default &&
1286             (phy->type != UNKNOWN)) {
1287             phy_default = phy;
1288         } else {
1289             status = mdio_read(ioaddr, phy->phy_id, MII_BMCR);
1290             mdio_write(ioaddr, phy->phy_id, MII_BMCR,
1291                    status | BMCR_ANENABLE | BMCR_ISOLATE);
1292             if (phy->type == HOME)
1293                 phy_home = phy;
1294             else if (phy->type == LAN)
1295                 phy_lan = phy;
1296         }
1297     }
1298 
1299     if (!phy_default) {
1300         if (phy_home)
1301             phy_default = phy_home;
1302         else if (phy_lan)
1303             phy_default = phy_lan;
1304         else
1305             phy_default = list_first_entry(&tp->first_phy,
1306                          struct sis190_phy, list);
1307     }
1308 
1309     if (mii_if->phy_id != phy_default->phy_id) {
1310         mii_if->phy_id = phy_default->phy_id;
1311         if (netif_msg_probe(tp))
1312             pr_info("%s: Using transceiver at address %d as default\n",
1313                 pci_name(tp->pci_dev), mii_if->phy_id);
1314     }
1315 
1316     status = mdio_read(ioaddr, mii_if->phy_id, MII_BMCR);
1317     status &= (~BMCR_ISOLATE);
1318 
1319     mdio_write(ioaddr, mii_if->phy_id, MII_BMCR, status);
1320     status = mdio_read_latched(ioaddr, mii_if->phy_id, MII_BMSR);
1321 
1322     return status;
1323 }
1324 
1325 static void sis190_init_phy(struct net_device *dev, struct sis190_private *tp,
1326                 struct sis190_phy *phy, unsigned int phy_id,
1327                 u16 mii_status)
1328 {
1329     void __iomem *ioaddr = tp->mmio_addr;
1330     struct mii_chip_info *p;
1331 
1332     INIT_LIST_HEAD(&phy->list);
1333     phy->status = mii_status;
1334     phy->phy_id = phy_id;
1335 
1336     phy->id[0] = mdio_read(ioaddr, phy_id, MII_PHYSID1);
1337     phy->id[1] = mdio_read(ioaddr, phy_id, MII_PHYSID2);
1338 
1339     for (p = mii_chip_table; p->type; p++) {
1340         if ((p->id[0] == phy->id[0]) &&
1341             (p->id[1] == (phy->id[1] & 0xfff0))) {
1342             break;
1343         }
1344     }
1345 
1346     if (p->id[1]) {
1347         phy->type = (p->type == MIX) ?
1348             ((mii_status & (BMSR_100FULL | BMSR_100HALF)) ?
1349                 LAN : HOME) : p->type;
1350         tp->features |= p->feature;
1351         if (netif_msg_probe(tp))
1352             pr_info("%s: %s transceiver at address %d\n",
1353                 pci_name(tp->pci_dev), p->name, phy_id);
1354     } else {
1355         phy->type = UNKNOWN;
1356         if (netif_msg_probe(tp))
1357             pr_info("%s: unknown PHY 0x%x:0x%x transceiver at address %d\n",
1358                 pci_name(tp->pci_dev),
1359                 phy->id[0], (phy->id[1] & 0xfff0), phy_id);
1360     }
1361 }
1362 
1363 static void sis190_mii_probe_88e1111_fixup(struct sis190_private *tp)
1364 {
1365     if (tp->features & F_PHY_88E1111) {
1366         void __iomem *ioaddr = tp->mmio_addr;
1367         int phy_id = tp->mii_if.phy_id;
1368         u16 reg[2][2] = {
1369             { 0x808b, 0x0ce1 },
1370             { 0x808f, 0x0c60 }
1371         }, *p;
1372 
1373         p = (tp->features & F_HAS_RGMII) ? reg[0] : reg[1];
1374 
1375         mdio_write(ioaddr, phy_id, 0x1b, p[0]);
1376         udelay(200);
1377         mdio_write(ioaddr, phy_id, 0x14, p[1]);
1378         udelay(200);
1379     }
1380 }
1381 
1382 /**
1383  *  sis190_mii_probe - Probe MII PHY for sis190
1384  *  @dev: the net device to probe for
1385  *
1386  *  Search for total of 32 possible mii phy addresses.
1387  *  Identify and set current phy if found one,
1388  *  return error if it failed to found.
1389  */
1390 static int sis190_mii_probe(struct net_device *dev)
1391 {
1392     struct sis190_private *tp = netdev_priv(dev);
1393     struct mii_if_info *mii_if = &tp->mii_if;
1394     void __iomem *ioaddr = tp->mmio_addr;
1395     int phy_id;
1396     int rc = 0;
1397 
1398     INIT_LIST_HEAD(&tp->first_phy);
1399 
1400     for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1401         struct sis190_phy *phy;
1402         u16 status;
1403 
1404         status = mdio_read_latched(ioaddr, phy_id, MII_BMSR);
1405 
1406         // Try next mii if the current one is not accessible.
1407         if (status == 0xffff || status == 0x0000)
1408             continue;
1409 
1410         phy = kmalloc(sizeof(*phy), GFP_KERNEL);
1411         if (!phy) {
1412             sis190_free_phy(&tp->first_phy);
1413             rc = -ENOMEM;
1414             goto out;
1415         }
1416 
1417         sis190_init_phy(dev, tp, phy, phy_id, status);
1418 
1419         list_add(&tp->first_phy, &phy->list);
1420     }
1421 
1422     if (list_empty(&tp->first_phy)) {
1423         if (netif_msg_probe(tp))
1424             pr_info("%s: No MII transceivers found!\n",
1425                 pci_name(tp->pci_dev));
1426         rc = -EIO;
1427         goto out;
1428     }
1429 
1430     /* Select default PHY for mac */
1431     sis190_default_phy(dev);
1432 
1433     sis190_mii_probe_88e1111_fixup(tp);
1434 
1435     mii_if->dev = dev;
1436     mii_if->mdio_read = __mdio_read;
1437     mii_if->mdio_write = __mdio_write;
1438     mii_if->phy_id_mask = PHY_ID_ANY;
1439     mii_if->reg_num_mask = MII_REG_ANY;
1440 out:
1441     return rc;
1442 }
1443 
1444 static void sis190_mii_remove(struct net_device *dev)
1445 {
1446     struct sis190_private *tp = netdev_priv(dev);
1447 
1448     sis190_free_phy(&tp->first_phy);
1449 }
1450 
1451 static void sis190_release_board(struct pci_dev *pdev)
1452 {
1453     struct net_device *dev = pci_get_drvdata(pdev);
1454     struct sis190_private *tp = netdev_priv(dev);
1455 
1456     iounmap(tp->mmio_addr);
1457     pci_release_regions(pdev);
1458     pci_disable_device(pdev);
1459     free_netdev(dev);
1460 }
1461 
1462 static struct net_device *sis190_init_board(struct pci_dev *pdev)
1463 {
1464     struct sis190_private *tp;
1465     struct net_device *dev;
1466     void __iomem *ioaddr;
1467     int rc;
1468 
1469     dev = alloc_etherdev(sizeof(*tp));
1470     if (!dev) {
1471         rc = -ENOMEM;
1472         goto err_out_0;
1473     }
1474 
1475     SET_NETDEV_DEV(dev, &pdev->dev);
1476 
1477     tp = netdev_priv(dev);
1478     tp->dev = dev;
1479     tp->msg_enable = netif_msg_init(debug.msg_enable, SIS190_MSG_DEFAULT);
1480 
1481     rc = pci_enable_device(pdev);
1482     if (rc < 0) {
1483         if (netif_msg_probe(tp))
1484             pr_err("%s: enable failure\n", pci_name(pdev));
1485         goto err_free_dev_1;
1486     }
1487 
1488     rc = -ENODEV;
1489 
1490     if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1491         if (netif_msg_probe(tp))
1492             pr_err("%s: region #0 is no MMIO resource\n",
1493                    pci_name(pdev));
1494         goto err_pci_disable_2;
1495     }
1496     if (pci_resource_len(pdev, 0) < SIS190_REGS_SIZE) {
1497         if (netif_msg_probe(tp))
1498             pr_err("%s: invalid PCI region size(s)\n",
1499                    pci_name(pdev));
1500         goto err_pci_disable_2;
1501     }
1502 
1503     rc = pci_request_regions(pdev, DRV_NAME);
1504     if (rc < 0) {
1505         if (netif_msg_probe(tp))
1506             pr_err("%s: could not request regions\n",
1507                    pci_name(pdev));
1508         goto err_pci_disable_2;
1509     }
1510 
1511     rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1512     if (rc < 0) {
1513         if (netif_msg_probe(tp))
1514             pr_err("%s: DMA configuration failed\n",
1515                    pci_name(pdev));
1516         goto err_free_res_3;
1517     }
1518 
1519     pci_set_master(pdev);
1520 
1521     ioaddr = ioremap(pci_resource_start(pdev, 0), SIS190_REGS_SIZE);
1522     if (!ioaddr) {
1523         if (netif_msg_probe(tp))
1524             pr_err("%s: cannot remap MMIO, aborting\n",
1525                    pci_name(pdev));
1526         rc = -EIO;
1527         goto err_free_res_3;
1528     }
1529 
1530     tp->pci_dev = pdev;
1531     tp->mmio_addr = ioaddr;
1532     tp->link_status = LNK_OFF;
1533 
1534     sis190_irq_mask_and_ack(ioaddr);
1535 
1536     sis190_soft_reset(ioaddr);
1537 out:
1538     return dev;
1539 
1540 err_free_res_3:
1541     pci_release_regions(pdev);
1542 err_pci_disable_2:
1543     pci_disable_device(pdev);
1544 err_free_dev_1:
1545     free_netdev(dev);
1546 err_out_0:
1547     dev = ERR_PTR(rc);
1548     goto out;
1549 }
1550 
1551 static void sis190_tx_timeout(struct net_device *dev, unsigned int txqueue)
1552 {
1553     struct sis190_private *tp = netdev_priv(dev);
1554     void __iomem *ioaddr = tp->mmio_addr;
1555     u8 tmp8;
1556 
1557     /* Disable Tx, if not already */
1558     tmp8 = SIS_R8(TxControl);
1559     if (tmp8 & CmdTxEnb)
1560         SIS_W8(TxControl, tmp8 & ~CmdTxEnb);
1561 
1562     netif_info(tp, tx_err, dev, "Transmit timeout, status %08x %08x\n",
1563            SIS_R32(TxControl), SIS_R32(TxSts));
1564 
1565     /* Disable interrupts by clearing the interrupt mask. */
1566     SIS_W32(IntrMask, 0x0000);
1567 
1568     /* Stop a shared interrupt from scavenging while we are. */
1569     spin_lock_irq(&tp->lock);
1570     sis190_tx_clear(tp);
1571     spin_unlock_irq(&tp->lock);
1572 
1573     /* ...and finally, reset everything. */
1574     sis190_hw_start(dev);
1575 
1576     netif_wake_queue(dev);
1577 }
1578 
1579 static void sis190_set_rgmii(struct sis190_private *tp, u8 reg)
1580 {
1581     tp->features |= (reg & 0x80) ? F_HAS_RGMII : 0;
1582 }
1583 
1584 static int sis190_get_mac_addr_from_eeprom(struct pci_dev *pdev,
1585                        struct net_device *dev)
1586 {
1587     struct sis190_private *tp = netdev_priv(dev);
1588     void __iomem *ioaddr = tp->mmio_addr;
1589     __le16 addr[ETH_ALEN / 2];
1590     u16 sig;
1591     int i;
1592 
1593     if (netif_msg_probe(tp))
1594         pr_info("%s: Read MAC address from EEPROM\n", pci_name(pdev));
1595 
1596     /* Check to see if there is a sane EEPROM */
1597     sig = (u16) sis190_read_eeprom(ioaddr, EEPROMSignature);
1598 
1599     if ((sig == 0xffff) || (sig == 0x0000)) {
1600         if (netif_msg_probe(tp))
1601             pr_info("%s: Error EEPROM read %x\n",
1602                 pci_name(pdev), sig);
1603         return -EIO;
1604     }
1605 
1606     /* Get MAC address from EEPROM */
1607     for (i = 0; i < ETH_ALEN / 2; i++) {
1608         u16 w = sis190_read_eeprom(ioaddr, EEPROMMACAddr + i);
1609 
1610         addr[i] = cpu_to_le16(w);
1611     }
1612     eth_hw_addr_set(dev, (u8 *)addr);
1613 
1614     sis190_set_rgmii(tp, sis190_read_eeprom(ioaddr, EEPROMInfo));
1615 
1616     return 0;
1617 }
1618 
1619 /**
1620  *  sis190_get_mac_addr_from_apc - Get MAC address for SiS96x model
1621  *  @pdev: PCI device
1622  *  @dev:  network device to get address for
1623  *
1624  *  SiS96x model, use APC CMOS RAM to store MAC address.
1625  *  APC CMOS RAM is accessed through ISA bridge.
1626  *  MAC address is read into @net_dev->dev_addr.
1627  */
1628 static int sis190_get_mac_addr_from_apc(struct pci_dev *pdev,
1629                     struct net_device *dev)
1630 {
1631     static const u16 ids[] = { 0x0965, 0x0966, 0x0968 };
1632     struct sis190_private *tp = netdev_priv(dev);
1633     struct pci_dev *isa_bridge;
1634     u8 addr[ETH_ALEN];
1635     u8 reg, tmp8;
1636     unsigned int i;
1637 
1638     if (netif_msg_probe(tp))
1639         pr_info("%s: Read MAC address from APC\n", pci_name(pdev));
1640 
1641     for (i = 0; i < ARRAY_SIZE(ids); i++) {
1642         isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, ids[i], NULL);
1643         if (isa_bridge)
1644             break;
1645     }
1646 
1647     if (!isa_bridge) {
1648         if (netif_msg_probe(tp))
1649             pr_info("%s: Can not find ISA bridge\n",
1650                 pci_name(pdev));
1651         return -EIO;
1652     }
1653 
1654     /* Enable port 78h & 79h to access APC Registers. */
1655     pci_read_config_byte(isa_bridge, 0x48, &tmp8);
1656     reg = (tmp8 & ~0x02);
1657     pci_write_config_byte(isa_bridge, 0x48, reg);
1658     udelay(50);
1659     pci_read_config_byte(isa_bridge, 0x48, &reg);
1660 
1661         for (i = 0; i < ETH_ALEN; i++) {
1662                 outb(0x9 + i, 0x78);
1663                 addr[i] = inb(0x79);
1664         }
1665     eth_hw_addr_set(dev, addr);
1666 
1667     outb(0x12, 0x78);
1668     reg = inb(0x79);
1669 
1670     sis190_set_rgmii(tp, reg);
1671 
1672     /* Restore the value to ISA Bridge */
1673     pci_write_config_byte(isa_bridge, 0x48, tmp8);
1674     pci_dev_put(isa_bridge);
1675 
1676     return 0;
1677 }
1678 
1679 /**
1680  *      sis190_init_rxfilter - Initialize the Rx filter
1681  *      @dev: network device to initialize
1682  *
1683  *      Set receive filter address to our MAC address
1684  *      and enable packet filtering.
1685  */
1686 static inline void sis190_init_rxfilter(struct net_device *dev)
1687 {
1688     struct sis190_private *tp = netdev_priv(dev);
1689     void __iomem *ioaddr = tp->mmio_addr;
1690     u16 ctl;
1691     int i;
1692 
1693     ctl = SIS_R16(RxMacControl);
1694     /*
1695      * Disable packet filtering before setting filter.
1696      * Note: SiS's driver writes 32 bits but RxMacControl is 16 bits
1697      * only and followed by RxMacAddr (6 bytes). Strange. -- FR
1698      */
1699     SIS_W16(RxMacControl, ctl & ~0x0f00);
1700 
1701     for (i = 0; i < ETH_ALEN; i++)
1702         SIS_W8(RxMacAddr + i, dev->dev_addr[i]);
1703 
1704     SIS_W16(RxMacControl, ctl);
1705     SIS_PCI_COMMIT();
1706 }
1707 
1708 static int sis190_get_mac_addr(struct pci_dev *pdev, struct net_device *dev)
1709 {
1710     int rc;
1711 
1712     rc = sis190_get_mac_addr_from_eeprom(pdev, dev);
1713     if (rc < 0) {
1714         u8 reg;
1715 
1716         pci_read_config_byte(pdev, 0x73, &reg);
1717 
1718         if (reg & 0x00000001)
1719             rc = sis190_get_mac_addr_from_apc(pdev, dev);
1720     }
1721     return rc;
1722 }
1723 
1724 static void sis190_set_speed_auto(struct net_device *dev)
1725 {
1726     struct sis190_private *tp = netdev_priv(dev);
1727     void __iomem *ioaddr = tp->mmio_addr;
1728     int phy_id = tp->mii_if.phy_id;
1729     int val;
1730 
1731     netif_info(tp, link, dev, "Enabling Auto-negotiation\n");
1732 
1733     val = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
1734 
1735     // Enable 10/100 Full/Half Mode, leave MII_ADVERTISE bit4:0
1736     // unchanged.
1737     mdio_write(ioaddr, phy_id, MII_ADVERTISE, (val & ADVERTISE_SLCT) |
1738            ADVERTISE_100FULL | ADVERTISE_10FULL |
1739            ADVERTISE_100HALF | ADVERTISE_10HALF);
1740 
1741     // Enable 1000 Full Mode.
1742     mdio_write(ioaddr, phy_id, MII_CTRL1000, ADVERTISE_1000FULL);
1743 
1744     // Enable auto-negotiation and restart auto-negotiation.
1745     mdio_write(ioaddr, phy_id, MII_BMCR,
1746            BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
1747 }
1748 
1749 static int sis190_get_link_ksettings(struct net_device *dev,
1750                      struct ethtool_link_ksettings *cmd)
1751 {
1752     struct sis190_private *tp = netdev_priv(dev);
1753 
1754     mii_ethtool_get_link_ksettings(&tp->mii_if, cmd);
1755 
1756     return 0;
1757 }
1758 
1759 static int sis190_set_link_ksettings(struct net_device *dev,
1760                      const struct ethtool_link_ksettings *cmd)
1761 {
1762     struct sis190_private *tp = netdev_priv(dev);
1763 
1764     return mii_ethtool_set_link_ksettings(&tp->mii_if, cmd);
1765 }
1766 
1767 static void sis190_get_drvinfo(struct net_device *dev,
1768                    struct ethtool_drvinfo *info)
1769 {
1770     struct sis190_private *tp = netdev_priv(dev);
1771 
1772     strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1773     strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1774     strlcpy(info->bus_info, pci_name(tp->pci_dev),
1775         sizeof(info->bus_info));
1776 }
1777 
1778 static int sis190_get_regs_len(struct net_device *dev)
1779 {
1780     return SIS190_REGS_SIZE;
1781 }
1782 
1783 static void sis190_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1784                 void *p)
1785 {
1786     struct sis190_private *tp = netdev_priv(dev);
1787     unsigned long flags;
1788 
1789     spin_lock_irqsave(&tp->lock, flags);
1790     memcpy_fromio(p, tp->mmio_addr, regs->len);
1791     spin_unlock_irqrestore(&tp->lock, flags);
1792 }
1793 
1794 static int sis190_nway_reset(struct net_device *dev)
1795 {
1796     struct sis190_private *tp = netdev_priv(dev);
1797 
1798     return mii_nway_restart(&tp->mii_if);
1799 }
1800 
1801 static u32 sis190_get_msglevel(struct net_device *dev)
1802 {
1803     struct sis190_private *tp = netdev_priv(dev);
1804 
1805     return tp->msg_enable;
1806 }
1807 
1808 static void sis190_set_msglevel(struct net_device *dev, u32 value)
1809 {
1810     struct sis190_private *tp = netdev_priv(dev);
1811 
1812     tp->msg_enable = value;
1813 }
1814 
1815 static const struct ethtool_ops sis190_ethtool_ops = {
1816     .get_drvinfo    = sis190_get_drvinfo,
1817     .get_regs_len   = sis190_get_regs_len,
1818     .get_regs   = sis190_get_regs,
1819     .get_link   = ethtool_op_get_link,
1820     .get_msglevel   = sis190_get_msglevel,
1821     .set_msglevel   = sis190_set_msglevel,
1822     .nway_reset = sis190_nway_reset,
1823     .get_link_ksettings = sis190_get_link_ksettings,
1824     .set_link_ksettings = sis190_set_link_ksettings,
1825 };
1826 
1827 static int sis190_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1828 {
1829     struct sis190_private *tp = netdev_priv(dev);
1830 
1831     return !netif_running(dev) ? -EINVAL :
1832         generic_mii_ioctl(&tp->mii_if, if_mii(ifr), cmd, NULL);
1833 }
1834 
1835 static int sis190_mac_addr(struct net_device  *dev, void *p)
1836 {
1837     int rc;
1838 
1839     rc = eth_mac_addr(dev, p);
1840     if (!rc)
1841         sis190_init_rxfilter(dev);
1842     return rc;
1843 }
1844 
1845 static const struct net_device_ops sis190_netdev_ops = {
1846     .ndo_open       = sis190_open,
1847     .ndo_stop       = sis190_close,
1848     .ndo_eth_ioctl      = sis190_ioctl,
1849     .ndo_start_xmit     = sis190_start_xmit,
1850     .ndo_tx_timeout     = sis190_tx_timeout,
1851     .ndo_set_rx_mode    = sis190_set_rx_mode,
1852     .ndo_set_mac_address    = sis190_mac_addr,
1853     .ndo_validate_addr  = eth_validate_addr,
1854 #ifdef CONFIG_NET_POLL_CONTROLLER
1855     .ndo_poll_controller     = sis190_netpoll,
1856 #endif
1857 };
1858 
1859 static int sis190_init_one(struct pci_dev *pdev,
1860                const struct pci_device_id *ent)
1861 {
1862     static int printed_version = 0;
1863     struct sis190_private *tp;
1864     struct net_device *dev;
1865     void __iomem *ioaddr;
1866     int rc;
1867 
1868     if (!printed_version) {
1869         if (netif_msg_drv(&debug))
1870             pr_info(SIS190_DRIVER_NAME " loaded\n");
1871         printed_version = 1;
1872     }
1873 
1874     dev = sis190_init_board(pdev);
1875     if (IS_ERR(dev)) {
1876         rc = PTR_ERR(dev);
1877         goto out;
1878     }
1879 
1880     pci_set_drvdata(pdev, dev);
1881 
1882     tp = netdev_priv(dev);
1883     ioaddr = tp->mmio_addr;
1884 
1885     rc = sis190_get_mac_addr(pdev, dev);
1886     if (rc < 0)
1887         goto err_release_board;
1888 
1889     sis190_init_rxfilter(dev);
1890 
1891     INIT_WORK(&tp->phy_task, sis190_phy_task);
1892 
1893     dev->netdev_ops = &sis190_netdev_ops;
1894 
1895     dev->ethtool_ops = &sis190_ethtool_ops;
1896     dev->watchdog_timeo = SIS190_TX_TIMEOUT;
1897 
1898     spin_lock_init(&tp->lock);
1899 
1900     rc = sis190_mii_probe(dev);
1901     if (rc < 0)
1902         goto err_release_board;
1903 
1904     rc = register_netdev(dev);
1905     if (rc < 0)
1906         goto err_remove_mii;
1907 
1908     if (netif_msg_probe(tp)) {
1909         netdev_info(dev, "%s: %s at %p (IRQ: %d), %pM\n",
1910                 pci_name(pdev),
1911                 sis_chip_info[ent->driver_data].name,
1912                 ioaddr, pdev->irq, dev->dev_addr);
1913         netdev_info(dev, "%s mode.\n",
1914                 (tp->features & F_HAS_RGMII) ? "RGMII" : "GMII");
1915     }
1916 
1917     netif_carrier_off(dev);
1918 
1919     sis190_set_speed_auto(dev);
1920 out:
1921     return rc;
1922 
1923 err_remove_mii:
1924     sis190_mii_remove(dev);
1925 err_release_board:
1926     sis190_release_board(pdev);
1927     goto out;
1928 }
1929 
1930 static void sis190_remove_one(struct pci_dev *pdev)
1931 {
1932     struct net_device *dev = pci_get_drvdata(pdev);
1933     struct sis190_private *tp = netdev_priv(dev);
1934 
1935     sis190_mii_remove(dev);
1936     cancel_work_sync(&tp->phy_task);
1937     unregister_netdev(dev);
1938     sis190_release_board(pdev);
1939 }
1940 
1941 static struct pci_driver sis190_pci_driver = {
1942     .name       = DRV_NAME,
1943     .id_table   = sis190_pci_tbl,
1944     .probe      = sis190_init_one,
1945     .remove     = sis190_remove_one,
1946 };
1947 
1948 module_pci_driver(sis190_pci_driver);
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