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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*  Silan SC92031 PCI Fast Ethernet Adapter driver
0003  *
0004  *  Based on vendor drivers:
0005  *  Silan Fast Ethernet Netcard Driver:
0006  *    MODULE_AUTHOR ("gaoyonghong");
0007  *    MODULE_DESCRIPTION ("SILAN Fast Ethernet driver");
0008  *    MODULE_LICENSE("GPL");
0009  *  8139D Fast Ethernet driver:
0010  *    (C) 2002 by gaoyonghong
0011  *    MODULE_AUTHOR ("gaoyonghong");
0012  *    MODULE_DESCRIPTION ("Rsltek 8139D PCI Fast Ethernet Adapter driver");
0013  *    MODULE_LICENSE("GPL");
0014  *  Both are almost identical and seem to be based on pci-skeleton.c
0015  *
0016  *  Rewritten for 2.6 by Cesar Eduardo Barros
0017  *
0018  *  A datasheet for this chip can be found at
0019  *  http://www.silan.com.cn/english/product/pdf/SC92031AY.pdf 
0020  */
0021 
0022 /* Note about set_mac_address: I don't know how to change the hardware
0023  * matching, so you need to enable IFF_PROMISC when using it.
0024  */
0025 
0026 #include <linux/interrupt.h>
0027 #include <linux/module.h>
0028 #include <linux/kernel.h>
0029 #include <linux/delay.h>
0030 #include <linux/pci.h>
0031 #include <linux/dma-mapping.h>
0032 #include <linux/netdevice.h>
0033 #include <linux/etherdevice.h>
0034 #include <linux/ethtool.h>
0035 #include <linux/mii.h>
0036 #include <linux/crc32.h>
0037 
0038 #include <asm/irq.h>
0039 
0040 #define SC92031_NAME "sc92031"
0041 
0042 /* BAR 0 is MMIO, BAR 1 is PIO */
0043 #define SC92031_USE_PIO 0
0044 
0045 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
0046 static int multicast_filter_limit = 64;
0047 module_param(multicast_filter_limit, int, 0);
0048 MODULE_PARM_DESC(multicast_filter_limit,
0049     "Maximum number of filtered multicast addresses");
0050 
0051 static int media;
0052 module_param(media, int, 0);
0053 MODULE_PARM_DESC(media, "Media type (0x00 = autodetect,"
0054     " 0x01 = 10M half, 0x02 = 10M full,"
0055     " 0x04 = 100M half, 0x08 = 100M full)");
0056 
0057 /* Size of the in-memory receive ring. */
0058 #define  RX_BUF_LEN_IDX  3 /* 0==8K, 1==16K, 2==32K, 3==64K ,4==128K*/
0059 #define  RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
0060 
0061 /* Number of Tx descriptor registers. */
0062 #define  NUM_TX_DESC       4
0063 
0064 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
0065 #define  MAX_ETH_FRAME_SIZE   1536
0066 
0067 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
0068 #define  TX_BUF_SIZE       MAX_ETH_FRAME_SIZE
0069 #define  TX_BUF_TOT_LEN    (TX_BUF_SIZE * NUM_TX_DESC)
0070 
0071 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */
0072 #define  RX_FIFO_THRESH    7     /* Rx buffer level before first PCI xfer.  */
0073 
0074 /* Time in jiffies before concluding the transmitter is hung. */
0075 #define  TX_TIMEOUT     (4*HZ)
0076 
0077 #define  SILAN_STATS_NUM    2    /* number of ETHTOOL_GSTATS */
0078 
0079 /* media options */
0080 #define  AUTOSELECT    0x00
0081 #define  M10_HALF      0x01
0082 #define  M10_FULL      0x02
0083 #define  M100_HALF     0x04
0084 #define  M100_FULL     0x08
0085 
0086  /* Symbolic offsets to registers. */
0087 enum  silan_registers {
0088    Config0    = 0x00,         // Config0
0089    Config1    = 0x04,         // Config1
0090    RxBufWPtr  = 0x08,         // Rx buffer writer poiter
0091    IntrStatus = 0x0C,         // Interrupt status
0092    IntrMask   = 0x10,         // Interrupt mask
0093    RxbufAddr  = 0x14,         // Rx buffer start address
0094    RxBufRPtr  = 0x18,         // Rx buffer read pointer
0095    Txstatusall = 0x1C,        // Transmit status of all descriptors
0096    TxStatus0  = 0x20,         // Transmit status (Four 32bit registers).
0097    TxAddr0    = 0x30,         // Tx descriptors (also four 32bit).
0098    RxConfig   = 0x40,         // Rx configuration
0099    MAC0       = 0x44,         // Ethernet hardware address.
0100    MAR0       = 0x4C,         // Multicast filter.
0101    RxStatus0  = 0x54,         // Rx status
0102    TxConfig   = 0x5C,         // Tx configuration
0103    PhyCtrl    = 0x60,         // physical control
0104    FlowCtrlConfig = 0x64,     // flow control
0105    Miicmd0    = 0x68,         // Mii command0 register
0106    Miicmd1    = 0x6C,         // Mii command1 register
0107    Miistatus  = 0x70,         // Mii status register
0108    Timercnt   = 0x74,         // Timer counter register
0109    TimerIntr  = 0x78,         // Timer interrupt register
0110    PMConfig   = 0x7C,         // Power Manager configuration
0111    CRC0       = 0x80,         // Power Manager CRC ( Two 32bit regisers)
0112    Wakeup0    = 0x88,         // power Manager wakeup( Eight 64bit regiser)
0113    LSBCRC0    = 0xC8,         // power Manager LSBCRC(Two 32bit regiser)
0114    TestD0     = 0xD0,
0115    TestD4     = 0xD4,
0116    TestD8     = 0xD8,
0117 };
0118 
0119 #define MII_JAB             16
0120 #define MII_OutputStatus    24
0121 
0122 #define PHY_16_JAB_ENB      0x1000
0123 #define PHY_16_PORT_ENB     0x1
0124 
0125 enum IntrStatusBits {
0126    LinkFail       = 0x80000000,
0127    LinkOK         = 0x40000000,
0128    TimeOut        = 0x20000000,
0129    RxOverflow     = 0x0040,
0130    RxOK           = 0x0020,
0131    TxOK           = 0x0001,
0132    IntrBits = LinkFail|LinkOK|TimeOut|RxOverflow|RxOK|TxOK,
0133 };
0134 
0135 enum TxStatusBits {
0136    TxCarrierLost = 0x20000000,
0137    TxAborted     = 0x10000000,
0138    TxOutOfWindow = 0x08000000,
0139    TxNccShift    = 22,
0140    EarlyTxThresShift = 16,
0141    TxStatOK      = 0x8000,
0142    TxUnderrun    = 0x4000,
0143    TxOwn         = 0x2000,
0144 };
0145 
0146 enum RxStatusBits {
0147    RxStatesOK   = 0x80000,
0148    RxBadAlign   = 0x40000,
0149    RxHugeFrame  = 0x20000,
0150    RxSmallFrame = 0x10000,
0151    RxCRCOK      = 0x8000,
0152    RxCrlFrame   = 0x4000,
0153    Rx_Broadcast = 0x2000,
0154    Rx_Multicast = 0x1000,
0155    RxAddrMatch  = 0x0800,
0156    MiiErr       = 0x0400,
0157 };
0158 
0159 enum RxConfigBits {
0160    RxFullDx    = 0x80000000,
0161    RxEnb       = 0x40000000,
0162    RxSmall     = 0x20000000,
0163    RxHuge      = 0x10000000,
0164    RxErr       = 0x08000000,
0165    RxAllphys   = 0x04000000,
0166    RxMulticast = 0x02000000,
0167    RxBroadcast = 0x01000000,
0168    RxLoopBack  = (1 << 23) | (1 << 22),
0169    LowThresholdShift  = 12,
0170    HighThresholdShift = 2,
0171 };
0172 
0173 enum TxConfigBits {
0174    TxFullDx       = 0x80000000,
0175    TxEnb          = 0x40000000,
0176    TxEnbPad       = 0x20000000,
0177    TxEnbHuge      = 0x10000000,
0178    TxEnbFCS       = 0x08000000,
0179    TxNoBackOff    = 0x04000000,
0180    TxEnbPrem      = 0x02000000,
0181    TxCareLostCrs  = 0x1000000,
0182    TxExdCollNum   = 0xf00000,
0183    TxDataRate     = 0x80000,
0184 };
0185 
0186 enum PhyCtrlconfigbits {
0187    PhyCtrlAne         = 0x80000000,
0188    PhyCtrlSpd100      = 0x40000000,
0189    PhyCtrlSpd10       = 0x20000000,
0190    PhyCtrlPhyBaseAddr = 0x1f000000,
0191    PhyCtrlDux         = 0x800000,
0192    PhyCtrlReset       = 0x400000,
0193 };
0194 
0195 enum FlowCtrlConfigBits {
0196    FlowCtrlFullDX = 0x80000000,
0197    FlowCtrlEnb    = 0x40000000,
0198 };
0199 
0200 enum Config0Bits {
0201    Cfg0_Reset  = 0x80000000,
0202    Cfg0_Anaoff = 0x40000000,
0203    Cfg0_LDPS   = 0x20000000,
0204 };
0205 
0206 enum Config1Bits {
0207    Cfg1_EarlyRx = 1 << 31,
0208    Cfg1_EarlyTx = 1 << 30,
0209 
0210    //rx buffer size
0211    Cfg1_Rcv8K   = 0x0,
0212    Cfg1_Rcv16K  = 0x1,
0213    Cfg1_Rcv32K  = 0x3,
0214    Cfg1_Rcv64K  = 0x7,
0215    Cfg1_Rcv128K = 0xf,
0216 };
0217 
0218 enum MiiCmd0Bits {
0219    Mii_Divider = 0x20000000,
0220    Mii_WRITE   = 0x400000,
0221    Mii_READ    = 0x200000,
0222    Mii_SCAN    = 0x100000,
0223    Mii_Tamod   = 0x80000,
0224    Mii_Drvmod  = 0x40000,
0225    Mii_mdc     = 0x20000,
0226    Mii_mdoen   = 0x10000,
0227    Mii_mdo     = 0x8000,
0228    Mii_mdi     = 0x4000,
0229 };
0230 
0231 enum MiiStatusBits {
0232     Mii_StatusBusy = 0x80000000,
0233 };
0234 
0235 enum PMConfigBits {
0236    PM_Enable  = 1 << 31,
0237    PM_LongWF  = 1 << 30,
0238    PM_Magic   = 1 << 29,
0239    PM_LANWake = 1 << 28,
0240    PM_LWPTN   = (1 << 27 | 1<< 26),
0241    PM_LinkUp  = 1 << 25,
0242    PM_WakeUp  = 1 << 24,
0243 };
0244 
0245 /* Locking rules:
0246  * priv->lock protects most of the fields of priv and most of the
0247  * hardware registers. It does not have to protect against softirqs
0248  * between sc92031_disable_interrupts and sc92031_enable_interrupts;
0249  * it also does not need to be used in ->open and ->stop while the
0250  * device interrupts are off.
0251  * Not having to protect against softirqs is very useful due to heavy
0252  * use of mdelay() at _sc92031_reset.
0253  * Functions prefixed with _sc92031_ must be called with the lock held;
0254  * functions prefixed with sc92031_ must be called without the lock held.
0255  */
0256 
0257 /* Locking rules for the interrupt:
0258  * - the interrupt and the tasklet never run at the same time
0259  * - neither run between sc92031_disable_interrupts and
0260  *   sc92031_enable_interrupt
0261  */
0262 
0263 struct sc92031_priv {
0264     spinlock_t      lock;
0265     /* iomap.h cookie */
0266     void __iomem        *port_base;
0267     /* pci device structure */
0268     struct pci_dev      *pdev;
0269     /* tasklet */
0270     struct tasklet_struct   tasklet;
0271 
0272     /* CPU address of rx ring */
0273     void            *rx_ring;
0274     /* PCI address of rx ring */
0275     dma_addr_t      rx_ring_dma_addr;
0276     /* PCI address of rx ring read pointer */
0277     dma_addr_t      rx_ring_tail;
0278 
0279     /* tx ring write index */
0280     unsigned        tx_head;
0281     /* tx ring read index */
0282     unsigned        tx_tail;
0283     /* CPU address of tx bounce buffer */
0284     void            *tx_bufs;
0285     /* PCI address of tx bounce buffer */
0286     dma_addr_t      tx_bufs_dma_addr;
0287 
0288     /* copies of some hardware registers */
0289     u32         intr_status;
0290     atomic_t        intr_mask;
0291     u32         rx_config;
0292     u32         tx_config;
0293     u32         pm_config;
0294 
0295     /* copy of some flags from dev->flags */
0296     unsigned int        mc_flags;
0297 
0298     /* for ETHTOOL_GSTATS */
0299     u64         tx_timeouts;
0300     u64         rx_loss;
0301 
0302     /* for dev->get_stats */
0303     long            rx_value;
0304     struct net_device   *ndev;
0305 };
0306 
0307 /* I don't know which registers can be safely read; however, I can guess
0308  * MAC0 is one of them. */
0309 static inline void _sc92031_dummy_read(void __iomem *port_base)
0310 {
0311     ioread32(port_base + MAC0);
0312 }
0313 
0314 static u32 _sc92031_mii_wait(void __iomem *port_base)
0315 {
0316     u32 mii_status;
0317 
0318     do {
0319         udelay(10);
0320         mii_status = ioread32(port_base + Miistatus);
0321     } while (mii_status & Mii_StatusBusy);
0322 
0323     return mii_status;
0324 }
0325 
0326 static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1)
0327 {
0328     iowrite32(Mii_Divider, port_base + Miicmd0);
0329 
0330     _sc92031_mii_wait(port_base);
0331 
0332     iowrite32(cmd1, port_base + Miicmd1);
0333     iowrite32(Mii_Divider | cmd0, port_base + Miicmd0);
0334 
0335     return _sc92031_mii_wait(port_base);
0336 }
0337 
0338 static void _sc92031_mii_scan(void __iomem *port_base)
0339 {
0340     _sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6);
0341 }
0342 
0343 static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg)
0344 {
0345     return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13;
0346 }
0347 
0348 static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val)
0349 {
0350     _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11));
0351 }
0352 
0353 static void sc92031_disable_interrupts(struct net_device *dev)
0354 {
0355     struct sc92031_priv *priv = netdev_priv(dev);
0356     void __iomem *port_base = priv->port_base;
0357 
0358     /* tell the tasklet/interrupt not to enable interrupts */
0359     atomic_set(&priv->intr_mask, 0);
0360     wmb();
0361 
0362     /* stop interrupts */
0363     iowrite32(0, port_base + IntrMask);
0364     _sc92031_dummy_read(port_base);
0365 
0366     /* wait for any concurrent interrupt/tasklet to finish */
0367     synchronize_irq(priv->pdev->irq);
0368     tasklet_disable(&priv->tasklet);
0369 }
0370 
0371 static void sc92031_enable_interrupts(struct net_device *dev)
0372 {
0373     struct sc92031_priv *priv = netdev_priv(dev);
0374     void __iomem *port_base = priv->port_base;
0375 
0376     tasklet_enable(&priv->tasklet);
0377 
0378     atomic_set(&priv->intr_mask, IntrBits);
0379     wmb();
0380 
0381     iowrite32(IntrBits, port_base + IntrMask);
0382 }
0383 
0384 static void _sc92031_disable_tx_rx(struct net_device *dev)
0385 {
0386     struct sc92031_priv *priv = netdev_priv(dev);
0387     void __iomem *port_base = priv->port_base;
0388 
0389     priv->rx_config &= ~RxEnb;
0390     priv->tx_config &= ~TxEnb;
0391     iowrite32(priv->rx_config, port_base + RxConfig);
0392     iowrite32(priv->tx_config, port_base + TxConfig);
0393 }
0394 
0395 static void _sc92031_enable_tx_rx(struct net_device *dev)
0396 {
0397     struct sc92031_priv *priv = netdev_priv(dev);
0398     void __iomem *port_base = priv->port_base;
0399 
0400     priv->rx_config |= RxEnb;
0401     priv->tx_config |= TxEnb;
0402     iowrite32(priv->rx_config, port_base + RxConfig);
0403     iowrite32(priv->tx_config, port_base + TxConfig);
0404 }
0405 
0406 static void _sc92031_tx_clear(struct net_device *dev)
0407 {
0408     struct sc92031_priv *priv = netdev_priv(dev);
0409 
0410     while (priv->tx_head - priv->tx_tail > 0) {
0411         priv->tx_tail++;
0412         dev->stats.tx_dropped++;
0413     }
0414     priv->tx_head = priv->tx_tail = 0;
0415 }
0416 
0417 static void _sc92031_set_mar(struct net_device *dev)
0418 {
0419     struct sc92031_priv *priv = netdev_priv(dev);
0420     void __iomem *port_base = priv->port_base;
0421     u32 mar0 = 0, mar1 = 0;
0422 
0423     if ((dev->flags & IFF_PROMISC) ||
0424         netdev_mc_count(dev) > multicast_filter_limit ||
0425         (dev->flags & IFF_ALLMULTI))
0426         mar0 = mar1 = 0xffffffff;
0427     else if (dev->flags & IFF_MULTICAST) {
0428         struct netdev_hw_addr *ha;
0429 
0430         netdev_for_each_mc_addr(ha, dev) {
0431             u32 crc;
0432             unsigned bit = 0;
0433 
0434             crc = ~ether_crc(ETH_ALEN, ha->addr);
0435             crc >>= 24;
0436 
0437             if (crc & 0x01) bit |= 0x02;
0438             if (crc & 0x02) bit |= 0x01;
0439             if (crc & 0x10) bit |= 0x20;
0440             if (crc & 0x20) bit |= 0x10;
0441             if (crc & 0x40) bit |= 0x08;
0442             if (crc & 0x80) bit |= 0x04;
0443 
0444             if (bit > 31)
0445                 mar0 |= 0x1 << (bit - 32);
0446             else
0447                 mar1 |= 0x1 << bit;
0448         }
0449     }
0450 
0451     iowrite32(mar0, port_base + MAR0);
0452     iowrite32(mar1, port_base + MAR0 + 4);
0453 }
0454 
0455 static void _sc92031_set_rx_config(struct net_device *dev)
0456 {
0457     struct sc92031_priv *priv = netdev_priv(dev);
0458     void __iomem *port_base = priv->port_base;
0459     unsigned int old_mc_flags;
0460     u32 rx_config_bits = 0;
0461 
0462     old_mc_flags = priv->mc_flags;
0463 
0464     if (dev->flags & IFF_PROMISC)
0465         rx_config_bits |= RxSmall | RxHuge | RxErr | RxBroadcast
0466                 | RxMulticast | RxAllphys;
0467 
0468     if (dev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
0469         rx_config_bits |= RxMulticast;
0470 
0471     if (dev->flags & IFF_BROADCAST)
0472         rx_config_bits |= RxBroadcast;
0473 
0474     priv->rx_config &= ~(RxSmall | RxHuge | RxErr | RxBroadcast
0475             | RxMulticast | RxAllphys);
0476     priv->rx_config |= rx_config_bits;
0477 
0478     priv->mc_flags = dev->flags & (IFF_PROMISC | IFF_ALLMULTI
0479             | IFF_MULTICAST | IFF_BROADCAST);
0480 
0481     if (netif_carrier_ok(dev) && priv->mc_flags != old_mc_flags)
0482         iowrite32(priv->rx_config, port_base + RxConfig);
0483 }
0484 
0485 static bool _sc92031_check_media(struct net_device *dev)
0486 {
0487     struct sc92031_priv *priv = netdev_priv(dev);
0488     void __iomem *port_base = priv->port_base;
0489     u16 bmsr;
0490 
0491     bmsr = _sc92031_mii_read(port_base, MII_BMSR);
0492     rmb();
0493     if (bmsr & BMSR_LSTATUS) {
0494         bool speed_100, duplex_full;
0495         u32 flow_ctrl_config = 0;
0496         u16 output_status = _sc92031_mii_read(port_base,
0497                 MII_OutputStatus);
0498         _sc92031_mii_scan(port_base);
0499 
0500         speed_100 = output_status & 0x2;
0501         duplex_full = output_status & 0x4;
0502 
0503         /* Initial Tx/Rx configuration */
0504         priv->rx_config = (0x40 << LowThresholdShift) | (0x1c0 << HighThresholdShift);
0505         priv->tx_config = 0x48800000;
0506 
0507         /* NOTE: vendor driver had dead code here to enable tx padding */
0508 
0509         if (!speed_100)
0510             priv->tx_config |= 0x80000;
0511 
0512         // configure rx mode
0513         _sc92031_set_rx_config(dev);
0514 
0515         if (duplex_full) {
0516             priv->rx_config |= RxFullDx;
0517             priv->tx_config |= TxFullDx;
0518             flow_ctrl_config = FlowCtrlFullDX | FlowCtrlEnb;
0519         } else {
0520             priv->rx_config &= ~RxFullDx;
0521             priv->tx_config &= ~TxFullDx;
0522         }
0523 
0524         _sc92031_set_mar(dev);
0525         _sc92031_set_rx_config(dev);
0526         _sc92031_enable_tx_rx(dev);
0527         iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig);
0528 
0529         netif_carrier_on(dev);
0530 
0531         if (printk_ratelimit())
0532             printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n",
0533                 dev->name,
0534                 speed_100 ? "100" : "10",
0535                 duplex_full ? "full" : "half");
0536         return true;
0537     } else {
0538         _sc92031_mii_scan(port_base);
0539 
0540         netif_carrier_off(dev);
0541 
0542         _sc92031_disable_tx_rx(dev);
0543 
0544         if (printk_ratelimit())
0545             printk(KERN_INFO "%s: link down\n", dev->name);
0546         return false;
0547     }
0548 }
0549 
0550 static void _sc92031_phy_reset(struct net_device *dev)
0551 {
0552     struct sc92031_priv *priv = netdev_priv(dev);
0553     void __iomem *port_base = priv->port_base;
0554     u32 phy_ctrl;
0555 
0556     phy_ctrl = ioread32(port_base + PhyCtrl);
0557     phy_ctrl &= ~(PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10);
0558     phy_ctrl |= PhyCtrlAne | PhyCtrlReset;
0559 
0560     switch (media) {
0561     default:
0562     case AUTOSELECT:
0563         phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
0564         break;
0565     case M10_HALF:
0566         phy_ctrl |= PhyCtrlSpd10;
0567         break;
0568     case M10_FULL:
0569         phy_ctrl |= PhyCtrlDux | PhyCtrlSpd10;
0570         break;
0571     case M100_HALF:
0572         phy_ctrl |= PhyCtrlSpd100;
0573         break;
0574     case M100_FULL:
0575         phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
0576         break;
0577     }
0578 
0579     iowrite32(phy_ctrl, port_base + PhyCtrl);
0580     mdelay(10);
0581 
0582     phy_ctrl &= ~PhyCtrlReset;
0583     iowrite32(phy_ctrl, port_base + PhyCtrl);
0584     mdelay(1);
0585 
0586     _sc92031_mii_write(port_base, MII_JAB,
0587             PHY_16_JAB_ENB | PHY_16_PORT_ENB);
0588     _sc92031_mii_scan(port_base);
0589 
0590     netif_carrier_off(dev);
0591     netif_stop_queue(dev);
0592 }
0593 
0594 static void _sc92031_reset(struct net_device *dev)
0595 {
0596     struct sc92031_priv *priv = netdev_priv(dev);
0597     void __iomem *port_base = priv->port_base;
0598 
0599     /* disable PM */
0600     iowrite32(0, port_base + PMConfig);
0601 
0602     /* soft reset the chip */
0603     iowrite32(Cfg0_Reset, port_base + Config0);
0604     mdelay(200);
0605 
0606     iowrite32(0, port_base + Config0);
0607     mdelay(10);
0608 
0609     /* disable interrupts */
0610     iowrite32(0, port_base + IntrMask);
0611 
0612     /* clear multicast address */
0613     iowrite32(0, port_base + MAR0);
0614     iowrite32(0, port_base + MAR0 + 4);
0615 
0616     /* init rx ring */
0617     iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr);
0618     priv->rx_ring_tail = priv->rx_ring_dma_addr;
0619 
0620     /* init tx ring */
0621     _sc92031_tx_clear(dev);
0622 
0623     /* clear old register values */
0624     priv->intr_status = 0;
0625     atomic_set(&priv->intr_mask, 0);
0626     priv->rx_config = 0;
0627     priv->tx_config = 0;
0628     priv->mc_flags = 0;
0629 
0630     /* configure rx buffer size */
0631     /* NOTE: vendor driver had dead code here to enable early tx/rx */
0632     iowrite32(Cfg1_Rcv64K, port_base + Config1);
0633 
0634     _sc92031_phy_reset(dev);
0635     _sc92031_check_media(dev);
0636 
0637     /* calculate rx fifo overflow */
0638     priv->rx_value = 0;
0639 
0640     /* enable PM */
0641     iowrite32(priv->pm_config, port_base + PMConfig);
0642 
0643     /* clear intr register */
0644     ioread32(port_base + IntrStatus);
0645 }
0646 
0647 static void _sc92031_tx_tasklet(struct net_device *dev)
0648 {
0649     struct sc92031_priv *priv = netdev_priv(dev);
0650     void __iomem *port_base = priv->port_base;
0651 
0652     unsigned old_tx_tail;
0653     unsigned entry;
0654     u32 tx_status;
0655 
0656     old_tx_tail = priv->tx_tail;
0657     while (priv->tx_head - priv->tx_tail > 0) {
0658         entry = priv->tx_tail % NUM_TX_DESC;
0659         tx_status = ioread32(port_base + TxStatus0 + entry * 4);
0660 
0661         if (!(tx_status & (TxStatOK | TxUnderrun | TxAborted)))
0662             break;
0663 
0664         priv->tx_tail++;
0665 
0666         if (tx_status & TxStatOK) {
0667             dev->stats.tx_bytes += tx_status & 0x1fff;
0668             dev->stats.tx_packets++;
0669             /* Note: TxCarrierLost is always asserted at 100mbps. */
0670             dev->stats.collisions += (tx_status >> 22) & 0xf;
0671         }
0672 
0673         if (tx_status & (TxOutOfWindow | TxAborted)) {
0674             dev->stats.tx_errors++;
0675 
0676             if (tx_status & TxAborted)
0677                 dev->stats.tx_aborted_errors++;
0678 
0679             if (tx_status & TxCarrierLost)
0680                 dev->stats.tx_carrier_errors++;
0681 
0682             if (tx_status & TxOutOfWindow)
0683                 dev->stats.tx_window_errors++;
0684         }
0685 
0686         if (tx_status & TxUnderrun)
0687             dev->stats.tx_fifo_errors++;
0688     }
0689 
0690     if (priv->tx_tail != old_tx_tail)
0691         if (netif_queue_stopped(dev))
0692             netif_wake_queue(dev);
0693 }
0694 
0695 static void _sc92031_rx_tasklet_error(struct net_device *dev,
0696                       u32 rx_status, unsigned rx_size)
0697 {
0698     if(rx_size > (MAX_ETH_FRAME_SIZE + 4) || rx_size < 16) {
0699         dev->stats.rx_errors++;
0700         dev->stats.rx_length_errors++;
0701     }
0702 
0703     if (!(rx_status & RxStatesOK)) {
0704         dev->stats.rx_errors++;
0705 
0706         if (rx_status & (RxHugeFrame | RxSmallFrame))
0707             dev->stats.rx_length_errors++;
0708 
0709         if (rx_status & RxBadAlign)
0710             dev->stats.rx_frame_errors++;
0711 
0712         if (!(rx_status & RxCRCOK))
0713             dev->stats.rx_crc_errors++;
0714     } else {
0715         struct sc92031_priv *priv = netdev_priv(dev);
0716         priv->rx_loss++;
0717     }
0718 }
0719 
0720 static void _sc92031_rx_tasklet(struct net_device *dev)
0721 {
0722     struct sc92031_priv *priv = netdev_priv(dev);
0723     void __iomem *port_base = priv->port_base;
0724 
0725     dma_addr_t rx_ring_head;
0726     unsigned rx_len;
0727     unsigned rx_ring_offset;
0728     void *rx_ring = priv->rx_ring;
0729 
0730     rx_ring_head = ioread32(port_base + RxBufWPtr);
0731     rmb();
0732 
0733     /* rx_ring_head is only 17 bits in the RxBufWPtr register.
0734      * we need to change it to 32 bits physical address
0735      */
0736     rx_ring_head &= (dma_addr_t)(RX_BUF_LEN - 1);
0737     rx_ring_head |= priv->rx_ring_dma_addr & ~(dma_addr_t)(RX_BUF_LEN - 1);
0738     if (rx_ring_head < priv->rx_ring_dma_addr)
0739         rx_ring_head += RX_BUF_LEN;
0740 
0741     if (rx_ring_head >= priv->rx_ring_tail)
0742         rx_len = rx_ring_head - priv->rx_ring_tail;
0743     else
0744         rx_len = RX_BUF_LEN - (priv->rx_ring_tail - rx_ring_head);
0745 
0746     if (!rx_len)
0747         return;
0748 
0749     if (unlikely(rx_len > RX_BUF_LEN)) {
0750         if (printk_ratelimit())
0751             printk(KERN_ERR "%s: rx packets length > rx buffer\n",
0752                     dev->name);
0753         return;
0754     }
0755 
0756     rx_ring_offset = (priv->rx_ring_tail - priv->rx_ring_dma_addr) % RX_BUF_LEN;
0757 
0758     while (rx_len) {
0759         u32 rx_status;
0760         unsigned rx_size, rx_size_align, pkt_size;
0761         struct sk_buff *skb;
0762 
0763         rx_status = le32_to_cpup((__le32 *)(rx_ring + rx_ring_offset));
0764         rmb();
0765 
0766         rx_size = rx_status >> 20;
0767         rx_size_align = (rx_size + 3) & ~3; // for 4 bytes aligned
0768         pkt_size = rx_size - 4; // Omit the four octet CRC from the length.
0769 
0770         rx_ring_offset = (rx_ring_offset + 4) % RX_BUF_LEN;
0771 
0772         if (unlikely(rx_status == 0 ||
0773                  rx_size > (MAX_ETH_FRAME_SIZE + 4) ||
0774                  rx_size < 16 ||
0775                  !(rx_status & RxStatesOK))) {
0776             _sc92031_rx_tasklet_error(dev, rx_status, rx_size);
0777             break;
0778         }
0779 
0780         if (unlikely(rx_size_align + 4 > rx_len)) {
0781             if (printk_ratelimit())
0782                 printk(KERN_ERR "%s: rx_len is too small\n", dev->name);
0783             break;
0784         }
0785 
0786         rx_len -= rx_size_align + 4;
0787 
0788         skb = netdev_alloc_skb_ip_align(dev, pkt_size);
0789         if (unlikely(!skb)) {
0790             if (printk_ratelimit())
0791                 printk(KERN_ERR "%s: Couldn't allocate a skb_buff for a packet of size %u\n",
0792                         dev->name, pkt_size);
0793             goto next;
0794         }
0795 
0796         if ((rx_ring_offset + pkt_size) > RX_BUF_LEN) {
0797             skb_put_data(skb, rx_ring + rx_ring_offset,
0798                      RX_BUF_LEN - rx_ring_offset);
0799             skb_put_data(skb, rx_ring,
0800                      pkt_size - (RX_BUF_LEN - rx_ring_offset));
0801         } else {
0802             skb_put_data(skb, rx_ring + rx_ring_offset, pkt_size);
0803         }
0804 
0805         skb->protocol = eth_type_trans(skb, dev);
0806         netif_rx(skb);
0807 
0808         dev->stats.rx_bytes += pkt_size;
0809         dev->stats.rx_packets++;
0810 
0811         if (rx_status & Rx_Multicast)
0812             dev->stats.multicast++;
0813 
0814     next:
0815         rx_ring_offset = (rx_ring_offset + rx_size_align) % RX_BUF_LEN;
0816     }
0817     mb();
0818 
0819     priv->rx_ring_tail = rx_ring_head;
0820     iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr);
0821 }
0822 
0823 static void _sc92031_link_tasklet(struct net_device *dev)
0824 {
0825     if (_sc92031_check_media(dev))
0826         netif_wake_queue(dev);
0827     else {
0828         netif_stop_queue(dev);
0829         dev->stats.tx_carrier_errors++;
0830     }
0831 }
0832 
0833 static void sc92031_tasklet(struct tasklet_struct *t)
0834 {
0835     struct  sc92031_priv *priv = from_tasklet(priv, t, tasklet);
0836     struct net_device *dev = priv->ndev;
0837     void __iomem *port_base = priv->port_base;
0838     u32 intr_status, intr_mask;
0839 
0840     intr_status = priv->intr_status;
0841 
0842     spin_lock(&priv->lock);
0843 
0844     if (unlikely(!netif_running(dev)))
0845         goto out;
0846 
0847     if (intr_status & TxOK)
0848         _sc92031_tx_tasklet(dev);
0849 
0850     if (intr_status & RxOK)
0851         _sc92031_rx_tasklet(dev);
0852 
0853     if (intr_status & RxOverflow)
0854         dev->stats.rx_errors++;
0855 
0856     if (intr_status & TimeOut) {
0857         dev->stats.rx_errors++;
0858         dev->stats.rx_length_errors++;
0859     }
0860 
0861     if (intr_status & (LinkFail | LinkOK))
0862         _sc92031_link_tasklet(dev);
0863 
0864 out:
0865     intr_mask = atomic_read(&priv->intr_mask);
0866     rmb();
0867 
0868     iowrite32(intr_mask, port_base + IntrMask);
0869 
0870     spin_unlock(&priv->lock);
0871 }
0872 
0873 static irqreturn_t sc92031_interrupt(int irq, void *dev_id)
0874 {
0875     struct net_device *dev = dev_id;
0876     struct sc92031_priv *priv = netdev_priv(dev);
0877     void __iomem *port_base = priv->port_base;
0878     u32 intr_status, intr_mask;
0879 
0880     /* mask interrupts before clearing IntrStatus */
0881     iowrite32(0, port_base + IntrMask);
0882     _sc92031_dummy_read(port_base);
0883 
0884     intr_status = ioread32(port_base + IntrStatus);
0885     if (unlikely(intr_status == 0xffffffff))
0886         return IRQ_NONE;    // hardware has gone missing
0887 
0888     intr_status &= IntrBits;
0889     if (!intr_status)
0890         goto out_none;
0891 
0892     priv->intr_status = intr_status;
0893     tasklet_schedule(&priv->tasklet);
0894 
0895     return IRQ_HANDLED;
0896 
0897 out_none:
0898     intr_mask = atomic_read(&priv->intr_mask);
0899     rmb();
0900 
0901     iowrite32(intr_mask, port_base + IntrMask);
0902 
0903     return IRQ_NONE;
0904 }
0905 
0906 static struct net_device_stats *sc92031_get_stats(struct net_device *dev)
0907 {
0908     struct sc92031_priv *priv = netdev_priv(dev);
0909     void __iomem *port_base = priv->port_base;
0910 
0911     // FIXME I do not understand what is this trying to do.
0912     if (netif_running(dev)) {
0913         int temp;
0914 
0915         spin_lock_bh(&priv->lock);
0916 
0917         /* Update the error count. */
0918         temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff;
0919 
0920         if (temp == 0xffff) {
0921             priv->rx_value += temp;
0922             dev->stats.rx_fifo_errors = priv->rx_value;
0923         } else
0924             dev->stats.rx_fifo_errors = temp + priv->rx_value;
0925 
0926         spin_unlock_bh(&priv->lock);
0927     }
0928 
0929     return &dev->stats;
0930 }
0931 
0932 static netdev_tx_t sc92031_start_xmit(struct sk_buff *skb,
0933                       struct net_device *dev)
0934 {
0935     struct sc92031_priv *priv = netdev_priv(dev);
0936     void __iomem *port_base = priv->port_base;
0937     unsigned len;
0938     unsigned entry;
0939     u32 tx_status;
0940 
0941     if (unlikely(skb->len > TX_BUF_SIZE)) {
0942         dev->stats.tx_dropped++;
0943         goto out;
0944     }
0945 
0946     spin_lock(&priv->lock);
0947 
0948     if (unlikely(!netif_carrier_ok(dev))) {
0949         dev->stats.tx_dropped++;
0950         goto out_unlock;
0951     }
0952 
0953     BUG_ON(priv->tx_head - priv->tx_tail >= NUM_TX_DESC);
0954 
0955     entry = priv->tx_head++ % NUM_TX_DESC;
0956 
0957     skb_copy_and_csum_dev(skb, priv->tx_bufs + entry * TX_BUF_SIZE);
0958 
0959     len = skb->len;
0960     if (len < ETH_ZLEN) {
0961         memset(priv->tx_bufs + entry * TX_BUF_SIZE + len,
0962                 0, ETH_ZLEN - len);
0963         len = ETH_ZLEN;
0964     }
0965 
0966     wmb();
0967 
0968     if (len < 100)
0969         tx_status = len;
0970     else if (len < 300)
0971         tx_status = 0x30000 | len;
0972     else
0973         tx_status = 0x50000 | len;
0974 
0975     iowrite32(priv->tx_bufs_dma_addr + entry * TX_BUF_SIZE,
0976             port_base + TxAddr0 + entry * 4);
0977     iowrite32(tx_status, port_base + TxStatus0 + entry * 4);
0978 
0979     if (priv->tx_head - priv->tx_tail >= NUM_TX_DESC)
0980         netif_stop_queue(dev);
0981 
0982 out_unlock:
0983     spin_unlock(&priv->lock);
0984 
0985 out:
0986     dev_consume_skb_any(skb);
0987 
0988     return NETDEV_TX_OK;
0989 }
0990 
0991 static int sc92031_open(struct net_device *dev)
0992 {
0993     int err;
0994     struct sc92031_priv *priv = netdev_priv(dev);
0995     struct pci_dev *pdev = priv->pdev;
0996 
0997     priv->rx_ring = dma_alloc_coherent(&pdev->dev, RX_BUF_LEN,
0998                        &priv->rx_ring_dma_addr, GFP_KERNEL);
0999     if (unlikely(!priv->rx_ring)) {
1000         err = -ENOMEM;
1001         goto out_alloc_rx_ring;
1002     }
1003 
1004     priv->tx_bufs = dma_alloc_coherent(&pdev->dev, TX_BUF_TOT_LEN,
1005                        &priv->tx_bufs_dma_addr, GFP_KERNEL);
1006     if (unlikely(!priv->tx_bufs)) {
1007         err = -ENOMEM;
1008         goto out_alloc_tx_bufs;
1009     }
1010     priv->tx_head = priv->tx_tail = 0;
1011 
1012     err = request_irq(pdev->irq, sc92031_interrupt,
1013             IRQF_SHARED, dev->name, dev);
1014     if (unlikely(err < 0))
1015         goto out_request_irq;
1016 
1017     priv->pm_config = 0;
1018 
1019     /* Interrupts already disabled by sc92031_stop or sc92031_probe */
1020     spin_lock_bh(&priv->lock);
1021 
1022     _sc92031_reset(dev);
1023 
1024     spin_unlock_bh(&priv->lock);
1025     sc92031_enable_interrupts(dev);
1026 
1027     if (netif_carrier_ok(dev))
1028         netif_start_queue(dev);
1029     else
1030         netif_tx_disable(dev);
1031 
1032     return 0;
1033 
1034 out_request_irq:
1035     dma_free_coherent(&pdev->dev, TX_BUF_TOT_LEN, priv->tx_bufs,
1036               priv->tx_bufs_dma_addr);
1037 out_alloc_tx_bufs:
1038     dma_free_coherent(&pdev->dev, RX_BUF_LEN, priv->rx_ring,
1039               priv->rx_ring_dma_addr);
1040 out_alloc_rx_ring:
1041     return err;
1042 }
1043 
1044 static int sc92031_stop(struct net_device *dev)
1045 {
1046     struct sc92031_priv *priv = netdev_priv(dev);
1047     struct pci_dev *pdev = priv->pdev;
1048 
1049     netif_tx_disable(dev);
1050 
1051     /* Disable interrupts, stop Tx and Rx. */
1052     sc92031_disable_interrupts(dev);
1053 
1054     spin_lock_bh(&priv->lock);
1055 
1056     _sc92031_disable_tx_rx(dev);
1057     _sc92031_tx_clear(dev);
1058 
1059     spin_unlock_bh(&priv->lock);
1060 
1061     free_irq(pdev->irq, dev);
1062     dma_free_coherent(&pdev->dev, TX_BUF_TOT_LEN, priv->tx_bufs,
1063               priv->tx_bufs_dma_addr);
1064     dma_free_coherent(&pdev->dev, RX_BUF_LEN, priv->rx_ring,
1065               priv->rx_ring_dma_addr);
1066 
1067     return 0;
1068 }
1069 
1070 static void sc92031_set_multicast_list(struct net_device *dev)
1071 {
1072     struct sc92031_priv *priv = netdev_priv(dev);
1073 
1074     spin_lock_bh(&priv->lock);
1075 
1076     _sc92031_set_mar(dev);
1077     _sc92031_set_rx_config(dev);
1078 
1079     spin_unlock_bh(&priv->lock);
1080 }
1081 
1082 static void sc92031_tx_timeout(struct net_device *dev, unsigned int txqueue)
1083 {
1084     struct sc92031_priv *priv = netdev_priv(dev);
1085 
1086     /* Disable interrupts by clearing the interrupt mask.*/
1087     sc92031_disable_interrupts(dev);
1088 
1089     spin_lock(&priv->lock);
1090 
1091     priv->tx_timeouts++;
1092 
1093     _sc92031_reset(dev);
1094 
1095     spin_unlock(&priv->lock);
1096 
1097     /* enable interrupts */
1098     sc92031_enable_interrupts(dev);
1099 
1100     if (netif_carrier_ok(dev))
1101         netif_wake_queue(dev);
1102 }
1103 
1104 #ifdef CONFIG_NET_POLL_CONTROLLER
1105 static void sc92031_poll_controller(struct net_device *dev)
1106 {
1107     struct sc92031_priv *priv = netdev_priv(dev);
1108     const int irq = priv->pdev->irq;
1109 
1110     disable_irq(irq);
1111     if (sc92031_interrupt(irq, dev) != IRQ_NONE)
1112         sc92031_tasklet(&priv->tasklet);
1113     enable_irq(irq);
1114 }
1115 #endif
1116 
1117 static int
1118 sc92031_ethtool_get_link_ksettings(struct net_device *dev,
1119                    struct ethtool_link_ksettings *cmd)
1120 {
1121     struct sc92031_priv *priv = netdev_priv(dev);
1122     void __iomem *port_base = priv->port_base;
1123     u8 phy_address;
1124     u32 phy_ctrl;
1125     u16 output_status;
1126     u32 supported, advertising;
1127 
1128     spin_lock_bh(&priv->lock);
1129 
1130     phy_address = ioread32(port_base + Miicmd1) >> 27;
1131     phy_ctrl = ioread32(port_base + PhyCtrl);
1132 
1133     output_status = _sc92031_mii_read(port_base, MII_OutputStatus);
1134     _sc92031_mii_scan(port_base);
1135 
1136     spin_unlock_bh(&priv->lock);
1137 
1138     supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
1139             | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
1140             | SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII;
1141 
1142     advertising = ADVERTISED_TP | ADVERTISED_MII;
1143 
1144     if ((phy_ctrl & (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1145             == (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1146         advertising |= ADVERTISED_Autoneg;
1147 
1148     if ((phy_ctrl & PhyCtrlSpd10) == PhyCtrlSpd10)
1149         advertising |= ADVERTISED_10baseT_Half;
1150 
1151     if ((phy_ctrl & (PhyCtrlSpd10 | PhyCtrlDux))
1152             == (PhyCtrlSpd10 | PhyCtrlDux))
1153         advertising |= ADVERTISED_10baseT_Full;
1154 
1155     if ((phy_ctrl & PhyCtrlSpd100) == PhyCtrlSpd100)
1156         advertising |= ADVERTISED_100baseT_Half;
1157 
1158     if ((phy_ctrl & (PhyCtrlSpd100 | PhyCtrlDux))
1159             == (PhyCtrlSpd100 | PhyCtrlDux))
1160         advertising |= ADVERTISED_100baseT_Full;
1161 
1162     if (phy_ctrl & PhyCtrlAne)
1163         advertising |= ADVERTISED_Autoneg;
1164 
1165     cmd->base.speed = (output_status & 0x2) ? SPEED_100 : SPEED_10;
1166     cmd->base.duplex = (output_status & 0x4) ? DUPLEX_FULL : DUPLEX_HALF;
1167     cmd->base.port = PORT_MII;
1168     cmd->base.phy_address = phy_address;
1169     cmd->base.autoneg = (phy_ctrl & PhyCtrlAne) ?
1170         AUTONEG_ENABLE : AUTONEG_DISABLE;
1171 
1172     ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1173                         supported);
1174     ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1175                         advertising);
1176 
1177     return 0;
1178 }
1179 
1180 static int
1181 sc92031_ethtool_set_link_ksettings(struct net_device *dev,
1182                    const struct ethtool_link_ksettings *cmd)
1183 {
1184     struct sc92031_priv *priv = netdev_priv(dev);
1185     void __iomem *port_base = priv->port_base;
1186     u32 speed = cmd->base.speed;
1187     u32 phy_ctrl;
1188     u32 old_phy_ctrl;
1189     u32 advertising;
1190 
1191     ethtool_convert_link_mode_to_legacy_u32(&advertising,
1192                         cmd->link_modes.advertising);
1193 
1194     if (!(speed == SPEED_10 || speed == SPEED_100))
1195         return -EINVAL;
1196     if (!(cmd->base.duplex == DUPLEX_HALF ||
1197           cmd->base.duplex == DUPLEX_FULL))
1198         return -EINVAL;
1199     if (!(cmd->base.port == PORT_MII))
1200         return -EINVAL;
1201     if (!(cmd->base.phy_address == 0x1f))
1202         return -EINVAL;
1203     if (!(cmd->base.autoneg == AUTONEG_DISABLE ||
1204           cmd->base.autoneg == AUTONEG_ENABLE))
1205         return -EINVAL;
1206 
1207     if (cmd->base.autoneg == AUTONEG_ENABLE) {
1208         if (!(advertising & (ADVERTISED_Autoneg
1209                 | ADVERTISED_100baseT_Full
1210                 | ADVERTISED_100baseT_Half
1211                 | ADVERTISED_10baseT_Full
1212                 | ADVERTISED_10baseT_Half)))
1213             return -EINVAL;
1214 
1215         phy_ctrl = PhyCtrlAne;
1216 
1217         // FIXME: I'm not sure what the original code was trying to do
1218         if (advertising & ADVERTISED_Autoneg)
1219             phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
1220         if (advertising & ADVERTISED_100baseT_Full)
1221             phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
1222         if (advertising & ADVERTISED_100baseT_Half)
1223             phy_ctrl |= PhyCtrlSpd100;
1224         if (advertising & ADVERTISED_10baseT_Full)
1225             phy_ctrl |= PhyCtrlSpd10 | PhyCtrlDux;
1226         if (advertising & ADVERTISED_10baseT_Half)
1227             phy_ctrl |= PhyCtrlSpd10;
1228     } else {
1229         // FIXME: Whole branch guessed
1230         phy_ctrl = 0;
1231 
1232         if (speed == SPEED_10)
1233             phy_ctrl |= PhyCtrlSpd10;
1234         else /* cmd->speed == SPEED_100 */
1235             phy_ctrl |= PhyCtrlSpd100;
1236 
1237         if (cmd->base.duplex == DUPLEX_FULL)
1238             phy_ctrl |= PhyCtrlDux;
1239     }
1240 
1241     spin_lock_bh(&priv->lock);
1242 
1243     old_phy_ctrl = ioread32(port_base + PhyCtrl);
1244     phy_ctrl |= old_phy_ctrl & ~(PhyCtrlAne | PhyCtrlDux
1245             | PhyCtrlSpd100 | PhyCtrlSpd10);
1246     if (phy_ctrl != old_phy_ctrl)
1247         iowrite32(phy_ctrl, port_base + PhyCtrl);
1248 
1249     spin_unlock_bh(&priv->lock);
1250 
1251     return 0;
1252 }
1253 
1254 static void sc92031_ethtool_get_wol(struct net_device *dev,
1255         struct ethtool_wolinfo *wolinfo)
1256 {
1257     struct sc92031_priv *priv = netdev_priv(dev);
1258     void __iomem *port_base = priv->port_base;
1259     u32 pm_config;
1260 
1261     spin_lock_bh(&priv->lock);
1262     pm_config = ioread32(port_base + PMConfig);
1263     spin_unlock_bh(&priv->lock);
1264 
1265     // FIXME: Guessed
1266     wolinfo->supported = WAKE_PHY | WAKE_MAGIC
1267             | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1268     wolinfo->wolopts = 0;
1269 
1270     if (pm_config & PM_LinkUp)
1271         wolinfo->wolopts |= WAKE_PHY;
1272 
1273     if (pm_config & PM_Magic)
1274         wolinfo->wolopts |= WAKE_MAGIC;
1275 
1276     if (pm_config & PM_WakeUp)
1277         // FIXME: Guessed
1278         wolinfo->wolopts |= WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1279 }
1280 
1281 static int sc92031_ethtool_set_wol(struct net_device *dev,
1282         struct ethtool_wolinfo *wolinfo)
1283 {
1284     struct sc92031_priv *priv = netdev_priv(dev);
1285     void __iomem *port_base = priv->port_base;
1286     u32 pm_config;
1287 
1288     spin_lock_bh(&priv->lock);
1289 
1290     pm_config = ioread32(port_base + PMConfig)
1291             & ~(PM_LinkUp | PM_Magic | PM_WakeUp);
1292 
1293     if (wolinfo->wolopts & WAKE_PHY)
1294         pm_config |= PM_LinkUp;
1295 
1296     if (wolinfo->wolopts & WAKE_MAGIC)
1297         pm_config |= PM_Magic;
1298 
1299     // FIXME: Guessed
1300     if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST))
1301         pm_config |= PM_WakeUp;
1302 
1303     priv->pm_config = pm_config;
1304     iowrite32(pm_config, port_base + PMConfig);
1305 
1306     spin_unlock_bh(&priv->lock);
1307 
1308     return 0;
1309 }
1310 
1311 static int sc92031_ethtool_nway_reset(struct net_device *dev)
1312 {
1313     int err = 0;
1314     struct sc92031_priv *priv = netdev_priv(dev);
1315     void __iomem *port_base = priv->port_base;
1316     u16 bmcr;
1317 
1318     spin_lock_bh(&priv->lock);
1319 
1320     bmcr = _sc92031_mii_read(port_base, MII_BMCR);
1321     if (!(bmcr & BMCR_ANENABLE)) {
1322         err = -EINVAL;
1323         goto out;
1324     }
1325 
1326     _sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);
1327 
1328 out:
1329     _sc92031_mii_scan(port_base);
1330 
1331     spin_unlock_bh(&priv->lock);
1332 
1333     return err;
1334 }
1335 
1336 static const char sc92031_ethtool_stats_strings[SILAN_STATS_NUM][ETH_GSTRING_LEN] = {
1337     "tx_timeout",
1338     "rx_loss",
1339 };
1340 
1341 static void sc92031_ethtool_get_strings(struct net_device *dev,
1342         u32 stringset, u8 *data)
1343 {
1344     if (stringset == ETH_SS_STATS)
1345         memcpy(data, sc92031_ethtool_stats_strings,
1346                 SILAN_STATS_NUM * ETH_GSTRING_LEN);
1347 }
1348 
1349 static int sc92031_ethtool_get_sset_count(struct net_device *dev, int sset)
1350 {
1351     switch (sset) {
1352     case ETH_SS_STATS:
1353         return SILAN_STATS_NUM;
1354     default:
1355         return -EOPNOTSUPP;
1356     }
1357 }
1358 
1359 static void sc92031_ethtool_get_ethtool_stats(struct net_device *dev,
1360         struct ethtool_stats *stats, u64 *data)
1361 {
1362     struct sc92031_priv *priv = netdev_priv(dev);
1363 
1364     spin_lock_bh(&priv->lock);
1365     data[0] = priv->tx_timeouts;
1366     data[1] = priv->rx_loss;
1367     spin_unlock_bh(&priv->lock);
1368 }
1369 
1370 static const struct ethtool_ops sc92031_ethtool_ops = {
1371     .get_wol        = sc92031_ethtool_get_wol,
1372     .set_wol        = sc92031_ethtool_set_wol,
1373     .nway_reset     = sc92031_ethtool_nway_reset,
1374     .get_link       = ethtool_op_get_link,
1375     .get_strings        = sc92031_ethtool_get_strings,
1376     .get_sset_count     = sc92031_ethtool_get_sset_count,
1377     .get_ethtool_stats  = sc92031_ethtool_get_ethtool_stats,
1378     .get_link_ksettings = sc92031_ethtool_get_link_ksettings,
1379     .set_link_ksettings = sc92031_ethtool_set_link_ksettings,
1380 };
1381 
1382 
1383 static const struct net_device_ops sc92031_netdev_ops = {
1384     .ndo_get_stats      = sc92031_get_stats,
1385     .ndo_start_xmit     = sc92031_start_xmit,
1386     .ndo_open       = sc92031_open,
1387     .ndo_stop       = sc92031_stop,
1388     .ndo_set_rx_mode    = sc92031_set_multicast_list,
1389     .ndo_validate_addr  = eth_validate_addr,
1390     .ndo_set_mac_address    = eth_mac_addr,
1391     .ndo_tx_timeout     = sc92031_tx_timeout,
1392 #ifdef CONFIG_NET_POLL_CONTROLLER
1393     .ndo_poll_controller    = sc92031_poll_controller,
1394 #endif
1395 };
1396 
1397 static int sc92031_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1398 {
1399     int err;
1400     void __iomem* port_base;
1401     struct net_device *dev;
1402     struct sc92031_priv *priv;
1403     u8 addr[ETH_ALEN];
1404     u32 mac0, mac1;
1405 
1406     err = pci_enable_device(pdev);
1407     if (unlikely(err < 0))
1408         goto out_enable_device;
1409 
1410     pci_set_master(pdev);
1411 
1412     err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1413     if (unlikely(err < 0))
1414         goto out_set_dma_mask;
1415 
1416     err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1417     if (unlikely(err < 0))
1418         goto out_set_dma_mask;
1419 
1420     err = pci_request_regions(pdev, SC92031_NAME);
1421     if (unlikely(err < 0))
1422         goto out_request_regions;
1423 
1424     port_base = pci_iomap(pdev, SC92031_USE_PIO, 0);
1425     if (unlikely(!port_base)) {
1426         err = -EIO;
1427         goto out_iomap;
1428     }
1429 
1430     dev = alloc_etherdev(sizeof(struct sc92031_priv));
1431     if (unlikely(!dev)) {
1432         err = -ENOMEM;
1433         goto out_alloc_etherdev;
1434     }
1435 
1436     pci_set_drvdata(pdev, dev);
1437     SET_NETDEV_DEV(dev, &pdev->dev);
1438 
1439     /* faked with skb_copy_and_csum_dev */
1440     dev->features = NETIF_F_SG | NETIF_F_HIGHDMA |
1441         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1442 
1443     dev->netdev_ops     = &sc92031_netdev_ops;
1444     dev->watchdog_timeo = TX_TIMEOUT;
1445     dev->ethtool_ops    = &sc92031_ethtool_ops;
1446 
1447     priv = netdev_priv(dev);
1448     priv->ndev = dev;
1449     spin_lock_init(&priv->lock);
1450     priv->port_base = port_base;
1451     priv->pdev = pdev;
1452     tasklet_setup(&priv->tasklet, sc92031_tasklet);
1453     /* Fudge tasklet count so the call to sc92031_enable_interrupts at
1454      * sc92031_open will work correctly */
1455     tasklet_disable_nosync(&priv->tasklet);
1456 
1457     /* PCI PM Wakeup */
1458     iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig);
1459 
1460     mac0 = ioread32(port_base + MAC0);
1461     mac1 = ioread32(port_base + MAC0 + 4);
1462     addr[0] = mac0 >> 24;
1463     addr[1] = mac0 >> 16;
1464     addr[2] = mac0 >> 8;
1465     addr[3] = mac0;
1466     addr[4] = mac1 >> 8;
1467     addr[5] = mac1;
1468     eth_hw_addr_set(dev, addr);
1469 
1470     err = register_netdev(dev);
1471     if (err < 0)
1472         goto out_register_netdev;
1473 
1474     printk(KERN_INFO "%s: SC92031 at 0x%lx, %pM, IRQ %d\n", dev->name,
1475            (long)pci_resource_start(pdev, SC92031_USE_PIO), dev->dev_addr,
1476            pdev->irq);
1477 
1478     return 0;
1479 
1480 out_register_netdev:
1481     free_netdev(dev);
1482 out_alloc_etherdev:
1483     pci_iounmap(pdev, port_base);
1484 out_iomap:
1485     pci_release_regions(pdev);
1486 out_request_regions:
1487 out_set_dma_mask:
1488     pci_disable_device(pdev);
1489 out_enable_device:
1490     return err;
1491 }
1492 
1493 static void sc92031_remove(struct pci_dev *pdev)
1494 {
1495     struct net_device *dev = pci_get_drvdata(pdev);
1496     struct sc92031_priv *priv = netdev_priv(dev);
1497     void __iomem* port_base = priv->port_base;
1498 
1499     unregister_netdev(dev);
1500     free_netdev(dev);
1501     pci_iounmap(pdev, port_base);
1502     pci_release_regions(pdev);
1503     pci_disable_device(pdev);
1504 }
1505 
1506 static int __maybe_unused sc92031_suspend(struct device *dev_d)
1507 {
1508     struct net_device *dev = dev_get_drvdata(dev_d);
1509     struct sc92031_priv *priv = netdev_priv(dev);
1510 
1511     if (!netif_running(dev))
1512         return 0;
1513 
1514     netif_device_detach(dev);
1515 
1516     /* Disable interrupts, stop Tx and Rx. */
1517     sc92031_disable_interrupts(dev);
1518 
1519     spin_lock_bh(&priv->lock);
1520 
1521     _sc92031_disable_tx_rx(dev);
1522     _sc92031_tx_clear(dev);
1523 
1524     spin_unlock_bh(&priv->lock);
1525 
1526     return 0;
1527 }
1528 
1529 static int __maybe_unused sc92031_resume(struct device *dev_d)
1530 {
1531     struct net_device *dev = dev_get_drvdata(dev_d);
1532     struct sc92031_priv *priv = netdev_priv(dev);
1533 
1534     if (!netif_running(dev))
1535         return 0;
1536 
1537     /* Interrupts already disabled by sc92031_suspend */
1538     spin_lock_bh(&priv->lock);
1539 
1540     _sc92031_reset(dev);
1541 
1542     spin_unlock_bh(&priv->lock);
1543     sc92031_enable_interrupts(dev);
1544 
1545     netif_device_attach(dev);
1546 
1547     if (netif_carrier_ok(dev))
1548         netif_wake_queue(dev);
1549     else
1550         netif_tx_disable(dev);
1551 
1552     return 0;
1553 }
1554 
1555 static const struct pci_device_id sc92031_pci_device_id_table[] = {
1556     { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x2031) },
1557     { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x8139) },
1558     { PCI_DEVICE(0x1088, 0x2031) },
1559     { 0, }
1560 };
1561 MODULE_DEVICE_TABLE(pci, sc92031_pci_device_id_table);
1562 
1563 static SIMPLE_DEV_PM_OPS(sc92031_pm_ops, sc92031_suspend, sc92031_resume);
1564 
1565 static struct pci_driver sc92031_pci_driver = {
1566     .name       = SC92031_NAME,
1567     .id_table   = sc92031_pci_device_id_table,
1568     .probe      = sc92031_probe,
1569     .remove     = sc92031_remove,
1570     .driver.pm  = &sc92031_pm_ops,
1571 };
1572 
1573 module_pci_driver(sc92031_pci_driver);
1574 MODULE_LICENSE("GPL");
1575 MODULE_AUTHOR("Cesar Eduardo Barros <cesarb@cesarb.net>");
1576 MODULE_DESCRIPTION("Silan SC92031 PCI Fast Ethernet Adapter driver");
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