ethernet/sgi/meth.h

0001 /* version dependencies have been confined to a separate file */
0002
0003 /* Tunable parameters */
0004 #define TX_RING_ENTRIES 64  /* 64-512?*/
0005
0006 #define RX_RING_ENTRIES 16 /* Do not change */
0007 /* Internal constants */
0008 #define TX_RING_BUFFER_SIZE (TX_RING_ENTRIES*sizeof(tx_packet))
0009 #define RX_BUFFER_SIZE 1546 /* ethenet packet size */
0010 #define METH_RX_BUFF_SIZE 4096
0011 #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
0012 #define RX_BUFFER_OFFSET (sizeof(rx_status_vector)+2) /* staus vector + 2 bytes of padding */
0013 #define RX_BUCKET_SIZE 256
0014
0015 /* For more detailed explanations of what each field menas,
0016    see Nick's great comments to #defines below (or docs, if
0017    you are lucky enough toget hold of them :)*/
0018
0019 /* tx status vector is written over tx command header upon
0020    dma completion. */
0021
0022 typedef struct tx_status_vector {
0023     u64     sent:1; /* always set to 1...*/
0024     u64     pad0:34;/* always set to 0 */
0025     u64     flags:9;            /*I'm too lazy to specify each one separately at the moment*/
0026     u64     col_retry_cnt:4;    /*collision retry count*/
0027     u64     len:16;             /*Transmit length in bytes*/
0028 } tx_status_vector;
0029
0030 /*
0031  * Each packet is 128 bytes long.
0032  * It consists of header, 0-3 concatination
0033  * buffer pointers and up to 120 data bytes.
0034  */
0035 typedef struct tx_packet_hdr {
0036     u64     pad1:36; /*should be filled with 0 */
0037     u64     cat_ptr3_valid:1,   /*Concatination pointer valid flags*/
0038             cat_ptr2_valid:1,
0039             cat_ptr1_valid:1;
0040     u64     tx_int_flag:1;      /*Generate TX intrrupt when packet has been sent*/
0041     u64     term_dma_flag:1;    /*Terminate transmit DMA on transmit abort conditions*/
0042     u64     data_offset:7;      /*Starting byte offset in ring data block*/
0043     u64     data_len:16;        /*Length of valid data in bytes-1*/
0044 } tx_packet_hdr;
0045 typedef union tx_cat_ptr {
0046     struct {
0047         u64     pad2:16; /* should be 0 */
0048         u64     len:16;             /*length of buffer data - 1*/
0049         u64     start_addr:29;      /*Physical starting address*/
0050         u64     pad1:3; /* should be zero */
0051     } form;
0052     u64 raw;
0053 } tx_cat_ptr;
0054
0055 typedef struct tx_packet {
0056     union {
0057         tx_packet_hdr header;
0058         tx_status_vector res;
0059         u64 raw;
0060     }header;
0061     union {
0062         tx_cat_ptr cat_buf[3];
0063         char dt[120];
0064     } data;
0065 } tx_packet;
0066
0067 typedef union rx_status_vector {
0068     volatile struct {
0069         u64     pad1:1;/*fill it with ones*/
0070         u64     pad2:15;/*fill with 0*/
0071         u64     ip_chk_sum:16;
0072         u64     seq_num:5;
0073         u64     mac_addr_match:1;
0074         u64     mcast_addr_match:1;
0075         u64     carrier_event_seen:1;
0076         u64     bad_packet:1;
0077         u64     long_event_seen:1;
0078         u64     invalid_preamble:1;
0079         u64     broadcast:1;
0080         u64     multicast:1;
0081         u64     crc_error:1;
0082         u64     huh:1;/*???*/
0083         u64     rx_code_violation:1;
0084         u64     rx_len:16;
0085     } parsed;
0086     volatile u64 raw;
0087 } rx_status_vector;
0088
0089 typedef struct rx_packet {
0090     rx_status_vector status;
0091         u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
0092         u16 pad2;
0093     char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
0094 } rx_packet;
0095
0096 #define TX_INFO_RPTR    0x00FF0000
0097 #define TX_INFO_WPTR    0x000000FF
0098
0099     /* Bits in METH_MAC */
0100
0101 #define SGI_MAC_RESET       BIT(0)  /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 core is active */
0102 #define METH_PHY_FDX        BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */
0103 #define METH_PHY_LOOP   BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loops internal MII bus */
0104                        /*    selects ignored */
0105 #define METH_100MBIT        BIT(3) /* 0: 10meg mode, 1: 100meg mode */
0106 #define METH_PHY_MII        BIT(4) /* 0: MII selected, 1: SIA selected */
0107                        /*   Note: when loopback is set this bit becomes collision control.  Setting this bit will */
0108                        /*         cause a collision to be reported. */
0109
0110                        /* Bits 5 and 6 are used to determine the Destination address filter mode */
0111 #define METH_ACCEPT_MY 0            /* 00: Accept PHY address only */
0112 #define METH_ACCEPT_MCAST 0x20  /* 01: Accept physical, broadcast, and multicast filter matches only */
0113 #define METH_ACCEPT_AMCAST 0x40 /* 10: Accept physical, broadcast, and all multicast packets */
0114 #define METH_PROMISC 0x60       /* 11: Promiscious mode */
0115
0116 #define METH_PHY_LINK_FAIL  BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link failure in PHY */
0117
0118 #define METH_MAC_IPG    0x1ffff00
0119
0120 #define METH_DEFAULT_IPG ((17<<15) | (11<<22) | (21<<8))
0121                         /* 0x172e5c00 */ /* 23, 23, 23 */ /*0x54A9500 *//*21,21,21*/
0122                        /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
0123                        /* The gap depends on the clock speed of the link, 80ns per increment for 100baseT, 800ns  */
0124                        /* per increment for 10BaseT */
0125
0126                        /* Bits 15 through 21 are used to determine IPGR1 */
0127
0128                        /* Bits 22 through 28 are used to determine IPGR2 */
0129
0130 #define METH_REV_SHIFT 29       /* Bits 29 through 31 are used to determine the revision */
0131                        /* 000: Initial revision */
0132                        /* 001: First revision, Improved TX concatenation */
0133
0134
0135 /* DMA control bits */
0136 #define METH_RX_OFFSET_SHIFT 12 /* Bits 12:14 of DMA control register indicate starting offset of packet data for RX operation */
0137 #define METH_RX_DEPTH_SHIFT 4 /* Bits 8:4 define RX fifo depth -- when # of RX fifo entries != depth, interrupt is generted */
0138
0139 #define METH_DMA_TX_EN BIT(1) /* enable TX DMA */
0140 #define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */
0141 #define METH_DMA_RX_EN BIT(15) /* Enable RX */
0142 #define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */
0143
0144 /* RX FIFO MCL Info bits */
0145 #define METH_RX_FIFO_WPTR(x)   (((x)>>16)&0xf)
0146 #define METH_RX_FIFO_RPTR(x)   (((x)>>8)&0xf)
0147 #define METH_RX_FIFO_DEPTH(x)  ((x)&0x1f)
0148
0149 /* RX status bits */
0150
0151 #define METH_RX_ST_VALID BIT(63)
0152 #define METH_RX_ST_RCV_CODE_VIOLATION BIT(16)
0153 #define METH_RX_ST_DRBL_NBL BIT(17)
0154 #define METH_RX_ST_CRC_ERR BIT(18)
0155 #define METH_RX_ST_MCAST_PKT BIT(19)
0156 #define METH_RX_ST_BCAST_PKT BIT(20)
0157 #define METH_RX_ST_INV_PREAMBLE_CTX BIT(21)
0158 #define METH_RX_ST_LONG_EVT_SEEN BIT(22)
0159 #define METH_RX_ST_BAD_PACKET BIT(23)
0160 #define METH_RX_ST_CARRIER_EVT_SEEN BIT(24)
0161 #define METH_RX_ST_MCAST_FILTER_MATCH BIT(25)
0162 #define METH_RX_ST_PHYS_ADDR_MATCH BIT(26)
0163
0164 #define METH_RX_STATUS_ERRORS \
0165     ( \
0166     METH_RX_ST_RCV_CODE_VIOLATION| \
0167     METH_RX_ST_CRC_ERR| \
0168     METH_RX_ST_INV_PREAMBLE_CTX| \
0169     METH_RX_ST_LONG_EVT_SEEN| \
0170     METH_RX_ST_BAD_PACKET| \
0171     METH_RX_ST_CARRIER_EVT_SEEN \
0172     )
0173     /* Bits in METH_INT */
0174     /* Write _1_ to corresponding bit to clear */
0175 #define METH_INT_TX_EMPTY   BIT(0)  /* 0: No interrupt pending, 1: The TX ring buffer is empty */
0176 #define METH_INT_TX_PKT     BIT(1)  /* 0: No interrupt pending */
0177                             /* 1: A TX message had the INT request bit set, the packet has been sent. */
0178 #define METH_INT_TX_LINK_FAIL   BIT(2)  /* 0: No interrupt pending, 1: PHY has reported a link failure */
0179 #define METH_INT_MEM_ERROR  BIT(3)  /* 0: No interrupt pending */
0180                         /* 1: A memory error occurred during DMA, DMA stopped, Fatal */
0181 #define METH_INT_TX_ABORT       BIT(4)  /* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */
0182 #define METH_INT_RX_THRESHOLD   BIT(5)  /* 0: No interrupt pending, 1: Selected receive threshold condition Valid */
0183 #define METH_INT_RX_UNDERFLOW   BIT(6)  /* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */
0184 #define METH_INT_RX_OVERFLOW        BIT(7)  /* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped, FATAL */
0185
0186 /*#define METH_INT_RX_RPTR_MASK 0x0001F00*/     /* Bits 8 through 12 alias of RX read-pointer */
0187 #define METH_INT_RX_RPTR_MASK 0x0000F00     /* Bits 8 through 11 alias of RX read-pointer - so, is Rx FIFO 16 or 32 entry?*/
0188
0189                         /* Bits 13 through 15 are always 0. */
0190
0191 #define METH_INT_TX_RPTR_MASK   0x1FF0000        /* Bits 16 through 24 alias of TX read-pointer */
0192
0193 #define METH_INT_RX_SEQ_MASK    0x2E000000  /* Bits 25 through 29 are the starting seq number for the message at the */
0194
0195                         /* top of the queue */
0196
0197 #define METH_INT_ERROR  (METH_INT_TX_LINK_FAIL| \
0198             METH_INT_MEM_ERROR| \
0199             METH_INT_TX_ABORT| \
0200             METH_INT_RX_OVERFLOW| \
0201             METH_INT_RX_UNDERFLOW)
0202
0203 #define METH_INT_MCAST_HASH     BIT(30) /* If RX DMA is enabled the hash select logic output is latched here */
0204
0205 /* TX status bits */
0206 #define METH_TX_ST_DONE      BIT(63) /* TX complete */
0207 #define METH_TX_ST_SUCCESS   BIT(23) /* Packet was transmitted successfully */
0208 #define METH_TX_ST_TOOLONG   BIT(24) /* TX abort due to excessive length */
0209 #define METH_TX_ST_UNDERRUN  BIT(25) /* TX abort due to underrun (?) */
0210 #define METH_TX_ST_EXCCOLL   BIT(26) /* TX abort due to excess collisions */
0211 #define METH_TX_ST_DEFER     BIT(27) /* TX abort due to excess deferals */
0212 #define METH_TX_ST_LATECOLL  BIT(28) /* TX abort due to late collision */
0213
0214
0215 /* Tx command header bits */
0216 #define METH_TX_CMD_INT_EN BIT(24) /* Generate TX interrupt when packet is sent */
0217
0218 /* Phy MDIO interface busy flag */
0219 #define MDIO_BUSY    BIT(16)
0220 #define MDIO_DATA_MASK 0xFFFF
0221 /* PHY defines */
0222 #define PHY_QS6612X    0x0181441    /* Quality TX */
0223 #define PHY_ICS1889    0x0015F41    /* ICS FX */
0224 #define PHY_ICS1890    0x0015F42    /* ICS TX */
0225 #define PHY_DP83840    0x20005C0    /* National TX */
0226
0227 #define ADVANCE_RX_PTR(x)  x=(x+1)&(RX_RING_ENTRIES-1)