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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * meth.c -- O2 Builtin 10/100 Ethernet driver
0004  *
0005  * Copyright (C) 2001-2003 Ilya Volynets
0006  */
0007 #include <linux/delay.h>
0008 #include <linux/dma-mapping.h>
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/slab.h>
0013 #include <linux/errno.h>
0014 #include <linux/types.h>
0015 #include <linux/interrupt.h>
0016 
0017 #include <linux/in.h>
0018 #include <linux/in6.h>
0019 #include <linux/device.h> /* struct device, et al */
0020 #include <linux/netdevice.h>   /* struct device, and other headers */
0021 #include <linux/etherdevice.h> /* eth_type_trans */
0022 #include <linux/ip.h>          /* struct iphdr */
0023 #include <linux/tcp.h>         /* struct tcphdr */
0024 #include <linux/skbuff.h>
0025 #include <linux/mii.h>         /* MII definitions */
0026 #include <linux/crc32.h>
0027 
0028 #include <asm/ip32/mace.h>
0029 #include <asm/ip32/ip32_ints.h>
0030 
0031 #include <asm/io.h>
0032 
0033 #include "meth.h"
0034 
0035 #ifndef MFE_DEBUG
0036 #define MFE_DEBUG 0
0037 #endif
0038 
0039 #if MFE_DEBUG>=1
0040 #define DPRINTK(str,args...) printk(KERN_DEBUG "meth: %s: " str, __func__ , ## args)
0041 #define MFE_RX_DEBUG 2
0042 #else
0043 #define DPRINTK(str,args...)
0044 #define MFE_RX_DEBUG 0
0045 #endif
0046 
0047 
0048 static const char *meth_str="SGI O2 Fast Ethernet";
0049 
0050 /* The maximum time waited (in jiffies) before assuming a Tx failed. (400ms) */
0051 #define TX_TIMEOUT (400*HZ/1000)
0052 
0053 static int timeout = TX_TIMEOUT;
0054 module_param(timeout, int, 0);
0055 
0056 /*
0057  * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
0058  * MACE Ethernet uses a 64 element hash table based on the Ethernet CRC.
0059  */
0060 #define METH_MCF_LIMIT 32
0061 
0062 /*
0063  * This structure is private to each device. It is used to pass
0064  * packets in and out, so there is place for a packet
0065  */
0066 struct meth_private {
0067     struct platform_device *pdev;
0068 
0069     /* in-memory copy of MAC Control register */
0070     u64 mac_ctrl;
0071 
0072     /* in-memory copy of DMA Control register */
0073     unsigned long dma_ctrl;
0074     /* address of PHY, used by mdio_* functions, initialized in mdio_probe */
0075     unsigned long phy_addr;
0076     tx_packet *tx_ring;
0077     dma_addr_t tx_ring_dma;
0078     struct sk_buff *tx_skbs[TX_RING_ENTRIES];
0079     dma_addr_t tx_skb_dmas[TX_RING_ENTRIES];
0080     unsigned long tx_read, tx_write, tx_count;
0081 
0082     rx_packet *rx_ring[RX_RING_ENTRIES];
0083     dma_addr_t rx_ring_dmas[RX_RING_ENTRIES];
0084     struct sk_buff *rx_skbs[RX_RING_ENTRIES];
0085     unsigned long rx_write;
0086 
0087     /* Multicast filter. */
0088     u64 mcast_filter;
0089 
0090     spinlock_t meth_lock;
0091 };
0092 
0093 static void meth_tx_timeout(struct net_device *dev, unsigned int txqueue);
0094 static irqreturn_t meth_interrupt(int irq, void *dev_id);
0095 
0096 /* global, initialized in ip32-setup.c */
0097 char o2meth_eaddr[8]={0,0,0,0,0,0,0,0};
0098 
0099 static inline void load_eaddr(struct net_device *dev)
0100 {
0101     int i;
0102     u64 macaddr;
0103 
0104     DPRINTK("Loading MAC Address: %pM\n", dev->dev_addr);
0105     macaddr = 0;
0106     for (i = 0; i < 6; i++)
0107         macaddr |= (u64)dev->dev_addr[i] << ((5 - i) * 8);
0108 
0109     mace->eth.mac_addr = macaddr;
0110 }
0111 
0112 /*
0113  * Waits for BUSY status of mdio bus to clear
0114  */
0115 #define WAIT_FOR_PHY(___rval)                   \
0116     while ((___rval = mace->eth.phy_data) & MDIO_BUSY) {    \
0117         udelay(25);                 \
0118     }
0119 /*read phy register, return value read */
0120 static unsigned long mdio_read(struct meth_private *priv, unsigned long phyreg)
0121 {
0122     unsigned long rval;
0123     WAIT_FOR_PHY(rval);
0124     mace->eth.phy_regs = (priv->phy_addr << 5) | (phyreg & 0x1f);
0125     udelay(25);
0126     mace->eth.phy_trans_go = 1;
0127     udelay(25);
0128     WAIT_FOR_PHY(rval);
0129     return rval & MDIO_DATA_MASK;
0130 }
0131 
0132 static int mdio_probe(struct meth_private *priv)
0133 {
0134     int i;
0135     unsigned long p2, p3, flags;
0136     /* check if phy is detected already */
0137     if(priv->phy_addr>=0&&priv->phy_addr<32)
0138         return 0;
0139     spin_lock_irqsave(&priv->meth_lock, flags);
0140     for (i=0;i<32;++i){
0141         priv->phy_addr=i;
0142         p2=mdio_read(priv,2);
0143         p3=mdio_read(priv,3);
0144 #if MFE_DEBUG>=2
0145         switch ((p2<<12)|(p3>>4)){
0146         case PHY_QS6612X:
0147             DPRINTK("PHY is QS6612X\n");
0148             break;
0149         case PHY_ICS1889:
0150             DPRINTK("PHY is ICS1889\n");
0151             break;
0152         case PHY_ICS1890:
0153             DPRINTK("PHY is ICS1890\n");
0154             break;
0155         case PHY_DP83840:
0156             DPRINTK("PHY is DP83840\n");
0157             break;
0158         }
0159 #endif
0160         if(p2!=0xffff&&p2!=0x0000){
0161             DPRINTK("PHY code: %x\n",(p2<<12)|(p3>>4));
0162             break;
0163         }
0164     }
0165     spin_unlock_irqrestore(&priv->meth_lock, flags);
0166     if(priv->phy_addr<32) {
0167         return 0;
0168     }
0169     DPRINTK("Oopsie! PHY is not known!\n");
0170     priv->phy_addr=-1;
0171     return -ENODEV;
0172 }
0173 
0174 static void meth_check_link(struct net_device *dev)
0175 {
0176     struct meth_private *priv = netdev_priv(dev);
0177     unsigned long mii_advertising = mdio_read(priv, 4);
0178     unsigned long mii_partner = mdio_read(priv, 5);
0179     unsigned long negotiated = mii_advertising & mii_partner;
0180     unsigned long duplex, speed;
0181 
0182     if (mii_partner == 0xffff)
0183         return;
0184 
0185     speed = (negotiated & 0x0380) ? METH_100MBIT : 0;
0186     duplex = ((negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040) ?
0187          METH_PHY_FDX : 0;
0188 
0189     if ((priv->mac_ctrl & METH_PHY_FDX) ^ duplex) {
0190         DPRINTK("Setting %s-duplex\n", duplex ? "full" : "half");
0191         if (duplex)
0192             priv->mac_ctrl |= METH_PHY_FDX;
0193         else
0194             priv->mac_ctrl &= ~METH_PHY_FDX;
0195         mace->eth.mac_ctrl = priv->mac_ctrl;
0196     }
0197 
0198     if ((priv->mac_ctrl & METH_100MBIT) ^ speed) {
0199         DPRINTK("Setting %dMbs mode\n", speed ? 100 : 10);
0200         if (duplex)
0201             priv->mac_ctrl |= METH_100MBIT;
0202         else
0203             priv->mac_ctrl &= ~METH_100MBIT;
0204         mace->eth.mac_ctrl = priv->mac_ctrl;
0205     }
0206 }
0207 
0208 
0209 static int meth_init_tx_ring(struct meth_private *priv)
0210 {
0211     /* Init TX ring */
0212     priv->tx_ring = dma_alloc_coherent(&priv->pdev->dev,
0213             TX_RING_BUFFER_SIZE, &priv->tx_ring_dma, GFP_ATOMIC);
0214     if (!priv->tx_ring)
0215         return -ENOMEM;
0216 
0217     priv->tx_count = priv->tx_read = priv->tx_write = 0;
0218     mace->eth.tx_ring_base = priv->tx_ring_dma;
0219     /* Now init skb save area */
0220     memset(priv->tx_skbs, 0, sizeof(priv->tx_skbs));
0221     memset(priv->tx_skb_dmas, 0, sizeof(priv->tx_skb_dmas));
0222     return 0;
0223 }
0224 
0225 static int meth_init_rx_ring(struct meth_private *priv)
0226 {
0227     int i;
0228 
0229     for (i = 0; i < RX_RING_ENTRIES; i++) {
0230         priv->rx_skbs[i] = alloc_skb(METH_RX_BUFF_SIZE, 0);
0231         /* 8byte status vector + 3quad padding + 2byte padding,
0232          * to put data on 64bit aligned boundary */
0233         skb_reserve(priv->rx_skbs[i],METH_RX_HEAD);
0234         priv->rx_ring[i]=(rx_packet*)(priv->rx_skbs[i]->head);
0235         /* I'll need to re-sync it after each RX */
0236         priv->rx_ring_dmas[i] =
0237             dma_map_single(&priv->pdev->dev, priv->rx_ring[i],
0238                        METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
0239         mace->eth.rx_fifo = priv->rx_ring_dmas[i];
0240     }
0241         priv->rx_write = 0;
0242     return 0;
0243 }
0244 static void meth_free_tx_ring(struct meth_private *priv)
0245 {
0246     int i;
0247 
0248     /* Remove any pending skb */
0249     for (i = 0; i < TX_RING_ENTRIES; i++) {
0250         dev_kfree_skb(priv->tx_skbs[i]);
0251         priv->tx_skbs[i] = NULL;
0252     }
0253     dma_free_coherent(&priv->pdev->dev, TX_RING_BUFFER_SIZE, priv->tx_ring,
0254                       priv->tx_ring_dma);
0255 }
0256 
0257 /* Presumes RX DMA engine is stopped, and RX fifo ring is reset */
0258 static void meth_free_rx_ring(struct meth_private *priv)
0259 {
0260     int i;
0261 
0262     for (i = 0; i < RX_RING_ENTRIES; i++) {
0263         dma_unmap_single(&priv->pdev->dev, priv->rx_ring_dmas[i],
0264                  METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
0265         priv->rx_ring[i] = 0;
0266         priv->rx_ring_dmas[i] = 0;
0267         kfree_skb(priv->rx_skbs[i]);
0268     }
0269 }
0270 
0271 int meth_reset(struct net_device *dev)
0272 {
0273     struct meth_private *priv = netdev_priv(dev);
0274 
0275     /* Reset card */
0276     mace->eth.mac_ctrl = SGI_MAC_RESET;
0277     udelay(1);
0278     mace->eth.mac_ctrl = 0;
0279     udelay(25);
0280 
0281     /* Load ethernet address */
0282     load_eaddr(dev);
0283     /* Should load some "errata", but later */
0284 
0285     /* Check for device */
0286     if (mdio_probe(priv) < 0) {
0287         DPRINTK("Unable to find PHY\n");
0288         return -ENODEV;
0289     }
0290 
0291     /* Initial mode: 10 | Half-duplex | Accept normal packets */
0292     priv->mac_ctrl = METH_ACCEPT_MCAST | METH_DEFAULT_IPG;
0293     if (dev->flags & IFF_PROMISC)
0294         priv->mac_ctrl |= METH_PROMISC;
0295     mace->eth.mac_ctrl = priv->mac_ctrl;
0296 
0297     /* Autonegotiate speed and duplex mode */
0298     meth_check_link(dev);
0299 
0300     /* Now set dma control, but don't enable DMA, yet */
0301     priv->dma_ctrl = (4 << METH_RX_OFFSET_SHIFT) |
0302              (RX_RING_ENTRIES << METH_RX_DEPTH_SHIFT);
0303     mace->eth.dma_ctrl = priv->dma_ctrl;
0304 
0305     return 0;
0306 }
0307 
0308 /*============End Helper Routines=====================*/
0309 
0310 /*
0311  * Open and close
0312  */
0313 static int meth_open(struct net_device *dev)
0314 {
0315     struct meth_private *priv = netdev_priv(dev);
0316     int ret;
0317 
0318     priv->phy_addr = -1;    /* No PHY is known yet... */
0319 
0320     /* Initialize the hardware */
0321     ret = meth_reset(dev);
0322     if (ret < 0)
0323         return ret;
0324 
0325     /* Allocate the ring buffers */
0326     ret = meth_init_tx_ring(priv);
0327     if (ret < 0)
0328         return ret;
0329     ret = meth_init_rx_ring(priv);
0330     if (ret < 0)
0331         goto out_free_tx_ring;
0332 
0333     ret = request_irq(dev->irq, meth_interrupt, 0, meth_str, dev);
0334     if (ret) {
0335         printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
0336         goto out_free_rx_ring;
0337     }
0338 
0339     /* Start DMA */
0340     priv->dma_ctrl |= METH_DMA_TX_EN | /*METH_DMA_TX_INT_EN |*/
0341               METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
0342     mace->eth.dma_ctrl = priv->dma_ctrl;
0343 
0344     DPRINTK("About to start queue\n");
0345     netif_start_queue(dev);
0346 
0347     return 0;
0348 
0349 out_free_rx_ring:
0350     meth_free_rx_ring(priv);
0351 out_free_tx_ring:
0352     meth_free_tx_ring(priv);
0353 
0354     return ret;
0355 }
0356 
0357 static int meth_release(struct net_device *dev)
0358 {
0359     struct meth_private *priv = netdev_priv(dev);
0360 
0361     DPRINTK("Stopping queue\n");
0362     netif_stop_queue(dev); /* can't transmit any more */
0363     /* shut down DMA */
0364     priv->dma_ctrl &= ~(METH_DMA_TX_EN | METH_DMA_TX_INT_EN |
0365                 METH_DMA_RX_EN | METH_DMA_RX_INT_EN);
0366     mace->eth.dma_ctrl = priv->dma_ctrl;
0367     free_irq(dev->irq, dev);
0368     meth_free_tx_ring(priv);
0369     meth_free_rx_ring(priv);
0370 
0371     return 0;
0372 }
0373 
0374 /*
0375  * Receive a packet: retrieve, encapsulate and pass over to upper levels
0376  */
0377 static void meth_rx(struct net_device* dev, unsigned long int_status)
0378 {
0379     struct sk_buff *skb;
0380     unsigned long status, flags;
0381     struct meth_private *priv = netdev_priv(dev);
0382     unsigned long fifo_rptr = (int_status & METH_INT_RX_RPTR_MASK) >> 8;
0383 
0384     spin_lock_irqsave(&priv->meth_lock, flags);
0385     priv->dma_ctrl &= ~METH_DMA_RX_INT_EN;
0386     mace->eth.dma_ctrl = priv->dma_ctrl;
0387     spin_unlock_irqrestore(&priv->meth_lock, flags);
0388 
0389     if (int_status & METH_INT_RX_UNDERFLOW) {
0390         fifo_rptr = (fifo_rptr - 1) & 0x0f;
0391     }
0392     while (priv->rx_write != fifo_rptr) {
0393         dma_unmap_single(&priv->pdev->dev,
0394                  priv->rx_ring_dmas[priv->rx_write],
0395                  METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
0396         status = priv->rx_ring[priv->rx_write]->status.raw;
0397 #if MFE_DEBUG
0398         if (!(status & METH_RX_ST_VALID)) {
0399             DPRINTK("Not received? status=%016lx\n",status);
0400         }
0401 #endif
0402         if ((!(status & METH_RX_STATUS_ERRORS)) && (status & METH_RX_ST_VALID)) {
0403             int len = (status & 0xffff) - 4; /* omit CRC */
0404             /* length sanity check */
0405             if (len < 60 || len > 1518) {
0406                 printk(KERN_DEBUG "%s: bogus packet size: %ld, status=%#2Lx.\n",
0407                        dev->name, priv->rx_write,
0408                        priv->rx_ring[priv->rx_write]->status.raw);
0409                 dev->stats.rx_errors++;
0410                 dev->stats.rx_length_errors++;
0411                 skb = priv->rx_skbs[priv->rx_write];
0412             } else {
0413                 skb = alloc_skb(METH_RX_BUFF_SIZE, GFP_ATOMIC);
0414                 if (!skb) {
0415                     /* Ouch! No memory! Drop packet on the floor */
0416                     DPRINTK("No mem: dropping packet\n");
0417                     dev->stats.rx_dropped++;
0418                     skb = priv->rx_skbs[priv->rx_write];
0419                 } else {
0420                     struct sk_buff *skb_c = priv->rx_skbs[priv->rx_write];
0421                     /* 8byte status vector + 3quad padding + 2byte padding,
0422                      * to put data on 64bit aligned boundary */
0423                     skb_reserve(skb, METH_RX_HEAD);
0424                     /* Write metadata, and then pass to the receive level */
0425                     skb_put(skb_c, len);
0426                     priv->rx_skbs[priv->rx_write] = skb;
0427                     skb_c->protocol = eth_type_trans(skb_c, dev);
0428                     dev->stats.rx_packets++;
0429                     dev->stats.rx_bytes += len;
0430                     netif_rx(skb_c);
0431                 }
0432             }
0433         } else {
0434             dev->stats.rx_errors++;
0435             skb=priv->rx_skbs[priv->rx_write];
0436 #if MFE_DEBUG>0
0437             printk(KERN_WARNING "meth: RX error: status=0x%016lx\n",status);
0438             if(status&METH_RX_ST_RCV_CODE_VIOLATION)
0439                 printk(KERN_WARNING "Receive Code Violation\n");
0440             if(status&METH_RX_ST_CRC_ERR)
0441                 printk(KERN_WARNING "CRC error\n");
0442             if(status&METH_RX_ST_INV_PREAMBLE_CTX)
0443                 printk(KERN_WARNING "Invalid Preamble Context\n");
0444             if(status&METH_RX_ST_LONG_EVT_SEEN)
0445                 printk(KERN_WARNING "Long Event Seen...\n");
0446             if(status&METH_RX_ST_BAD_PACKET)
0447                 printk(KERN_WARNING "Bad Packet\n");
0448             if(status&METH_RX_ST_CARRIER_EVT_SEEN)
0449                 printk(KERN_WARNING "Carrier Event Seen\n");
0450 #endif
0451         }
0452         priv->rx_ring[priv->rx_write] = (rx_packet*)skb->head;
0453         priv->rx_ring[priv->rx_write]->status.raw = 0;
0454         priv->rx_ring_dmas[priv->rx_write] =
0455             dma_map_single(&priv->pdev->dev,
0456                        priv->rx_ring[priv->rx_write],
0457                        METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
0458         mace->eth.rx_fifo = priv->rx_ring_dmas[priv->rx_write];
0459         ADVANCE_RX_PTR(priv->rx_write);
0460     }
0461     spin_lock_irqsave(&priv->meth_lock, flags);
0462     /* In case there was underflow, and Rx DMA was disabled */
0463     priv->dma_ctrl |= METH_DMA_RX_INT_EN | METH_DMA_RX_EN;
0464     mace->eth.dma_ctrl = priv->dma_ctrl;
0465     mace->eth.int_stat = METH_INT_RX_THRESHOLD;
0466     spin_unlock_irqrestore(&priv->meth_lock, flags);
0467 }
0468 
0469 static int meth_tx_full(struct net_device *dev)
0470 {
0471     struct meth_private *priv = netdev_priv(dev);
0472 
0473     return priv->tx_count >= TX_RING_ENTRIES - 1;
0474 }
0475 
0476 static void meth_tx_cleanup(struct net_device* dev, unsigned long int_status)
0477 {
0478     struct meth_private *priv = netdev_priv(dev);
0479     unsigned long status, flags;
0480     struct sk_buff *skb;
0481     unsigned long rptr = (int_status&TX_INFO_RPTR) >> 16;
0482 
0483     spin_lock_irqsave(&priv->meth_lock, flags);
0484 
0485     /* Stop DMA notification */
0486     priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
0487     mace->eth.dma_ctrl = priv->dma_ctrl;
0488 
0489     while (priv->tx_read != rptr) {
0490         skb = priv->tx_skbs[priv->tx_read];
0491         status = priv->tx_ring[priv->tx_read].header.raw;
0492 #if MFE_DEBUG>=1
0493         if (priv->tx_read == priv->tx_write)
0494             DPRINTK("Auchi! tx_read=%d,tx_write=%d,rptr=%d?\n", priv->tx_read, priv->tx_write,rptr);
0495 #endif
0496         if (status & METH_TX_ST_DONE) {
0497             if (status & METH_TX_ST_SUCCESS){
0498                 dev->stats.tx_packets++;
0499                 dev->stats.tx_bytes += skb->len;
0500             } else {
0501                 dev->stats.tx_errors++;
0502 #if MFE_DEBUG>=1
0503                 DPRINTK("TX error: status=%016lx <",status);
0504                 if(status & METH_TX_ST_SUCCESS)
0505                     printk(" SUCCESS");
0506                 if(status & METH_TX_ST_TOOLONG)
0507                     printk(" TOOLONG");
0508                 if(status & METH_TX_ST_UNDERRUN)
0509                     printk(" UNDERRUN");
0510                 if(status & METH_TX_ST_EXCCOLL)
0511                     printk(" EXCCOLL");
0512                 if(status & METH_TX_ST_DEFER)
0513                     printk(" DEFER");
0514                 if(status & METH_TX_ST_LATECOLL)
0515                     printk(" LATECOLL");
0516                 printk(" >\n");
0517 #endif
0518             }
0519         } else {
0520             DPRINTK("RPTR points us here, but packet not done?\n");
0521             break;
0522         }
0523         dev_consume_skb_irq(skb);
0524         priv->tx_skbs[priv->tx_read] = NULL;
0525         priv->tx_ring[priv->tx_read].header.raw = 0;
0526         priv->tx_read = (priv->tx_read+1)&(TX_RING_ENTRIES-1);
0527         priv->tx_count--;
0528     }
0529 
0530     /* wake up queue if it was stopped */
0531     if (netif_queue_stopped(dev) && !meth_tx_full(dev)) {
0532         netif_wake_queue(dev);
0533     }
0534 
0535     mace->eth.int_stat = METH_INT_TX_EMPTY | METH_INT_TX_PKT;
0536     spin_unlock_irqrestore(&priv->meth_lock, flags);
0537 }
0538 
0539 static void meth_error(struct net_device* dev, unsigned status)
0540 {
0541     struct meth_private *priv = netdev_priv(dev);
0542     unsigned long flags;
0543 
0544     printk(KERN_WARNING "meth: error status: 0x%08x\n",status);
0545     /* check for errors too... */
0546     if (status & (METH_INT_TX_LINK_FAIL))
0547         printk(KERN_WARNING "meth: link failure\n");
0548     /* Should I do full reset in this case? */
0549     if (status & (METH_INT_MEM_ERROR))
0550         printk(KERN_WARNING "meth: memory error\n");
0551     if (status & (METH_INT_TX_ABORT))
0552         printk(KERN_WARNING "meth: aborted\n");
0553     if (status & (METH_INT_RX_OVERFLOW))
0554         printk(KERN_WARNING "meth: Rx overflow\n");
0555     if (status & (METH_INT_RX_UNDERFLOW)) {
0556         printk(KERN_WARNING "meth: Rx underflow\n");
0557         spin_lock_irqsave(&priv->meth_lock, flags);
0558         mace->eth.int_stat = METH_INT_RX_UNDERFLOW;
0559         /* more underflow interrupts will be delivered,
0560          * effectively throwing us into an infinite loop.
0561          *  Thus I stop processing Rx in this case. */
0562         priv->dma_ctrl &= ~METH_DMA_RX_EN;
0563         mace->eth.dma_ctrl = priv->dma_ctrl;
0564         DPRINTK("Disabled meth Rx DMA temporarily\n");
0565         spin_unlock_irqrestore(&priv->meth_lock, flags);
0566     }
0567     mace->eth.int_stat = METH_INT_ERROR;
0568 }
0569 
0570 /*
0571  * The typical interrupt entry point
0572  */
0573 static irqreturn_t meth_interrupt(int irq, void *dev_id)
0574 {
0575     struct net_device *dev = (struct net_device *)dev_id;
0576     struct meth_private *priv = netdev_priv(dev);
0577     unsigned long status;
0578 
0579     status = mace->eth.int_stat;
0580     while (status & 0xff) {
0581         /* First handle errors - if we get Rx underflow,
0582          * Rx DMA will be disabled, and Rx handler will reenable
0583          * it. I don't think it's possible to get Rx underflow,
0584          * without getting Rx interrupt */
0585         if (status & METH_INT_ERROR) {
0586             meth_error(dev, status);
0587         }
0588         if (status & (METH_INT_TX_EMPTY | METH_INT_TX_PKT)) {
0589             /* a transmission is over: free the skb */
0590             meth_tx_cleanup(dev, status);
0591         }
0592         if (status & METH_INT_RX_THRESHOLD) {
0593             if (!(priv->dma_ctrl & METH_DMA_RX_INT_EN))
0594                 break;
0595             /* send it to meth_rx for handling */
0596             meth_rx(dev, status);
0597         }
0598         status = mace->eth.int_stat;
0599     }
0600 
0601     return IRQ_HANDLED;
0602 }
0603 
0604 /*
0605  * Transmits packets that fit into TX descriptor (are <=120B)
0606  */
0607 static void meth_tx_short_prepare(struct meth_private *priv,
0608                   struct sk_buff *skb)
0609 {
0610     tx_packet *desc = &priv->tx_ring[priv->tx_write];
0611     int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
0612 
0613     desc->header.raw = METH_TX_CMD_INT_EN | (len-1) | ((128-len) << 16);
0614     /* maybe I should set whole thing to 0 first... */
0615     skb_copy_from_linear_data(skb, desc->data.dt + (120 - len), skb->len);
0616     if (skb->len < len)
0617         memset(desc->data.dt + 120 - len + skb->len, 0, len-skb->len);
0618 }
0619 #define TX_CATBUF1 BIT(25)
0620 static void meth_tx_1page_prepare(struct meth_private *priv,
0621                   struct sk_buff *skb)
0622 {
0623     tx_packet *desc = &priv->tx_ring[priv->tx_write];
0624     void *buffer_data = (void *)(((unsigned long)skb->data + 7) & ~7);
0625     int unaligned_len = (int)((unsigned long)buffer_data - (unsigned long)skb->data);
0626     int buffer_len = skb->len - unaligned_len;
0627     dma_addr_t catbuf;
0628 
0629     desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | (skb->len - 1);
0630 
0631     /* unaligned part */
0632     if (unaligned_len) {
0633         skb_copy_from_linear_data(skb, desc->data.dt + (120 - unaligned_len),
0634                   unaligned_len);
0635         desc->header.raw |= (128 - unaligned_len) << 16;
0636     }
0637 
0638     /* first page */
0639     catbuf = dma_map_single(&priv->pdev->dev, buffer_data, buffer_len,
0640                 DMA_TO_DEVICE);
0641     desc->data.cat_buf[0].form.start_addr = catbuf >> 3;
0642     desc->data.cat_buf[0].form.len = buffer_len - 1;
0643 }
0644 #define TX_CATBUF2 BIT(26)
0645 static void meth_tx_2page_prepare(struct meth_private *priv,
0646                   struct sk_buff *skb)
0647 {
0648     tx_packet *desc = &priv->tx_ring[priv->tx_write];
0649     void *buffer1_data = (void *)(((unsigned long)skb->data + 7) & ~7);
0650     void *buffer2_data = (void *)PAGE_ALIGN((unsigned long)skb->data);
0651     int unaligned_len = (int)((unsigned long)buffer1_data - (unsigned long)skb->data);
0652     int buffer1_len = (int)((unsigned long)buffer2_data - (unsigned long)buffer1_data);
0653     int buffer2_len = skb->len - buffer1_len - unaligned_len;
0654     dma_addr_t catbuf1, catbuf2;
0655 
0656     desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | TX_CATBUF2| (skb->len - 1);
0657     /* unaligned part */
0658     if (unaligned_len){
0659         skb_copy_from_linear_data(skb, desc->data.dt + (120 - unaligned_len),
0660                   unaligned_len);
0661         desc->header.raw |= (128 - unaligned_len) << 16;
0662     }
0663 
0664     /* first page */
0665     catbuf1 = dma_map_single(&priv->pdev->dev, buffer1_data, buffer1_len,
0666                  DMA_TO_DEVICE);
0667     desc->data.cat_buf[0].form.start_addr = catbuf1 >> 3;
0668     desc->data.cat_buf[0].form.len = buffer1_len - 1;
0669     /* second page */
0670     catbuf2 = dma_map_single(&priv->pdev->dev, buffer2_data, buffer2_len,
0671                  DMA_TO_DEVICE);
0672     desc->data.cat_buf[1].form.start_addr = catbuf2 >> 3;
0673     desc->data.cat_buf[1].form.len = buffer2_len - 1;
0674 }
0675 
0676 static void meth_add_to_tx_ring(struct meth_private *priv, struct sk_buff *skb)
0677 {
0678     /* Remember the skb, so we can free it at interrupt time */
0679     priv->tx_skbs[priv->tx_write] = skb;
0680     if (skb->len <= 120) {
0681         /* Whole packet fits into descriptor */
0682         meth_tx_short_prepare(priv, skb);
0683     } else if (PAGE_ALIGN((unsigned long)skb->data) !=
0684            PAGE_ALIGN((unsigned long)skb->data + skb->len - 1)) {
0685         /* Packet crosses page boundary */
0686         meth_tx_2page_prepare(priv, skb);
0687     } else {
0688         /* Packet is in one page */
0689         meth_tx_1page_prepare(priv, skb);
0690     }
0691     priv->tx_write = (priv->tx_write + 1) & (TX_RING_ENTRIES - 1);
0692     mace->eth.tx_info = priv->tx_write;
0693     priv->tx_count++;
0694 }
0695 
0696 /*
0697  * Transmit a packet (called by the kernel)
0698  */
0699 static netdev_tx_t meth_tx(struct sk_buff *skb, struct net_device *dev)
0700 {
0701     struct meth_private *priv = netdev_priv(dev);
0702     unsigned long flags;
0703 
0704     spin_lock_irqsave(&priv->meth_lock, flags);
0705     /* Stop DMA notification */
0706     priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
0707     mace->eth.dma_ctrl = priv->dma_ctrl;
0708 
0709     meth_add_to_tx_ring(priv, skb);
0710     netif_trans_update(dev); /* save the timestamp */
0711 
0712     /* If TX ring is full, tell the upper layer to stop sending packets */
0713     if (meth_tx_full(dev)) {
0714             printk(KERN_DEBUG "TX full: stopping\n");
0715         netif_stop_queue(dev);
0716     }
0717 
0718     /* Restart DMA notification */
0719     priv->dma_ctrl |= METH_DMA_TX_INT_EN;
0720     mace->eth.dma_ctrl = priv->dma_ctrl;
0721 
0722     spin_unlock_irqrestore(&priv->meth_lock, flags);
0723 
0724     return NETDEV_TX_OK;
0725 }
0726 
0727 /*
0728  * Deal with a transmit timeout.
0729  */
0730 static void meth_tx_timeout(struct net_device *dev, unsigned int txqueue)
0731 {
0732     struct meth_private *priv = netdev_priv(dev);
0733     unsigned long flags;
0734 
0735     printk(KERN_WARNING "%s: transmit timed out\n", dev->name);
0736 
0737     /* Protect against concurrent rx interrupts */
0738     spin_lock_irqsave(&priv->meth_lock,flags);
0739 
0740     /* Try to reset the interface. */
0741     meth_reset(dev);
0742 
0743     dev->stats.tx_errors++;
0744 
0745     /* Clear all rings */
0746     meth_free_tx_ring(priv);
0747     meth_free_rx_ring(priv);
0748     meth_init_tx_ring(priv);
0749     meth_init_rx_ring(priv);
0750 
0751     /* Restart dma */
0752     priv->dma_ctrl |= METH_DMA_TX_EN | METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
0753     mace->eth.dma_ctrl = priv->dma_ctrl;
0754 
0755     /* Enable interrupt */
0756     spin_unlock_irqrestore(&priv->meth_lock, flags);
0757 
0758     netif_trans_update(dev); /* prevent tx timeout */
0759     netif_wake_queue(dev);
0760 }
0761 
0762 /*
0763  * Ioctl commands
0764  */
0765 static int meth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
0766 {
0767     /* XXX Not yet implemented */
0768     switch(cmd) {
0769     case SIOCGMIIPHY:
0770     case SIOCGMIIREG:
0771     case SIOCSMIIREG:
0772     default:
0773         return -EOPNOTSUPP;
0774     }
0775 }
0776 
0777 static void meth_set_rx_mode(struct net_device *dev)
0778 {
0779     struct meth_private *priv = netdev_priv(dev);
0780     unsigned long flags;
0781 
0782     netif_stop_queue(dev);
0783     spin_lock_irqsave(&priv->meth_lock, flags);
0784     priv->mac_ctrl &= ~METH_PROMISC;
0785 
0786     if (dev->flags & IFF_PROMISC) {
0787         priv->mac_ctrl |= METH_PROMISC;
0788         priv->mcast_filter = 0xffffffffffffffffUL;
0789     } else if ((netdev_mc_count(dev) > METH_MCF_LIMIT) ||
0790            (dev->flags & IFF_ALLMULTI)) {
0791         priv->mac_ctrl |= METH_ACCEPT_AMCAST;
0792         priv->mcast_filter = 0xffffffffffffffffUL;
0793     } else {
0794         struct netdev_hw_addr *ha;
0795         priv->mac_ctrl |= METH_ACCEPT_MCAST;
0796 
0797         netdev_for_each_mc_addr(ha, dev)
0798             set_bit((ether_crc(ETH_ALEN, ha->addr) >> 26),
0799                     (volatile unsigned long *)&priv->mcast_filter);
0800     }
0801 
0802     /* Write the changes to the chip registers. */
0803     mace->eth.mac_ctrl = priv->mac_ctrl;
0804     mace->eth.mcast_filter = priv->mcast_filter;
0805 
0806     /* Done! */
0807     spin_unlock_irqrestore(&priv->meth_lock, flags);
0808     netif_wake_queue(dev);
0809 }
0810 
0811 static const struct net_device_ops meth_netdev_ops = {
0812     .ndo_open       = meth_open,
0813     .ndo_stop       = meth_release,
0814     .ndo_start_xmit     = meth_tx,
0815     .ndo_eth_ioctl      = meth_ioctl,
0816     .ndo_tx_timeout     = meth_tx_timeout,
0817     .ndo_validate_addr  = eth_validate_addr,
0818     .ndo_set_mac_address    = eth_mac_addr,
0819     .ndo_set_rx_mode        = meth_set_rx_mode,
0820 };
0821 
0822 /*
0823  * The init function.
0824  */
0825 static int meth_probe(struct platform_device *pdev)
0826 {
0827     struct net_device *dev;
0828     struct meth_private *priv;
0829     int err;
0830 
0831     dev = alloc_etherdev(sizeof(struct meth_private));
0832     if (!dev)
0833         return -ENOMEM;
0834 
0835     dev->netdev_ops     = &meth_netdev_ops;
0836     dev->watchdog_timeo = timeout;
0837     dev->irq        = MACE_ETHERNET_IRQ;
0838     dev->base_addr      = (unsigned long)&mace->eth;
0839     eth_hw_addr_set(dev, o2meth_eaddr);
0840 
0841     priv = netdev_priv(dev);
0842     priv->pdev = pdev;
0843     spin_lock_init(&priv->meth_lock);
0844     SET_NETDEV_DEV(dev, &pdev->dev);
0845 
0846     err = register_netdev(dev);
0847     if (err) {
0848         free_netdev(dev);
0849         return err;
0850     }
0851 
0852     printk(KERN_INFO "%s: SGI MACE Ethernet rev. %d\n",
0853            dev->name, (unsigned int)(mace->eth.mac_ctrl >> 29));
0854     return 0;
0855 }
0856 
0857 static int meth_remove(struct platform_device *pdev)
0858 {
0859     struct net_device *dev = platform_get_drvdata(pdev);
0860 
0861     unregister_netdev(dev);
0862     free_netdev(dev);
0863 
0864     return 0;
0865 }
0866 
0867 static struct platform_driver meth_driver = {
0868     .probe  = meth_probe,
0869     .remove = meth_remove,
0870     .driver = {
0871         .name   = "meth",
0872     }
0873 };
0874 
0875 module_platform_driver(meth_driver);
0876 
0877 MODULE_AUTHOR("Ilya Volynets <ilya@theIlya.com>");
0878 MODULE_DESCRIPTION("SGI O2 Builtin Fast Ethernet driver");
0879 MODULE_LICENSE("GPL");
0880 MODULE_ALIAS("platform:meth");
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