ethernet/sfc/tx_common.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /****************************************************************************
0003  * Driver for Solarflare network controllers and boards
0004  * Copyright 2018 Solarflare Communications Inc.
0005  *
0006  * This program is free software; you can redistribute it and/or modify it
0007  * under the terms of the GNU General Public License version 2 as published
0008  * by the Free Software Foundation, incorporated herein by reference.
0009  */
0010
0011 #include "net_driver.h"
0012 #include "efx.h"
0013 #include "nic_common.h"
0014 #include "tx_common.h"
0015
0016 static unsigned int efx_tx_cb_page_count(struct efx_tx_queue *tx_queue)
0017 {
0018     return DIV_ROUND_UP(tx_queue->ptr_mask + 1,
0019                 PAGE_SIZE >> EFX_TX_CB_ORDER);
0020 }
0021
0022 int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
0023 {
0024     struct efx_nic *efx = tx_queue->efx;
0025     unsigned int entries;
0026     int rc;
0027
0028     /* Create the smallest power-of-two aligned ring */
0029     entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE);
0030     EFX_WARN_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
0031     tx_queue->ptr_mask = entries - 1;
0032
0033     netif_dbg(efx, probe, efx->net_dev,
0034           "creating TX queue %d size %#x mask %#x\n",
0035           tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
0036
0037     /* Allocate software ring */
0038     tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer),
0039                    GFP_KERNEL);
0040     if (!tx_queue->buffer)
0041         return -ENOMEM;
0042
0043     tx_queue->cb_page = kcalloc(efx_tx_cb_page_count(tx_queue),
0044                     sizeof(tx_queue->cb_page[0]), GFP_KERNEL);
0045     if (!tx_queue->cb_page) {
0046         rc = -ENOMEM;
0047         goto fail1;
0048     }
0049
0050     /* Allocate hardware ring, determine TXQ type */
0051     rc = efx_nic_probe_tx(tx_queue);
0052     if (rc)
0053         goto fail2;
0054
0055     tx_queue->channel->tx_queue_by_type[tx_queue->type] = tx_queue;
0056     return 0;
0057
0058 fail2:
0059     kfree(tx_queue->cb_page);
0060     tx_queue->cb_page = NULL;
0061 fail1:
0062     kfree(tx_queue->buffer);
0063     tx_queue->buffer = NULL;
0064     return rc;
0065 }
0066
0067 void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
0068 {
0069     struct efx_nic *efx = tx_queue->efx;
0070
0071     netif_dbg(efx, drv, efx->net_dev,
0072           "initialising TX queue %d\n", tx_queue->queue);
0073
0074     tx_queue->insert_count = 0;
0075     tx_queue->notify_count = 0;
0076     tx_queue->write_count = 0;
0077     tx_queue->packet_write_count = 0;
0078     tx_queue->old_write_count = 0;
0079     tx_queue->read_count = 0;
0080     tx_queue->old_read_count = 0;
0081     tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID;
0082     tx_queue->xmit_pending = false;
0083     tx_queue->timestamping = (efx_ptp_use_mac_tx_timestamps(efx) &&
0084                   tx_queue->channel == efx_ptp_channel(efx));
0085     tx_queue->completed_timestamp_major = 0;
0086     tx_queue->completed_timestamp_minor = 0;
0087
0088     tx_queue->xdp_tx = efx_channel_is_xdp_tx(tx_queue->channel);
0089     tx_queue->tso_version = 0;
0090
0091     /* Set up TX descriptor ring */
0092     efx_nic_init_tx(tx_queue);
0093
0094     tx_queue->initialised = true;
0095 }
0096
0097 void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
0098 {
0099     struct efx_tx_buffer *buffer;
0100
0101     netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
0102           "shutting down TX queue %d\n", tx_queue->queue);
0103
0104     tx_queue->initialised = false;
0105
0106     if (!tx_queue->buffer)
0107         return;
0108
0109     /* Free any buffers left in the ring */
0110     while (tx_queue->read_count != tx_queue->write_count) {
0111         unsigned int pkts_compl = 0, bytes_compl = 0;
0112         unsigned int efv_pkts_compl = 0;
0113
0114         buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
0115         efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl,
0116                    &efv_pkts_compl);
0117
0118         ++tx_queue->read_count;
0119     }
0120     tx_queue->xmit_pending = false;
0121     netdev_tx_reset_queue(tx_queue->core_txq);
0122 }
0123
0124 void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
0125 {
0126     int i;
0127
0128     if (!tx_queue->buffer)
0129         return;
0130
0131     netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
0132           "destroying TX queue %d\n", tx_queue->queue);
0133     efx_nic_remove_tx(tx_queue);
0134
0135     if (tx_queue->cb_page) {
0136         for (i = 0; i < efx_tx_cb_page_count(tx_queue); i++)
0137             efx_nic_free_buffer(tx_queue->efx,
0138                         &tx_queue->cb_page[i]);
0139         kfree(tx_queue->cb_page);
0140         tx_queue->cb_page = NULL;
0141     }
0142
0143     kfree(tx_queue->buffer);
0144     tx_queue->buffer = NULL;
0145     tx_queue->channel->tx_queue_by_type[tx_queue->type] = NULL;
0146 }
0147
0148 void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
0149             struct efx_tx_buffer *buffer,
0150             unsigned int *pkts_compl,
0151             unsigned int *bytes_compl,
0152             unsigned int *efv_pkts_compl)
0153 {
0154     if (buffer->unmap_len) {
0155         struct device *dma_dev = &tx_queue->efx->pci_dev->dev;
0156         dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset;
0157
0158         if (buffer->flags & EFX_TX_BUF_MAP_SINGLE)
0159             dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len,
0160                      DMA_TO_DEVICE);
0161         else
0162             dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len,
0163                        DMA_TO_DEVICE);
0164         buffer->unmap_len = 0;
0165     }
0166
0167     if (buffer->flags & EFX_TX_BUF_SKB) {
0168         struct sk_buff *skb = (struct sk_buff *)buffer->skb;
0169
0170         if (unlikely(buffer->flags & EFX_TX_BUF_EFV)) {
0171             EFX_WARN_ON_PARANOID(!efv_pkts_compl);
0172             (*efv_pkts_compl)++;
0173         } else {
0174             EFX_WARN_ON_PARANOID(!pkts_compl || !bytes_compl);
0175             (*pkts_compl)++;
0176             (*bytes_compl) += skb->len;
0177         }
0178
0179         if (tx_queue->timestamping &&
0180             (tx_queue->completed_timestamp_major ||
0181              tx_queue->completed_timestamp_minor)) {
0182             struct skb_shared_hwtstamps hwtstamp;
0183
0184             hwtstamp.hwtstamp =
0185                 efx_ptp_nic_to_kernel_time(tx_queue);
0186             skb_tstamp_tx(skb, &hwtstamp);
0187
0188             tx_queue->completed_timestamp_major = 0;
0189             tx_queue->completed_timestamp_minor = 0;
0190         }
0191         dev_consume_skb_any((struct sk_buff *)buffer->skb);
0192         netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
0193                "TX queue %d transmission id %x complete\n",
0194                tx_queue->queue, tx_queue->read_count);
0195     } else if (buffer->flags & EFX_TX_BUF_XDP) {
0196         xdp_return_frame_rx_napi(buffer->xdpf);
0197     }
0198
0199     buffer->len = 0;
0200     buffer->flags = 0;
0201 }
0202
0203 /* Remove packets from the TX queue
0204  *
0205  * This removes packets from the TX queue, up to and including the
0206  * specified index.
0207  */
0208 static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
0209                 unsigned int index,
0210                 unsigned int *pkts_compl,
0211                 unsigned int *bytes_compl,
0212                 unsigned int *efv_pkts_compl)
0213 {
0214     struct efx_nic *efx = tx_queue->efx;
0215     unsigned int stop_index, read_ptr;
0216
0217     stop_index = (index + 1) & tx_queue->ptr_mask;
0218     read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
0219
0220     while (read_ptr != stop_index) {
0221         struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
0222
0223         if (!efx_tx_buffer_in_use(buffer)) {
0224             netif_err(efx, tx_err, efx->net_dev,
0225                   "TX queue %d spurious TX completion id %d\n",
0226                   tx_queue->queue, read_ptr);
0227             efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
0228             return;
0229         }
0230
0231         efx_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl,
0232                    efv_pkts_compl);
0233
0234         ++tx_queue->read_count;
0235         read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
0236     }
0237 }
0238
0239 void efx_xmit_done_check_empty(struct efx_tx_queue *tx_queue)
0240 {
0241     if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) {
0242         tx_queue->old_write_count = READ_ONCE(tx_queue->write_count);
0243         if (tx_queue->read_count == tx_queue->old_write_count) {
0244             /* Ensure that read_count is flushed. */
0245             smp_mb();
0246             tx_queue->empty_read_count =
0247                 tx_queue->read_count | EFX_EMPTY_COUNT_VALID;
0248         }
0249     }
0250 }
0251
0252 void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
0253 {
0254     unsigned int fill_level, pkts_compl = 0, bytes_compl = 0;
0255     unsigned int efv_pkts_compl = 0;
0256     struct efx_nic *efx = tx_queue->efx;
0257
0258     EFX_WARN_ON_ONCE_PARANOID(index > tx_queue->ptr_mask);
0259
0260     efx_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl,
0261                 &efv_pkts_compl);
0262     tx_queue->pkts_compl += pkts_compl;
0263     tx_queue->bytes_compl += bytes_compl;
0264
0265     if (pkts_compl + efv_pkts_compl > 1)
0266         ++tx_queue->merge_events;
0267
0268     /* See if we need to restart the netif queue.  This memory
0269      * barrier ensures that we write read_count (inside
0270      * efx_dequeue_buffers()) before reading the queue status.
0271      */
0272     smp_mb();
0273     if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) &&
0274         likely(efx->port_enabled) &&
0275         likely(netif_device_present(efx->net_dev))) {
0276         fill_level = efx_channel_tx_fill_level(tx_queue->channel);
0277         if (fill_level <= efx->txq_wake_thresh)
0278             netif_tx_wake_queue(tx_queue->core_txq);
0279     }
0280
0281     efx_xmit_done_check_empty(tx_queue);
0282 }
0283
0284 /* Remove buffers put into a tx_queue for the current packet.
0285  * None of the buffers must have an skb attached.
0286  */
0287 void efx_enqueue_unwind(struct efx_tx_queue *tx_queue,
0288             unsigned int insert_count)
0289 {
0290     unsigned int efv_pkts_compl = 0;
0291     struct efx_tx_buffer *buffer;
0292     unsigned int bytes_compl = 0;
0293     unsigned int pkts_compl = 0;
0294
0295     /* Work backwards until we hit the original insert pointer value */
0296     while (tx_queue->insert_count != insert_count) {
0297         --tx_queue->insert_count;
0298         buffer = __efx_tx_queue_get_insert_buffer(tx_queue);
0299         efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl,
0300                    &efv_pkts_compl);
0301     }
0302 }
0303
0304 struct efx_tx_buffer *efx_tx_map_chunk(struct efx_tx_queue *tx_queue,
0305                        dma_addr_t dma_addr, size_t len)
0306 {
0307     const struct efx_nic_type *nic_type = tx_queue->efx->type;
0308     struct efx_tx_buffer *buffer;
0309     unsigned int dma_len;
0310
0311     /* Map the fragment taking account of NIC-dependent DMA limits. */
0312     do {
0313         buffer = efx_tx_queue_get_insert_buffer(tx_queue);
0314
0315         if (nic_type->tx_limit_len)
0316             dma_len = nic_type->tx_limit_len(tx_queue, dma_addr, len);
0317         else
0318             dma_len = len;
0319
0320         buffer->len = dma_len;
0321         buffer->dma_addr = dma_addr;
0322         buffer->flags = EFX_TX_BUF_CONT;
0323         len -= dma_len;
0324         dma_addr += dma_len;
0325         ++tx_queue->insert_count;
0326     } while (len);
0327
0328     return buffer;
0329 }
0330
0331 int efx_tx_tso_header_length(struct sk_buff *skb)
0332 {
0333     size_t header_len;
0334
0335     if (skb->encapsulation)
0336         header_len = skb_inner_transport_header(skb) -
0337                 skb->data +
0338                 (inner_tcp_hdr(skb)->doff << 2u);
0339     else
0340         header_len = skb_transport_header(skb) - skb->data +
0341                 (tcp_hdr(skb)->doff << 2u);
0342     return header_len;
0343 }
0344
0345 /* Map all data from an SKB for DMA and create descriptors on the queue. */
0346 int efx_tx_map_data(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
0347             unsigned int segment_count)
0348 {
0349     struct efx_nic *efx = tx_queue->efx;
0350     struct device *dma_dev = &efx->pci_dev->dev;
0351     unsigned int frag_index, nr_frags;
0352     dma_addr_t dma_addr, unmap_addr;
0353     unsigned short dma_flags;
0354     size_t len, unmap_len;
0355
0356     nr_frags = skb_shinfo(skb)->nr_frags;
0357     frag_index = 0;
0358
0359     /* Map header data. */
0360     len = skb_headlen(skb);
0361     dma_addr = dma_map_single(dma_dev, skb->data, len, DMA_TO_DEVICE);
0362     dma_flags = EFX_TX_BUF_MAP_SINGLE;
0363     unmap_len = len;
0364     unmap_addr = dma_addr;
0365
0366     if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
0367         return -EIO;
0368
0369     if (segment_count) {
0370         /* For TSO we need to put the header in to a separate
0371          * descriptor. Map this separately if necessary.
0372          */
0373         size_t header_len = efx_tx_tso_header_length(skb);
0374
0375         if (header_len != len) {
0376             tx_queue->tso_long_headers++;
0377             efx_tx_map_chunk(tx_queue, dma_addr, header_len);
0378             len -= header_len;
0379             dma_addr += header_len;
0380         }
0381     }
0382
0383     /* Add descriptors for each fragment. */
0384     do {
0385         struct efx_tx_buffer *buffer;
0386         skb_frag_t *fragment;
0387
0388         buffer = efx_tx_map_chunk(tx_queue, dma_addr, len);
0389
0390         /* The final descriptor for a fragment is responsible for
0391          * unmapping the whole fragment.
0392          */
0393         buffer->flags = EFX_TX_BUF_CONT | dma_flags;
0394         buffer->unmap_len = unmap_len;
0395         buffer->dma_offset = buffer->dma_addr - unmap_addr;
0396
0397         if (frag_index >= nr_frags) {
0398             /* Store SKB details with the final buffer for
0399              * the completion.
0400              */
0401             buffer->skb = skb;
0402             buffer->flags = EFX_TX_BUF_SKB | dma_flags;
0403             return 0;
0404         }
0405
0406         /* Move on to the next fragment. */
0407         fragment = &skb_shinfo(skb)->frags[frag_index++];
0408         len = skb_frag_size(fragment);
0409         dma_addr = skb_frag_dma_map(dma_dev, fragment, 0, len,
0410                         DMA_TO_DEVICE);
0411         dma_flags = 0;
0412         unmap_len = len;
0413         unmap_addr = dma_addr;
0414
0415         if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
0416             return -EIO;
0417     } while (1);
0418 }
0419
0420 unsigned int efx_tx_max_skb_descs(struct efx_nic *efx)
0421 {
0422     /* Header and payload descriptor for each output segment, plus
0423      * one for every input fragment boundary within a segment
0424      */
0425     unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS;
0426
0427     /* Possibly one more per segment for option descriptors */
0428     if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
0429         max_descs += EFX_TSO_MAX_SEGS;
0430
0431     /* Possibly more for PCIe page boundaries within input fragments */
0432     if (PAGE_SIZE > EFX_PAGE_SIZE)
0433         max_descs += max_t(unsigned int, MAX_SKB_FRAGS,
0434                    DIV_ROUND_UP(GSO_LEGACY_MAX_SIZE,
0435                         EFX_PAGE_SIZE));
0436
0437     return max_descs;
0438 }
0439
0440 /*
0441  * Fallback to software TSO.
0442  *
0443  * This is used if we are unable to send a GSO packet through hardware TSO.
0444  * This should only ever happen due to per-queue restrictions - unsupported
0445  * packets should first be filtered by the feature flags.
0446  *
0447  * Returns 0 on success, error code otherwise.
0448  */
0449 int efx_tx_tso_fallback(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
0450 {
0451     struct sk_buff *segments, *next;
0452
0453     segments = skb_gso_segment(skb, 0);
0454     if (IS_ERR(segments))
0455         return PTR_ERR(segments);
0456
0457     dev_consume_skb_any(skb);
0458
0459     skb_list_walk_safe(segments, skb, next) {
0460         skb_mark_not_on_list(skb);
0461         efx_enqueue_skb(tx_queue, skb);
0462     }
0463
0464     return 0;
0465 }