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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /****************************************************************************
0003  * Driver for Solarflare network controllers and boards
0004  * Copyright 2005-2006 Fen Systems Ltd.
0005  * Copyright 2005-2013 Solarflare Communications Inc.
0006  */
0007 
0008 #include <linux/pci.h>
0009 #include <linux/tcp.h>
0010 #include <linux/ip.h>
0011 #include <linux/in.h>
0012 #include <linux/ipv6.h>
0013 #include <linux/slab.h>
0014 #include <net/ipv6.h>
0015 #include <linux/if_ether.h>
0016 #include <linux/highmem.h>
0017 #include <linux/cache.h>
0018 #include "net_driver.h"
0019 #include "efx.h"
0020 #include "io.h"
0021 #include "nic.h"
0022 #include "tx.h"
0023 #include "tx_common.h"
0024 #include "workarounds.h"
0025 #include "ef10_regs.h"
0026 
0027 #ifdef EFX_USE_PIO
0028 
0029 #define EFX_PIOBUF_SIZE_DEF ALIGN(256, L1_CACHE_BYTES)
0030 unsigned int efx_piobuf_size __read_mostly = EFX_PIOBUF_SIZE_DEF;
0031 
0032 #endif /* EFX_USE_PIO */
0033 
0034 static inline u8 *efx_tx_get_copy_buffer(struct efx_tx_queue *tx_queue,
0035                      struct efx_tx_buffer *buffer)
0036 {
0037     unsigned int index = efx_tx_queue_get_insert_index(tx_queue);
0038     struct efx_buffer *page_buf =
0039         &tx_queue->cb_page[index >> (PAGE_SHIFT - EFX_TX_CB_ORDER)];
0040     unsigned int offset =
0041         ((index << EFX_TX_CB_ORDER) + NET_IP_ALIGN) & (PAGE_SIZE - 1);
0042 
0043     if (unlikely(!page_buf->addr) &&
0044         efx_nic_alloc_buffer(tx_queue->efx, page_buf, PAGE_SIZE,
0045                  GFP_ATOMIC))
0046         return NULL;
0047     buffer->dma_addr = page_buf->dma_addr + offset;
0048     buffer->unmap_len = 0;
0049     return (u8 *)page_buf->addr + offset;
0050 }
0051 
0052 u8 *efx_tx_get_copy_buffer_limited(struct efx_tx_queue *tx_queue,
0053                    struct efx_tx_buffer *buffer, size_t len)
0054 {
0055     if (len > EFX_TX_CB_SIZE)
0056         return NULL;
0057     return efx_tx_get_copy_buffer(tx_queue, buffer);
0058 }
0059 
0060 static void efx_tx_maybe_stop_queue(struct efx_tx_queue *txq1)
0061 {
0062     /* We need to consider all queues that the net core sees as one */
0063     struct efx_nic *efx = txq1->efx;
0064     struct efx_tx_queue *txq2;
0065     unsigned int fill_level;
0066 
0067     fill_level = efx_channel_tx_old_fill_level(txq1->channel);
0068     if (likely(fill_level < efx->txq_stop_thresh))
0069         return;
0070 
0071     /* We used the stale old_read_count above, which gives us a
0072      * pessimistic estimate of the fill level (which may even
0073      * validly be >= efx->txq_entries).  Now try again using
0074      * read_count (more likely to be a cache miss).
0075      *
0076      * If we read read_count and then conditionally stop the
0077      * queue, it is possible for the completion path to race with
0078      * us and complete all outstanding descriptors in the middle,
0079      * after which there will be no more completions to wake it.
0080      * Therefore we stop the queue first, then read read_count
0081      * (with a memory barrier to ensure the ordering), then
0082      * restart the queue if the fill level turns out to be low
0083      * enough.
0084      */
0085     netif_tx_stop_queue(txq1->core_txq);
0086     smp_mb();
0087     efx_for_each_channel_tx_queue(txq2, txq1->channel)
0088         txq2->old_read_count = READ_ONCE(txq2->read_count);
0089 
0090     fill_level = efx_channel_tx_old_fill_level(txq1->channel);
0091     EFX_WARN_ON_ONCE_PARANOID(fill_level >= efx->txq_entries);
0092     if (likely(fill_level < efx->txq_stop_thresh)) {
0093         smp_mb();
0094         if (likely(!efx->loopback_selftest))
0095             netif_tx_start_queue(txq1->core_txq);
0096     }
0097 }
0098 
0099 static int efx_enqueue_skb_copy(struct efx_tx_queue *tx_queue,
0100                 struct sk_buff *skb)
0101 {
0102     unsigned int copy_len = skb->len;
0103     struct efx_tx_buffer *buffer;
0104     u8 *copy_buffer;
0105     int rc;
0106 
0107     EFX_WARN_ON_ONCE_PARANOID(copy_len > EFX_TX_CB_SIZE);
0108 
0109     buffer = efx_tx_queue_get_insert_buffer(tx_queue);
0110 
0111     copy_buffer = efx_tx_get_copy_buffer(tx_queue, buffer);
0112     if (unlikely(!copy_buffer))
0113         return -ENOMEM;
0114 
0115     rc = skb_copy_bits(skb, 0, copy_buffer, copy_len);
0116     EFX_WARN_ON_PARANOID(rc);
0117     buffer->len = copy_len;
0118 
0119     buffer->skb = skb;
0120     buffer->flags = EFX_TX_BUF_SKB;
0121 
0122     ++tx_queue->insert_count;
0123     return rc;
0124 }
0125 
0126 #ifdef EFX_USE_PIO
0127 
0128 struct efx_short_copy_buffer {
0129     int used;
0130     u8 buf[L1_CACHE_BYTES];
0131 };
0132 
0133 /* Copy to PIO, respecting that writes to PIO buffers must be dword aligned.
0134  * Advances piobuf pointer. Leaves additional data in the copy buffer.
0135  */
0136 static void efx_memcpy_toio_aligned(struct efx_nic *efx, u8 __iomem **piobuf,
0137                     u8 *data, int len,
0138                     struct efx_short_copy_buffer *copy_buf)
0139 {
0140     int block_len = len & ~(sizeof(copy_buf->buf) - 1);
0141 
0142     __iowrite64_copy(*piobuf, data, block_len >> 3);
0143     *piobuf += block_len;
0144     len -= block_len;
0145 
0146     if (len) {
0147         data += block_len;
0148         BUG_ON(copy_buf->used);
0149         BUG_ON(len > sizeof(copy_buf->buf));
0150         memcpy(copy_buf->buf, data, len);
0151         copy_buf->used = len;
0152     }
0153 }
0154 
0155 /* Copy to PIO, respecting dword alignment, popping data from copy buffer first.
0156  * Advances piobuf pointer. Leaves additional data in the copy buffer.
0157  */
0158 static void efx_memcpy_toio_aligned_cb(struct efx_nic *efx, u8 __iomem **piobuf,
0159                        u8 *data, int len,
0160                        struct efx_short_copy_buffer *copy_buf)
0161 {
0162     if (copy_buf->used) {
0163         /* if the copy buffer is partially full, fill it up and write */
0164         int copy_to_buf =
0165             min_t(int, sizeof(copy_buf->buf) - copy_buf->used, len);
0166 
0167         memcpy(copy_buf->buf + copy_buf->used, data, copy_to_buf);
0168         copy_buf->used += copy_to_buf;
0169 
0170         /* if we didn't fill it up then we're done for now */
0171         if (copy_buf->used < sizeof(copy_buf->buf))
0172             return;
0173 
0174         __iowrite64_copy(*piobuf, copy_buf->buf,
0175                  sizeof(copy_buf->buf) >> 3);
0176         *piobuf += sizeof(copy_buf->buf);
0177         data += copy_to_buf;
0178         len -= copy_to_buf;
0179         copy_buf->used = 0;
0180     }
0181 
0182     efx_memcpy_toio_aligned(efx, piobuf, data, len, copy_buf);
0183 }
0184 
0185 static void efx_flush_copy_buffer(struct efx_nic *efx, u8 __iomem *piobuf,
0186                   struct efx_short_copy_buffer *copy_buf)
0187 {
0188     /* if there's anything in it, write the whole buffer, including junk */
0189     if (copy_buf->used)
0190         __iowrite64_copy(piobuf, copy_buf->buf,
0191                  sizeof(copy_buf->buf) >> 3);
0192 }
0193 
0194 /* Traverse skb structure and copy fragments in to PIO buffer.
0195  * Advances piobuf pointer.
0196  */
0197 static void efx_skb_copy_bits_to_pio(struct efx_nic *efx, struct sk_buff *skb,
0198                      u8 __iomem **piobuf,
0199                      struct efx_short_copy_buffer *copy_buf)
0200 {
0201     int i;
0202 
0203     efx_memcpy_toio_aligned(efx, piobuf, skb->data, skb_headlen(skb),
0204                 copy_buf);
0205 
0206     for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) {
0207         skb_frag_t *f = &skb_shinfo(skb)->frags[i];
0208         u8 *vaddr;
0209 
0210         vaddr = kmap_atomic(skb_frag_page(f));
0211 
0212         efx_memcpy_toio_aligned_cb(efx, piobuf, vaddr + skb_frag_off(f),
0213                        skb_frag_size(f), copy_buf);
0214         kunmap_atomic(vaddr);
0215     }
0216 
0217     EFX_WARN_ON_ONCE_PARANOID(skb_shinfo(skb)->frag_list);
0218 }
0219 
0220 static int efx_enqueue_skb_pio(struct efx_tx_queue *tx_queue,
0221                    struct sk_buff *skb)
0222 {
0223     struct efx_tx_buffer *buffer =
0224         efx_tx_queue_get_insert_buffer(tx_queue);
0225     u8 __iomem *piobuf = tx_queue->piobuf;
0226 
0227     /* Copy to PIO buffer. Ensure the writes are padded to the end
0228      * of a cache line, as this is required for write-combining to be
0229      * effective on at least x86.
0230      */
0231 
0232     if (skb_shinfo(skb)->nr_frags) {
0233         /* The size of the copy buffer will ensure all writes
0234          * are the size of a cache line.
0235          */
0236         struct efx_short_copy_buffer copy_buf;
0237 
0238         copy_buf.used = 0;
0239 
0240         efx_skb_copy_bits_to_pio(tx_queue->efx, skb,
0241                      &piobuf, &copy_buf);
0242         efx_flush_copy_buffer(tx_queue->efx, piobuf, &copy_buf);
0243     } else {
0244         /* Pad the write to the size of a cache line.
0245          * We can do this because we know the skb_shared_info struct is
0246          * after the source, and the destination buffer is big enough.
0247          */
0248         BUILD_BUG_ON(L1_CACHE_BYTES >
0249                  SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
0250         __iowrite64_copy(tx_queue->piobuf, skb->data,
0251                  ALIGN(skb->len, L1_CACHE_BYTES) >> 3);
0252     }
0253 
0254     buffer->skb = skb;
0255     buffer->flags = EFX_TX_BUF_SKB | EFX_TX_BUF_OPTION;
0256 
0257     EFX_POPULATE_QWORD_5(buffer->option,
0258                  ESF_DZ_TX_DESC_IS_OPT, 1,
0259                  ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_PIO,
0260                  ESF_DZ_TX_PIO_CONT, 0,
0261                  ESF_DZ_TX_PIO_BYTE_CNT, skb->len,
0262                  ESF_DZ_TX_PIO_BUF_ADDR,
0263                  tx_queue->piobuf_offset);
0264     ++tx_queue->insert_count;
0265     return 0;
0266 }
0267 
0268 /* Decide whether we can use TX PIO, ie. write packet data directly into
0269  * a buffer on the device.  This can reduce latency at the expense of
0270  * throughput, so we only do this if both hardware and software TX rings
0271  * are empty, including all queues for the channel.  This also ensures that
0272  * only one packet at a time can be using the PIO buffer. If the xmit_more
0273  * flag is set then we don't use this - there'll be another packet along
0274  * shortly and we want to hold off the doorbell.
0275  */
0276 static bool efx_tx_may_pio(struct efx_tx_queue *tx_queue)
0277 {
0278     struct efx_channel *channel = tx_queue->channel;
0279 
0280     if (!tx_queue->piobuf)
0281         return false;
0282 
0283     EFX_WARN_ON_ONCE_PARANOID(!channel->efx->type->option_descriptors);
0284 
0285     efx_for_each_channel_tx_queue(tx_queue, channel)
0286         if (!efx_nic_tx_is_empty(tx_queue, tx_queue->packet_write_count))
0287             return false;
0288 
0289     return true;
0290 }
0291 #endif /* EFX_USE_PIO */
0292 
0293 /* Send any pending traffic for a channel. xmit_more is shared across all
0294  * queues for a channel, so we must check all of them.
0295  */
0296 static void efx_tx_send_pending(struct efx_channel *channel)
0297 {
0298     struct efx_tx_queue *q;
0299 
0300     efx_for_each_channel_tx_queue(q, channel) {
0301         if (q->xmit_pending)
0302             efx_nic_push_buffers(q);
0303     }
0304 }
0305 
0306 /*
0307  * Add a socket buffer to a TX queue
0308  *
0309  * This maps all fragments of a socket buffer for DMA and adds them to
0310  * the TX queue.  The queue's insert pointer will be incremented by
0311  * the number of fragments in the socket buffer.
0312  *
0313  * If any DMA mapping fails, any mapped fragments will be unmapped,
0314  * the queue's insert pointer will be restored to its original value.
0315  *
0316  * This function is split out from efx_hard_start_xmit to allow the
0317  * loopback test to direct packets via specific TX queues.
0318  *
0319  * Returns NETDEV_TX_OK.
0320  * You must hold netif_tx_lock() to call this function.
0321  */
0322 netdev_tx_t __efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
0323 {
0324     unsigned int old_insert_count = tx_queue->insert_count;
0325     bool xmit_more = netdev_xmit_more();
0326     bool data_mapped = false;
0327     unsigned int segments;
0328     unsigned int skb_len;
0329     int rc;
0330 
0331     skb_len = skb->len;
0332     segments = skb_is_gso(skb) ? skb_shinfo(skb)->gso_segs : 0;
0333     if (segments == 1)
0334         segments = 0; /* Don't use TSO for a single segment. */
0335 
0336     /* Handle TSO first - it's *possible* (although unlikely) that we might
0337      * be passed a packet to segment that's smaller than the copybreak/PIO
0338      * size limit.
0339      */
0340     if (segments) {
0341         switch (tx_queue->tso_version) {
0342         case 1:
0343             rc = efx_enqueue_skb_tso(tx_queue, skb, &data_mapped);
0344             break;
0345         case 2:
0346             rc = efx_ef10_tx_tso_desc(tx_queue, skb, &data_mapped);
0347             break;
0348         case 0: /* No TSO on this queue, SW fallback needed */
0349         default:
0350             rc = -EINVAL;
0351             break;
0352         }
0353         if (rc == -EINVAL) {
0354             rc = efx_tx_tso_fallback(tx_queue, skb);
0355             tx_queue->tso_fallbacks++;
0356             if (rc == 0)
0357                 return 0;
0358         }
0359         if (rc)
0360             goto err;
0361 #ifdef EFX_USE_PIO
0362     } else if (skb_len <= efx_piobuf_size && !xmit_more &&
0363            efx_tx_may_pio(tx_queue)) {
0364         /* Use PIO for short packets with an empty queue. */
0365         if (efx_enqueue_skb_pio(tx_queue, skb))
0366             goto err;
0367         tx_queue->pio_packets++;
0368         data_mapped = true;
0369 #endif
0370     } else if (skb->data_len && skb_len <= EFX_TX_CB_SIZE) {
0371         /* Pad short packets or coalesce short fragmented packets. */
0372         if (efx_enqueue_skb_copy(tx_queue, skb))
0373             goto err;
0374         tx_queue->cb_packets++;
0375         data_mapped = true;
0376     }
0377 
0378     /* Map for DMA and create descriptors if we haven't done so already. */
0379     if (!data_mapped && (efx_tx_map_data(tx_queue, skb, segments)))
0380         goto err;
0381 
0382     efx_tx_maybe_stop_queue(tx_queue);
0383 
0384     tx_queue->xmit_pending = true;
0385 
0386     /* Pass off to hardware */
0387     if (__netdev_tx_sent_queue(tx_queue->core_txq, skb_len, xmit_more))
0388         efx_tx_send_pending(tx_queue->channel);
0389 
0390     if (segments) {
0391         tx_queue->tso_bursts++;
0392         tx_queue->tso_packets += segments;
0393         tx_queue->tx_packets  += segments;
0394     } else {
0395         tx_queue->tx_packets++;
0396     }
0397 
0398     return NETDEV_TX_OK;
0399 
0400 
0401 err:
0402     efx_enqueue_unwind(tx_queue, old_insert_count);
0403     dev_kfree_skb_any(skb);
0404 
0405     /* If we're not expecting another transmit and we had something to push
0406      * on this queue or a partner queue then we need to push here to get the
0407      * previous packets out.
0408      */
0409     if (!xmit_more)
0410         efx_tx_send_pending(tx_queue->channel);
0411 
0412     return NETDEV_TX_OK;
0413 }
0414 
0415 /* Transmit a packet from an XDP buffer
0416  *
0417  * Returns number of packets sent on success, error code otherwise.
0418  * Runs in NAPI context, either in our poll (for XDP TX) or a different NIC
0419  * (for XDP redirect).
0420  */
0421 int efx_xdp_tx_buffers(struct efx_nic *efx, int n, struct xdp_frame **xdpfs,
0422                bool flush)
0423 {
0424     struct efx_tx_buffer *tx_buffer;
0425     struct efx_tx_queue *tx_queue;
0426     struct xdp_frame *xdpf;
0427     dma_addr_t dma_addr;
0428     unsigned int len;
0429     int space;
0430     int cpu;
0431     int i = 0;
0432 
0433     if (unlikely(n && !xdpfs))
0434         return -EINVAL;
0435     if (unlikely(!n))
0436         return 0;
0437 
0438     cpu = raw_smp_processor_id();
0439     if (unlikely(cpu >= efx->xdp_tx_queue_count))
0440         return -EINVAL;
0441 
0442     tx_queue = efx->xdp_tx_queues[cpu];
0443     if (unlikely(!tx_queue))
0444         return -EINVAL;
0445 
0446     if (!tx_queue->initialised)
0447         return -EINVAL;
0448 
0449     if (efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_DEDICATED)
0450         HARD_TX_LOCK(efx->net_dev, tx_queue->core_txq, cpu);
0451 
0452     /* If we're borrowing net stack queues we have to handle stop-restart
0453      * or we might block the queue and it will be considered as frozen
0454      */
0455     if (efx->xdp_txq_queues_mode == EFX_XDP_TX_QUEUES_BORROWED) {
0456         if (netif_tx_queue_stopped(tx_queue->core_txq))
0457             goto unlock;
0458         efx_tx_maybe_stop_queue(tx_queue);
0459     }
0460 
0461     /* Check for available space. We should never need multiple
0462      * descriptors per frame.
0463      */
0464     space = efx->txq_entries +
0465         tx_queue->read_count - tx_queue->insert_count;
0466 
0467     for (i = 0; i < n; i++) {
0468         xdpf = xdpfs[i];
0469 
0470         if (i >= space)
0471             break;
0472 
0473         /* We'll want a descriptor for this tx. */
0474         prefetchw(__efx_tx_queue_get_insert_buffer(tx_queue));
0475 
0476         len = xdpf->len;
0477 
0478         /* Map for DMA. */
0479         dma_addr = dma_map_single(&efx->pci_dev->dev,
0480                       xdpf->data, len,
0481                       DMA_TO_DEVICE);
0482         if (dma_mapping_error(&efx->pci_dev->dev, dma_addr))
0483             break;
0484 
0485         /*  Create descriptor and set up for unmapping DMA. */
0486         tx_buffer = efx_tx_map_chunk(tx_queue, dma_addr, len);
0487         tx_buffer->xdpf = xdpf;
0488         tx_buffer->flags = EFX_TX_BUF_XDP |
0489                    EFX_TX_BUF_MAP_SINGLE;
0490         tx_buffer->dma_offset = 0;
0491         tx_buffer->unmap_len = len;
0492         tx_queue->tx_packets++;
0493     }
0494 
0495     /* Pass mapped frames to hardware. */
0496     if (flush && i > 0)
0497         efx_nic_push_buffers(tx_queue);
0498 
0499 unlock:
0500     if (efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_DEDICATED)
0501         HARD_TX_UNLOCK(efx->net_dev, tx_queue->core_txq);
0502 
0503     return i == 0 ? -EIO : i;
0504 }
0505 
0506 /* Initiate a packet transmission.  We use one channel per CPU
0507  * (sharing when we have more CPUs than channels).
0508  *
0509  * Context: non-blocking.
0510  * Should always return NETDEV_TX_OK and consume the skb.
0511  */
0512 netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
0513                 struct net_device *net_dev)
0514 {
0515     struct efx_nic *efx = efx_netdev_priv(net_dev);
0516     struct efx_tx_queue *tx_queue;
0517     unsigned index, type;
0518 
0519     EFX_WARN_ON_PARANOID(!netif_device_present(net_dev));
0520 
0521     index = skb_get_queue_mapping(skb);
0522     type = efx_tx_csum_type_skb(skb);
0523     if (index >= efx->n_tx_channels) {
0524         index -= efx->n_tx_channels;
0525         type |= EFX_TXQ_TYPE_HIGHPRI;
0526     }
0527 
0528     /* PTP "event" packet */
0529     if (unlikely(efx_xmit_with_hwtstamp(skb)) &&
0530         ((efx_ptp_use_mac_tx_timestamps(efx) && efx->ptp_data) ||
0531         unlikely(efx_ptp_is_ptp_tx(efx, skb)))) {
0532         /* There may be existing transmits on the channel that are
0533          * waiting for this packet to trigger the doorbell write.
0534          * We need to send the packets at this point.
0535          */
0536         efx_tx_send_pending(efx_get_tx_channel(efx, index));
0537         return efx_ptp_tx(efx, skb);
0538     }
0539 
0540     tx_queue = efx_get_tx_queue(efx, index, type);
0541     if (WARN_ON_ONCE(!tx_queue)) {
0542         /* We don't have a TXQ of the right type.
0543          * This should never happen, as we don't advertise offload
0544          * features unless we can support them.
0545          */
0546         dev_kfree_skb_any(skb);
0547         /* If we're not expecting another transmit and we had something to push
0548          * on this queue or a partner queue then we need to push here to get the
0549          * previous packets out.
0550          */
0551         if (!netdev_xmit_more())
0552             efx_tx_send_pending(efx_get_tx_channel(efx, index));
0553         return NETDEV_TX_OK;
0554     }
0555 
0556     return __efx_enqueue_skb(tx_queue, skb);
0557 }
0558 
0559 void efx_xmit_done_single(struct efx_tx_queue *tx_queue)
0560 {
0561     unsigned int pkts_compl = 0, bytes_compl = 0;
0562     unsigned int efv_pkts_compl = 0;
0563     unsigned int read_ptr;
0564     bool finished = false;
0565 
0566     read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
0567 
0568     while (!finished) {
0569         struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
0570 
0571         if (!efx_tx_buffer_in_use(buffer)) {
0572             struct efx_nic *efx = tx_queue->efx;
0573 
0574             netif_err(efx, hw, efx->net_dev,
0575                   "TX queue %d spurious single TX completion\n",
0576                   tx_queue->queue);
0577             efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
0578             return;
0579         }
0580 
0581         /* Need to check the flag before dequeueing. */
0582         if (buffer->flags & EFX_TX_BUF_SKB)
0583             finished = true;
0584         efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl,
0585                    &efv_pkts_compl);
0586 
0587         ++tx_queue->read_count;
0588         read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
0589     }
0590 
0591     tx_queue->pkts_compl += pkts_compl;
0592     tx_queue->bytes_compl += bytes_compl;
0593 
0594     EFX_WARN_ON_PARANOID(pkts_compl + efv_pkts_compl != 1);
0595 
0596     efx_xmit_done_check_empty(tx_queue);
0597 }
0598 
0599 void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue)
0600 {
0601     struct efx_nic *efx = tx_queue->efx;
0602 
0603     /* Must be inverse of queue lookup in efx_hard_start_xmit() */
0604     tx_queue->core_txq =
0605         netdev_get_tx_queue(efx->net_dev,
0606                     tx_queue->channel->channel +
0607                     ((tx_queue->type & EFX_TXQ_TYPE_HIGHPRI) ?
0608                      efx->n_tx_channels : 0));
0609 }
0610 
0611 int efx_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
0612          void *type_data)
0613 {
0614     struct efx_nic *efx = efx_netdev_priv(net_dev);
0615     struct tc_mqprio_qopt *mqprio = type_data;
0616     unsigned tc, num_tc;
0617 
0618     if (type != TC_SETUP_QDISC_MQPRIO)
0619         return -EOPNOTSUPP;
0620 
0621     /* Only Siena supported highpri queues */
0622     if (efx_nic_rev(efx) > EFX_REV_SIENA_A0)
0623         return -EOPNOTSUPP;
0624 
0625     num_tc = mqprio->num_tc;
0626 
0627     if (num_tc > EFX_MAX_TX_TC)
0628         return -EINVAL;
0629 
0630     mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
0631 
0632     if (num_tc == net_dev->num_tc)
0633         return 0;
0634 
0635     for (tc = 0; tc < num_tc; tc++) {
0636         net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels;
0637         net_dev->tc_to_txq[tc].count = efx->n_tx_channels;
0638     }
0639 
0640     net_dev->num_tc = num_tc;
0641 
0642     return netif_set_real_num_tx_queues(net_dev,
0643                         max_t(int, num_tc, 1) *
0644                         efx->n_tx_channels);
0645 }
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