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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /****************************************************************************
0003  * Driver for Solarflare network controllers and boards
0004  * Copyright 2005-2006 Fen Systems Ltd.
0005  * Copyright 2006-2013 Solarflare Communications Inc.
0006  */
0007 
0008 #include <linux/bitops.h>
0009 #include <linux/delay.h>
0010 #include <linux/pci.h>
0011 #include <linux/module.h>
0012 #include <linux/slab.h>
0013 #include <linux/random.h>
0014 #include "net_driver.h"
0015 #include "bitfield.h"
0016 #include "efx.h"
0017 #include "efx_common.h"
0018 #include "nic.h"
0019 #include "farch_regs.h"
0020 #include "io.h"
0021 #include "workarounds.h"
0022 #include "mcdi.h"
0023 #include "mcdi_pcol.h"
0024 #include "mcdi_port.h"
0025 #include "mcdi_port_common.h"
0026 #include "selftest.h"
0027 #include "siena_sriov.h"
0028 #include "rx_common.h"
0029 
0030 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
0031 
0032 static void siena_init_wol(struct efx_nic *efx);
0033 
0034 
0035 static void siena_push_irq_moderation(struct efx_channel *channel)
0036 {
0037     struct efx_nic *efx = channel->efx;
0038     efx_dword_t timer_cmd;
0039 
0040     if (channel->irq_moderation_us) {
0041         unsigned int ticks;
0042 
0043         ticks = efx_siena_usecs_to_ticks(efx, channel->irq_moderation_us);
0044         EFX_POPULATE_DWORD_2(timer_cmd,
0045                      FRF_CZ_TC_TIMER_MODE,
0046                      FFE_CZ_TIMER_MODE_INT_HLDOFF,
0047                      FRF_CZ_TC_TIMER_VAL,
0048                      ticks - 1);
0049     } else {
0050         EFX_POPULATE_DWORD_2(timer_cmd,
0051                      FRF_CZ_TC_TIMER_MODE,
0052                      FFE_CZ_TIMER_MODE_DIS,
0053                      FRF_CZ_TC_TIMER_VAL, 0);
0054     }
0055     efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
0056                    channel->channel);
0057 }
0058 
0059 void efx_siena_prepare_flush(struct efx_nic *efx)
0060 {
0061     if (efx->fc_disable++ == 0)
0062         efx_siena_mcdi_set_mac(efx);
0063 }
0064 
0065 void siena_finish_flush(struct efx_nic *efx)
0066 {
0067     if (--efx->fc_disable == 0)
0068         efx_siena_mcdi_set_mac(efx);
0069 }
0070 
0071 static const struct efx_farch_register_test siena_register_tests[] = {
0072     { FR_AZ_ADR_REGION,
0073       EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
0074     { FR_CZ_USR_EV_CFG,
0075       EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
0076     { FR_AZ_RX_CFG,
0077       EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
0078     { FR_AZ_TX_CFG,
0079       EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
0080     { FR_AZ_TX_RESERVED,
0081       EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
0082     { FR_AZ_SRM_TX_DC_CFG,
0083       EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
0084     { FR_AZ_RX_DC_CFG,
0085       EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
0086     { FR_AZ_RX_DC_PF_WM,
0087       EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
0088     { FR_BZ_DP_CTRL,
0089       EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
0090     { FR_BZ_RX_RSS_TKEY,
0091       EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
0092     { FR_CZ_RX_RSS_IPV6_REG1,
0093       EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
0094     { FR_CZ_RX_RSS_IPV6_REG2,
0095       EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
0096     { FR_CZ_RX_RSS_IPV6_REG3,
0097       EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
0098 };
0099 
0100 static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
0101 {
0102     enum reset_type reset_method = RESET_TYPE_ALL;
0103     int rc, rc2;
0104 
0105     efx_siena_reset_down(efx, reset_method);
0106 
0107     /* Reset the chip immediately so that it is completely
0108      * quiescent regardless of what any VF driver does.
0109      */
0110     rc = efx_siena_mcdi_reset(efx, reset_method);
0111     if (rc)
0112         goto out;
0113 
0114     tests->registers =
0115         efx_farch_test_registers(efx, siena_register_tests,
0116                      ARRAY_SIZE(siena_register_tests))
0117         ? -1 : 1;
0118 
0119     rc = efx_siena_mcdi_reset(efx, reset_method);
0120 out:
0121     rc2 = efx_siena_reset_up(efx, reset_method, rc == 0);
0122     return rc ? rc : rc2;
0123 }
0124 
0125 /**************************************************************************
0126  *
0127  * PTP
0128  *
0129  **************************************************************************
0130  */
0131 
0132 static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
0133 {
0134     _efx_writed(efx, cpu_to_le32(host_time),
0135             FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST);
0136 }
0137 
0138 static int siena_ptp_set_ts_config(struct efx_nic *efx,
0139                    struct hwtstamp_config *init)
0140 {
0141     int rc;
0142 
0143     switch (init->rx_filter) {
0144     case HWTSTAMP_FILTER_NONE:
0145         /* if TX timestamping is still requested then leave PTP on */
0146         return efx_siena_ptp_change_mode(efx,
0147                     init->tx_type != HWTSTAMP_TX_OFF,
0148                     efx_siena_ptp_get_mode(efx));
0149     case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
0150     case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
0151     case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
0152         init->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
0153         return efx_siena_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V1);
0154     case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
0155     case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
0156     case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
0157         init->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
0158         rc = efx_siena_ptp_change_mode(efx, true,
0159                            MC_CMD_PTP_MODE_V2_ENHANCED);
0160         /* bug 33070 - old versions of the firmware do not support the
0161          * improved UUID filtering option. Similarly old versions of the
0162          * application do not expect it to be enabled. If the firmware
0163          * does not accept the enhanced mode, fall back to the standard
0164          * PTP v2 UUID filtering. */
0165         if (rc != 0)
0166             rc = efx_siena_ptp_change_mode(efx, true,
0167                                MC_CMD_PTP_MODE_V2);
0168         return rc;
0169     default:
0170         return -ERANGE;
0171     }
0172 }
0173 
0174 /**************************************************************************
0175  *
0176  * Device reset
0177  *
0178  **************************************************************************
0179  */
0180 
0181 static int siena_map_reset_flags(u32 *flags)
0182 {
0183     enum {
0184         SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
0185                     ETH_RESET_OFFLOAD | ETH_RESET_MAC |
0186                     ETH_RESET_PHY),
0187         SIENA_RESET_MC = (SIENA_RESET_PORT |
0188                   ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
0189     };
0190 
0191     if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
0192         *flags &= ~SIENA_RESET_MC;
0193         return RESET_TYPE_WORLD;
0194     }
0195 
0196     if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
0197         *flags &= ~SIENA_RESET_PORT;
0198         return RESET_TYPE_ALL;
0199     }
0200 
0201     /* no invisible reset implemented */
0202 
0203     return -EINVAL;
0204 }
0205 
0206 #ifdef CONFIG_EEH
0207 /* When a PCI device is isolated from the bus, a subsequent MMIO read is
0208  * required for the kernel EEH mechanisms to notice. As the Solarflare driver
0209  * was written to minimise MMIO read (for latency) then a periodic call to check
0210  * the EEH status of the device is required so that device recovery can happen
0211  * in a timely fashion.
0212  */
0213 static void siena_monitor(struct efx_nic *efx)
0214 {
0215     struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
0216 
0217     eeh_dev_check_failure(eehdev);
0218 }
0219 #endif
0220 
0221 static int siena_probe_nvconfig(struct efx_nic *efx)
0222 {
0223     u32 caps = 0;
0224     int rc;
0225 
0226     rc = efx_siena_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL,
0227                       &caps);
0228 
0229     efx->timer_quantum_ns =
0230         (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
0231         3072 : 6144; /* 768 cycles */
0232     efx->timer_max_ns = efx->type->timer_period_max *
0233                 efx->timer_quantum_ns;
0234 
0235     return rc;
0236 }
0237 
0238 static int siena_dimension_resources(struct efx_nic *efx)
0239 {
0240     /* Each port has a small block of internal SRAM dedicated to
0241      * the buffer table and descriptor caches.  In theory we can
0242      * map both blocks to one port, but we don't.
0243      */
0244     efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
0245     return 0;
0246 }
0247 
0248 /* On all Falcon-architecture NICs, PFs use BAR 0 for I/O space and BAR 2(&3)
0249  * for memory.
0250  */
0251 static unsigned int siena_mem_bar(struct efx_nic *efx)
0252 {
0253     return 2;
0254 }
0255 
0256 static unsigned int siena_mem_map_size(struct efx_nic *efx)
0257 {
0258     return FR_CZ_MC_TREG_SMEM +
0259         FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS;
0260 }
0261 
0262 static int siena_probe_nic(struct efx_nic *efx)
0263 {
0264     struct siena_nic_data *nic_data;
0265     efx_oword_t reg;
0266     int rc;
0267 
0268     /* Allocate storage for hardware specific data */
0269     nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
0270     if (!nic_data)
0271         return -ENOMEM;
0272     nic_data->efx = efx;
0273     efx->nic_data = nic_data;
0274 
0275     if (efx_farch_fpga_ver(efx) != 0) {
0276         netif_err(efx, probe, efx->net_dev,
0277               "Siena FPGA not supported\n");
0278         rc = -ENODEV;
0279         goto fail1;
0280     }
0281 
0282     efx->max_channels = EFX_MAX_CHANNELS;
0283     efx->max_vis = EFX_MAX_CHANNELS;
0284     efx->max_tx_channels = EFX_MAX_CHANNELS;
0285     efx->tx_queues_per_channel = 4;
0286 
0287     efx_reado(efx, &reg, FR_AZ_CS_DEBUG);
0288     efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
0289 
0290     rc = efx_siena_mcdi_init(efx);
0291     if (rc)
0292         goto fail1;
0293 
0294     /* Now we can reset the NIC */
0295     rc = efx_siena_mcdi_reset(efx, RESET_TYPE_ALL);
0296     if (rc) {
0297         netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
0298         goto fail3;
0299     }
0300 
0301     siena_init_wol(efx);
0302 
0303     /* Allocate memory for INT_KER */
0304     rc = efx_siena_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
0305                     GFP_KERNEL);
0306     if (rc)
0307         goto fail4;
0308     BUG_ON(efx->irq_status.dma_addr & 0x0f);
0309 
0310     netif_dbg(efx, probe, efx->net_dev,
0311           "INT_KER at %llx (virt %p phys %llx)\n",
0312           (unsigned long long)efx->irq_status.dma_addr,
0313           efx->irq_status.addr,
0314           (unsigned long long)virt_to_phys(efx->irq_status.addr));
0315 
0316     /* Read in the non-volatile configuration */
0317     rc = siena_probe_nvconfig(efx);
0318     if (rc == -EINVAL) {
0319         netif_err(efx, probe, efx->net_dev,
0320               "NVRAM is invalid therefore using defaults\n");
0321         efx->phy_type = PHY_TYPE_NONE;
0322         efx->mdio.prtad = MDIO_PRTAD_NONE;
0323     } else if (rc) {
0324         goto fail5;
0325     }
0326 
0327     rc = efx_siena_mcdi_mon_probe(efx);
0328     if (rc)
0329         goto fail5;
0330 
0331 #ifdef CONFIG_SFC_SIENA_SRIOV
0332     efx_siena_sriov_probe(efx);
0333 #endif
0334     efx_siena_ptp_defer_probe_with_channel(efx);
0335 
0336     return 0;
0337 
0338 fail5:
0339     efx_siena_free_buffer(efx, &efx->irq_status);
0340 fail4:
0341 fail3:
0342     efx_siena_mcdi_detach(efx);
0343     efx_siena_mcdi_fini(efx);
0344 fail1:
0345     kfree(efx->nic_data);
0346     return rc;
0347 }
0348 
0349 static int siena_rx_pull_rss_config(struct efx_nic *efx)
0350 {
0351     efx_oword_t temp;
0352 
0353     /* Read from IPv6 RSS key as that's longer (the IPv4 key is just the
0354      * first 128 bits of the same key, assuming it's been set by
0355      * siena_rx_push_rss_config, below)
0356      */
0357     efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
0358     memcpy(efx->rss_context.rx_hash_key, &temp, sizeof(temp));
0359     efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
0360     memcpy(efx->rss_context.rx_hash_key + sizeof(temp), &temp, sizeof(temp));
0361     efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
0362     memcpy(efx->rss_context.rx_hash_key + 2 * sizeof(temp), &temp,
0363            FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
0364     efx_farch_rx_pull_indir_table(efx);
0365     return 0;
0366 }
0367 
0368 static int siena_rx_push_rss_config(struct efx_nic *efx, bool user,
0369                     const u32 *rx_indir_table, const u8 *key)
0370 {
0371     efx_oword_t temp;
0372 
0373     /* Set hash key for IPv4 */
0374     if (key)
0375         memcpy(efx->rss_context.rx_hash_key, key, sizeof(temp));
0376     memcpy(&temp, efx->rss_context.rx_hash_key, sizeof(temp));
0377     efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
0378 
0379     /* Enable IPv6 RSS */
0380     BUILD_BUG_ON(sizeof(efx->rss_context.rx_hash_key) <
0381              2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
0382              FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
0383     memcpy(&temp, efx->rss_context.rx_hash_key, sizeof(temp));
0384     efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
0385     memcpy(&temp, efx->rss_context.rx_hash_key + sizeof(temp), sizeof(temp));
0386     efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
0387     EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
0388                  FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
0389     memcpy(&temp, efx->rss_context.rx_hash_key + 2 * sizeof(temp),
0390            FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
0391     efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
0392 
0393     memcpy(efx->rss_context.rx_indir_table, rx_indir_table,
0394            sizeof(efx->rss_context.rx_indir_table));
0395     efx_farch_rx_push_indir_table(efx);
0396 
0397     return 0;
0398 }
0399 
0400 /* This call performs hardware-specific global initialisation, such as
0401  * defining the descriptor cache sizes and number of RSS channels.
0402  * It does not set up any buffers, descriptor rings or event queues.
0403  */
0404 static int siena_init_nic(struct efx_nic *efx)
0405 {
0406     efx_oword_t temp;
0407     int rc;
0408 
0409     /* Recover from a failed assertion post-reset */
0410     rc = efx_siena_mcdi_handle_assertion(efx);
0411     if (rc)
0412         return rc;
0413 
0414     /* Squash TX of packets of 16 bytes or less */
0415     efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
0416     EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
0417     efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
0418 
0419     /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
0420      * descriptors (which is bad).
0421      */
0422     efx_reado(efx, &temp, FR_AZ_TX_CFG);
0423     EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
0424     EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
0425     efx_writeo(efx, &temp, FR_AZ_TX_CFG);
0426 
0427     efx_reado(efx, &temp, FR_AZ_RX_CFG);
0428     EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
0429     EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
0430     /* Enable hash insertion. This is broken for the 'Falcon' hash
0431      * if IPv6 hashing is also enabled, so also select Toeplitz
0432      * TCP/IPv4 and IPv4 hashes. */
0433     EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
0434     EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
0435     EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
0436     EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
0437                 EFX_RX_USR_BUF_SIZE >> 5);
0438     efx_writeo(efx, &temp, FR_AZ_RX_CFG);
0439 
0440     siena_rx_push_rss_config(efx, false, efx->rss_context.rx_indir_table, NULL);
0441     efx->rss_context.context_id = 0; /* indicates RSS is active */
0442 
0443     /* Enable event logging */
0444     rc = efx_siena_mcdi_log_ctrl(efx, true, false, 0);
0445     if (rc)
0446         return rc;
0447 
0448     /* Set destination of both TX and RX Flush events */
0449     EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
0450     efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
0451 
0452     EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
0453     efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
0454 
0455     efx_farch_init_common(efx);
0456     return 0;
0457 }
0458 
0459 static void siena_remove_nic(struct efx_nic *efx)
0460 {
0461     efx_siena_mcdi_mon_remove(efx);
0462 
0463     efx_siena_free_buffer(efx, &efx->irq_status);
0464 
0465     efx_siena_mcdi_reset(efx, RESET_TYPE_ALL);
0466 
0467     efx_siena_mcdi_detach(efx);
0468     efx_siena_mcdi_fini(efx);
0469 
0470     /* Tear down the private nic state */
0471     kfree(efx->nic_data);
0472     efx->nic_data = NULL;
0473 }
0474 
0475 #define SIENA_DMA_STAT(ext_name, mcdi_name)         \
0476     [SIENA_STAT_ ## ext_name] =             \
0477     { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
0478 #define SIENA_OTHER_STAT(ext_name)              \
0479     [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
0480 #define GENERIC_SW_STAT(ext_name)               \
0481     [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
0482 
0483 static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = {
0484     SIENA_DMA_STAT(tx_bytes, TX_BYTES),
0485     SIENA_OTHER_STAT(tx_good_bytes),
0486     SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES),
0487     SIENA_DMA_STAT(tx_packets, TX_PKTS),
0488     SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS),
0489     SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
0490     SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS),
0491     SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
0492     SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
0493     SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
0494     SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS),
0495     SIENA_DMA_STAT(tx_64, TX_64_PKTS),
0496     SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
0497     SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
0498     SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
0499     SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
0500     SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
0501     SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
0502     SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS),
0503     SIENA_OTHER_STAT(tx_collision),
0504     SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS),
0505     SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS),
0506     SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS),
0507     SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS),
0508     SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS),
0509     SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS),
0510     SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS),
0511     SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS),
0512     SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS),
0513     SIENA_DMA_STAT(rx_bytes, RX_BYTES),
0514     SIENA_OTHER_STAT(rx_good_bytes),
0515     SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES),
0516     SIENA_DMA_STAT(rx_packets, RX_PKTS),
0517     SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS),
0518     SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
0519     SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
0520     SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS),
0521     SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
0522     SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
0523     SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
0524     SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
0525     SIENA_DMA_STAT(rx_64, RX_64_PKTS),
0526     SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
0527     SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
0528     SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
0529     SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
0530     SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
0531     SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
0532     SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
0533     SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
0534     SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
0535     SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS),
0536     SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS),
0537     SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
0538     SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
0539     SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS),
0540     SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS),
0541     GENERIC_SW_STAT(rx_nodesc_trunc),
0542     GENERIC_SW_STAT(rx_noskb_drops),
0543 };
0544 static const unsigned long siena_stat_mask[] = {
0545     [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL,
0546 };
0547 
0548 static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names)
0549 {
0550     return efx_siena_describe_stats(siena_stat_desc, SIENA_STAT_COUNT,
0551                     siena_stat_mask, names);
0552 }
0553 
0554 static int siena_try_update_nic_stats(struct efx_nic *efx)
0555 {
0556     struct siena_nic_data *nic_data = efx->nic_data;
0557     u64 *stats = nic_data->stats;
0558     __le64 *dma_stats;
0559     __le64 generation_start, generation_end;
0560 
0561     dma_stats = efx->stats_buffer.addr;
0562 
0563     generation_end = dma_stats[efx->num_mac_stats - 1];
0564     if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
0565         return 0;
0566     rmb();
0567     efx_siena_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask,
0568                    stats, efx->stats_buffer.addr, false);
0569     rmb();
0570     generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
0571     if (generation_end != generation_start)
0572         return -EAGAIN;
0573 
0574     /* Update derived statistics */
0575     efx_siena_fix_nodesc_drop_stat(efx,
0576                        &stats[SIENA_STAT_rx_nodesc_drop_cnt]);
0577     efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes],
0578                  stats[SIENA_STAT_tx_bytes] -
0579                  stats[SIENA_STAT_tx_bad_bytes]);
0580     stats[SIENA_STAT_tx_collision] =
0581         stats[SIENA_STAT_tx_single_collision] +
0582         stats[SIENA_STAT_tx_multiple_collision] +
0583         stats[SIENA_STAT_tx_excessive_collision] +
0584         stats[SIENA_STAT_tx_late_collision];
0585     efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes],
0586                  stats[SIENA_STAT_rx_bytes] -
0587                  stats[SIENA_STAT_rx_bad_bytes]);
0588     efx_siena_update_sw_stats(efx, stats);
0589     return 0;
0590 }
0591 
0592 static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
0593                      struct rtnl_link_stats64 *core_stats)
0594 {
0595     struct siena_nic_data *nic_data = efx->nic_data;
0596     u64 *stats = nic_data->stats;
0597     int retry;
0598 
0599     /* If we're unlucky enough to read statistics wduring the DMA, wait
0600      * up to 10ms for it to finish (typically takes <500us) */
0601     for (retry = 0; retry < 100; ++retry) {
0602         if (siena_try_update_nic_stats(efx) == 0)
0603             break;
0604         udelay(100);
0605     }
0606 
0607     if (full_stats)
0608         memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT);
0609 
0610     if (core_stats) {
0611         core_stats->rx_packets = stats[SIENA_STAT_rx_packets];
0612         core_stats->tx_packets = stats[SIENA_STAT_tx_packets];
0613         core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes];
0614         core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes];
0615         core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt] +
0616                      stats[GENERIC_STAT_rx_nodesc_trunc] +
0617                      stats[GENERIC_STAT_rx_noskb_drops];
0618         core_stats->multicast = stats[SIENA_STAT_rx_multicast];
0619         core_stats->collisions = stats[SIENA_STAT_tx_collision];
0620         core_stats->rx_length_errors =
0621             stats[SIENA_STAT_rx_gtjumbo] +
0622             stats[SIENA_STAT_rx_length_error];
0623         core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad];
0624         core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error];
0625         core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow];
0626         core_stats->tx_window_errors =
0627             stats[SIENA_STAT_tx_late_collision];
0628 
0629         core_stats->rx_errors = (core_stats->rx_length_errors +
0630                      core_stats->rx_crc_errors +
0631                      core_stats->rx_frame_errors +
0632                      stats[SIENA_STAT_rx_symbol_error]);
0633         core_stats->tx_errors = (core_stats->tx_window_errors +
0634                      stats[SIENA_STAT_tx_bad]);
0635     }
0636 
0637     return SIENA_STAT_COUNT;
0638 }
0639 
0640 static int siena_mac_reconfigure(struct efx_nic *efx, bool mtu_only __always_unused)
0641 {
0642     MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
0643     int rc;
0644 
0645     BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
0646              MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
0647              sizeof(efx->multicast_hash));
0648 
0649     efx_farch_filter_sync_rx_mode(efx);
0650 
0651     WARN_ON(!mutex_is_locked(&efx->mac_lock));
0652 
0653     rc = efx_siena_mcdi_set_mac(efx);
0654     if (rc != 0)
0655         return rc;
0656 
0657     memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
0658            efx->multicast_hash.byte, sizeof(efx->multicast_hash));
0659     return efx_siena_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
0660                   inbuf, sizeof(inbuf), NULL, 0, NULL);
0661 }
0662 
0663 /**************************************************************************
0664  *
0665  * Wake on LAN
0666  *
0667  **************************************************************************
0668  */
0669 
0670 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
0671 {
0672     struct siena_nic_data *nic_data = efx->nic_data;
0673 
0674     wol->supported = WAKE_MAGIC;
0675     if (nic_data->wol_filter_id != -1)
0676         wol->wolopts = WAKE_MAGIC;
0677     else
0678         wol->wolopts = 0;
0679     memset(&wol->sopass, 0, sizeof(wol->sopass));
0680 }
0681 
0682 
0683 static int siena_set_wol(struct efx_nic *efx, u32 type)
0684 {
0685     struct siena_nic_data *nic_data = efx->nic_data;
0686     int rc;
0687 
0688     if (type & ~WAKE_MAGIC)
0689         return -EINVAL;
0690 
0691     if (type & WAKE_MAGIC) {
0692         if (nic_data->wol_filter_id != -1)
0693             efx_siena_mcdi_wol_filter_remove(efx,
0694                         nic_data->wol_filter_id);
0695         rc = efx_siena_mcdi_wol_filter_set_magic(efx,
0696                         efx->net_dev->dev_addr,
0697                         &nic_data->wol_filter_id);
0698         if (rc)
0699             goto fail;
0700 
0701         pci_wake_from_d3(efx->pci_dev, true);
0702     } else {
0703         rc = efx_siena_mcdi_wol_filter_reset(efx);
0704         nic_data->wol_filter_id = -1;
0705         pci_wake_from_d3(efx->pci_dev, false);
0706         if (rc)
0707             goto fail;
0708     }
0709 
0710     return 0;
0711  fail:
0712     netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
0713           __func__, type, rc);
0714     return rc;
0715 }
0716 
0717 
0718 static void siena_init_wol(struct efx_nic *efx)
0719 {
0720     struct siena_nic_data *nic_data = efx->nic_data;
0721     int rc;
0722 
0723     rc = efx_siena_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
0724 
0725     if (rc != 0) {
0726         /* If it failed, attempt to get into a synchronised
0727          * state with MC by resetting any set WoL filters */
0728         efx_siena_mcdi_wol_filter_reset(efx);
0729         nic_data->wol_filter_id = -1;
0730     } else if (nic_data->wol_filter_id != -1) {
0731         pci_wake_from_d3(efx->pci_dev, true);
0732     }
0733 }
0734 
0735 /**************************************************************************
0736  *
0737  * MCDI
0738  *
0739  **************************************************************************
0740  */
0741 
0742 #define MCDI_PDU(efx)                           \
0743     (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
0744 #define MCDI_DOORBELL(efx)                      \
0745     (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
0746 #define MCDI_STATUS(efx)                        \
0747     (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
0748 
0749 static void siena_mcdi_request(struct efx_nic *efx,
0750                    const efx_dword_t *hdr, size_t hdr_len,
0751                    const efx_dword_t *sdu, size_t sdu_len)
0752 {
0753     unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
0754     unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
0755     unsigned int i;
0756     unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
0757 
0758     EFX_WARN_ON_PARANOID(hdr_len != 4);
0759 
0760     efx_writed(efx, hdr, pdu);
0761 
0762     for (i = 0; i < inlen_dw; i++)
0763         efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
0764 
0765     /* Ensure the request is written out before the doorbell */
0766     wmb();
0767 
0768     /* ring the doorbell with a distinctive value */
0769     _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
0770 }
0771 
0772 static bool siena_mcdi_poll_response(struct efx_nic *efx)
0773 {
0774     unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
0775     efx_dword_t hdr;
0776 
0777     efx_readd(efx, &hdr, pdu);
0778 
0779     /* All 1's indicates that shared memory is in reset (and is
0780      * not a valid hdr). Wait for it to come out reset before
0781      * completing the command
0782      */
0783     return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
0784         EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
0785 }
0786 
0787 static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
0788                      size_t offset, size_t outlen)
0789 {
0790     unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
0791     unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
0792     int i;
0793 
0794     for (i = 0; i < outlen_dw; i++)
0795         efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
0796 }
0797 
0798 static int siena_mcdi_poll_reboot(struct efx_nic *efx)
0799 {
0800     struct siena_nic_data *nic_data = efx->nic_data;
0801     unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
0802     efx_dword_t reg;
0803     u32 value;
0804 
0805     efx_readd(efx, &reg, addr);
0806     value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
0807 
0808     if (value == 0)
0809         return 0;
0810 
0811     EFX_ZERO_DWORD(reg);
0812     efx_writed(efx, &reg, addr);
0813 
0814     /* MAC statistics have been cleared on the NIC; clear the local
0815      * copies that we update with efx_update_diff_stat().
0816      */
0817     nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;
0818     nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;
0819 
0820     if (value == MC_STATUS_DWORD_ASSERT)
0821         return -EINTR;
0822     else
0823         return -EIO;
0824 }
0825 
0826 /**************************************************************************
0827  *
0828  * MTD
0829  *
0830  **************************************************************************
0831  */
0832 
0833 #ifdef CONFIG_SFC_SIENA_MTD
0834 
0835 struct siena_nvram_type_info {
0836     int port;
0837     const char *name;
0838 };
0839 
0840 static const struct siena_nvram_type_info siena_nvram_types[] = {
0841     [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO]   = { 0, "sfc_dummy_phy" },
0842     [MC_CMD_NVRAM_TYPE_MC_FW]       = { 0, "sfc_mcfw" },
0843     [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP]    = { 0, "sfc_mcfw_backup" },
0844     [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0]    = { 0, "sfc_static_cfg" },
0845     [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1]    = { 1, "sfc_static_cfg" },
0846     [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0]   = { 0, "sfc_dynamic_cfg" },
0847     [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1]   = { 1, "sfc_dynamic_cfg" },
0848     [MC_CMD_NVRAM_TYPE_EXP_ROM]     = { 0, "sfc_exp_rom" },
0849     [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0]   = { 0, "sfc_exp_rom_cfg" },
0850     [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1]   = { 1, "sfc_exp_rom_cfg" },
0851     [MC_CMD_NVRAM_TYPE_PHY_PORT0]       = { 0, "sfc_phy_fw" },
0852     [MC_CMD_NVRAM_TYPE_PHY_PORT1]       = { 1, "sfc_phy_fw" },
0853     [MC_CMD_NVRAM_TYPE_FPGA]        = { 0, "sfc_fpga" },
0854 };
0855 
0856 static int siena_mtd_probe_partition(struct efx_nic *efx,
0857                      struct efx_mcdi_mtd_partition *part,
0858                      unsigned int type)
0859 {
0860     const struct siena_nvram_type_info *info;
0861     size_t size, erase_size;
0862     bool protected;
0863     int rc;
0864 
0865     if (type >= ARRAY_SIZE(siena_nvram_types) ||
0866         siena_nvram_types[type].name == NULL)
0867         return -ENODEV;
0868 
0869     info = &siena_nvram_types[type];
0870 
0871     if (info->port != efx_port_num(efx))
0872         return -ENODEV;
0873 
0874     rc = efx_siena_mcdi_nvram_info(efx, type, &size, &erase_size,
0875                        &protected);
0876     if (rc)
0877         return rc;
0878     if (protected)
0879         return -ENODEV; /* hide it */
0880 
0881     part->nvram_type = type;
0882     part->common.dev_type_name = "Siena NVRAM manager";
0883     part->common.type_name = info->name;
0884 
0885     part->common.mtd.type = MTD_NORFLASH;
0886     part->common.mtd.flags = MTD_CAP_NORFLASH;
0887     part->common.mtd.size = size;
0888     part->common.mtd.erasesize = erase_size;
0889 
0890     return 0;
0891 }
0892 
0893 static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
0894                      struct efx_mcdi_mtd_partition *parts,
0895                      size_t n_parts)
0896 {
0897     uint16_t fw_subtype_list[
0898         MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM];
0899     size_t i;
0900     int rc;
0901 
0902     rc = efx_siena_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL);
0903     if (rc)
0904         return rc;
0905 
0906     for (i = 0; i < n_parts; i++)
0907         parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type];
0908 
0909     return 0;
0910 }
0911 
0912 static int siena_mtd_probe(struct efx_nic *efx)
0913 {
0914     struct efx_mcdi_mtd_partition *parts;
0915     u32 nvram_types;
0916     unsigned int type;
0917     size_t n_parts;
0918     int rc;
0919 
0920     ASSERT_RTNL();
0921 
0922     rc = efx_siena_mcdi_nvram_types(efx, &nvram_types);
0923     if (rc)
0924         return rc;
0925 
0926     parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL);
0927     if (!parts)
0928         return -ENOMEM;
0929 
0930     type = 0;
0931     n_parts = 0;
0932 
0933     while (nvram_types != 0) {
0934         if (nvram_types & 1) {
0935             rc = siena_mtd_probe_partition(efx, &parts[n_parts],
0936                                type);
0937             if (rc == 0)
0938                 n_parts++;
0939             else if (rc != -ENODEV)
0940                 goto fail;
0941         }
0942         type++;
0943         nvram_types >>= 1;
0944     }
0945 
0946     rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts);
0947     if (rc)
0948         goto fail;
0949 
0950     rc = efx_siena_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
0951 fail:
0952     if (rc)
0953         kfree(parts);
0954     return rc;
0955 }
0956 
0957 #endif /* CONFIG_SFC_SIENA_MTD */
0958 
0959 static unsigned int siena_check_caps(const struct efx_nic *efx,
0960                      u8 flag, u32 offset)
0961 {
0962     /* Siena did not support MC_CMD_GET_CAPABILITIES */
0963     return 0;
0964 }
0965 
0966 static unsigned int efx_siena_recycle_ring_size(const struct efx_nic *efx)
0967 {
0968     /* Maximum link speed is 10G */
0969     return EFX_RECYCLE_RING_SIZE_10G;
0970 }
0971 
0972 /**************************************************************************
0973  *
0974  * Revision-dependent attributes used by efx.c and nic.c
0975  *
0976  **************************************************************************
0977  */
0978 
0979 const struct efx_nic_type siena_a0_nic_type = {
0980     .is_vf = false,
0981     .mem_bar = siena_mem_bar,
0982     .mem_map_size = siena_mem_map_size,
0983     .probe = siena_probe_nic,
0984     .remove = siena_remove_nic,
0985     .init = siena_init_nic,
0986     .dimension_resources = siena_dimension_resources,
0987     .fini = efx_siena_port_dummy_op_void,
0988 #ifdef CONFIG_EEH
0989     .monitor = siena_monitor,
0990 #else
0991     .monitor = NULL,
0992 #endif
0993     .map_reset_reason = efx_siena_mcdi_map_reset_reason,
0994     .map_reset_flags = siena_map_reset_flags,
0995     .reset = efx_siena_mcdi_reset,
0996     .probe_port = efx_siena_mcdi_port_probe,
0997     .remove_port = efx_siena_mcdi_port_remove,
0998     .fini_dmaq = efx_farch_fini_dmaq,
0999     .prepare_flush = efx_siena_prepare_flush,
1000     .finish_flush = siena_finish_flush,
1001     .prepare_flr = efx_siena_port_dummy_op_void,
1002     .finish_flr = efx_farch_finish_flr,
1003     .describe_stats = siena_describe_nic_stats,
1004     .update_stats = siena_update_nic_stats,
1005     .start_stats = efx_siena_mcdi_mac_start_stats,
1006     .pull_stats = efx_siena_mcdi_mac_pull_stats,
1007     .stop_stats = efx_siena_mcdi_mac_stop_stats,
1008     .push_irq_moderation = siena_push_irq_moderation,
1009     .reconfigure_mac = siena_mac_reconfigure,
1010     .check_mac_fault = efx_siena_mcdi_mac_check_fault,
1011     .reconfigure_port = efx_siena_mcdi_port_reconfigure,
1012     .get_wol = siena_get_wol,
1013     .set_wol = siena_set_wol,
1014     .resume_wol = siena_init_wol,
1015     .test_chip = siena_test_chip,
1016     .test_nvram = efx_siena_mcdi_nvram_test_all,
1017     .mcdi_request = siena_mcdi_request,
1018     .mcdi_poll_response = siena_mcdi_poll_response,
1019     .mcdi_read_response = siena_mcdi_read_response,
1020     .mcdi_poll_reboot = siena_mcdi_poll_reboot,
1021     .irq_enable_master = efx_farch_irq_enable_master,
1022     .irq_test_generate = efx_farch_irq_test_generate,
1023     .irq_disable_non_ev = efx_farch_irq_disable_master,
1024     .irq_handle_msi = efx_farch_msi_interrupt,
1025     .irq_handle_legacy = efx_farch_legacy_interrupt,
1026     .tx_probe = efx_farch_tx_probe,
1027     .tx_init = efx_farch_tx_init,
1028     .tx_remove = efx_farch_tx_remove,
1029     .tx_write = efx_farch_tx_write,
1030     .tx_limit_len = efx_farch_tx_limit_len,
1031     .tx_enqueue = __efx_siena_enqueue_skb,
1032     .rx_push_rss_config = siena_rx_push_rss_config,
1033     .rx_pull_rss_config = siena_rx_pull_rss_config,
1034     .rx_probe = efx_farch_rx_probe,
1035     .rx_init = efx_farch_rx_init,
1036     .rx_remove = efx_farch_rx_remove,
1037     .rx_write = efx_farch_rx_write,
1038     .rx_defer_refill = efx_farch_rx_defer_refill,
1039     .rx_packet = __efx_siena_rx_packet,
1040     .ev_probe = efx_farch_ev_probe,
1041     .ev_init = efx_farch_ev_init,
1042     .ev_fini = efx_farch_ev_fini,
1043     .ev_remove = efx_farch_ev_remove,
1044     .ev_process = efx_farch_ev_process,
1045     .ev_read_ack = efx_farch_ev_read_ack,
1046     .ev_test_generate = efx_farch_ev_test_generate,
1047     .filter_table_probe = efx_farch_filter_table_probe,
1048     .filter_table_restore = efx_farch_filter_table_restore,
1049     .filter_table_remove = efx_farch_filter_table_remove,
1050     .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
1051     .filter_insert = efx_farch_filter_insert,
1052     .filter_remove_safe = efx_farch_filter_remove_safe,
1053     .filter_get_safe = efx_farch_filter_get_safe,
1054     .filter_clear_rx = efx_farch_filter_clear_rx,
1055     .filter_count_rx_used = efx_farch_filter_count_rx_used,
1056     .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
1057     .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
1058 #ifdef CONFIG_RFS_ACCEL
1059     .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
1060 #endif
1061 #ifdef CONFIG_SFC_SIENA_MTD
1062     .mtd_probe = siena_mtd_probe,
1063     .mtd_rename = efx_siena_mcdi_mtd_rename,
1064     .mtd_read = efx_siena_mcdi_mtd_read,
1065     .mtd_erase = efx_siena_mcdi_mtd_erase,
1066     .mtd_write = efx_siena_mcdi_mtd_write,
1067     .mtd_sync = efx_siena_mcdi_mtd_sync,
1068 #endif
1069     .ptp_write_host_time = siena_ptp_write_host_time,
1070     .ptp_set_ts_config = siena_ptp_set_ts_config,
1071 #ifdef CONFIG_SFC_SIENA_SRIOV
1072     .sriov_configure = efx_siena_sriov_configure,
1073     .sriov_init = efx_siena_sriov_init,
1074     .sriov_fini = efx_siena_sriov_fini,
1075     .sriov_wanted = efx_siena_sriov_wanted,
1076     .sriov_reset = efx_siena_sriov_reset,
1077     .sriov_flr = efx_siena_sriov_flr,
1078     .sriov_set_vf_mac = efx_siena_sriov_set_vf_mac,
1079     .sriov_set_vf_vlan = efx_siena_sriov_set_vf_vlan,
1080     .sriov_set_vf_spoofchk = efx_siena_sriov_set_vf_spoofchk,
1081     .sriov_get_vf_config = efx_siena_sriov_get_vf_config,
1082     .vswitching_probe = efx_siena_port_dummy_op_int,
1083     .vswitching_restore = efx_siena_port_dummy_op_int,
1084     .vswitching_remove = efx_siena_port_dummy_op_void,
1085     .set_mac_address = efx_siena_sriov_mac_address_changed,
1086 #endif
1087 
1088     .revision = EFX_REV_SIENA_A0,
1089     .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1090     .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1091     .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1092     .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1093     .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1094     .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1095     .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
1096     .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
1097     .rx_buffer_padding = 0,
1098     .can_rx_scatter = true,
1099     .option_descriptors = false,
1100     .min_interrupt_mode = EFX_INT_MODE_LEGACY,
1101     .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
1102     .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1103                  NETIF_F_RXHASH | NETIF_F_NTUPLE),
1104     .mcdi_max_ver = 1,
1105     .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
1106     .hwtstamp_filters = (1 << HWTSTAMP_FILTER_NONE |
1107                  1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT |
1108                  1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT),
1109     .rx_hash_key_size = 16,
1110     .check_caps = siena_check_caps,
1111     .sensor_event = efx_siena_mcdi_sensor_event,
1112     .rx_recycle_ring_size = efx_siena_recycle_ring_size,
1113 };
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