sfc/siena/nic_common.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /****************************************************************************
0003  * Driver for Solarflare network controllers and boards
0004  * Copyright 2005-2006 Fen Systems Ltd.
0005  * Copyright 2006-2013 Solarflare Communications Inc.
0006  * Copyright 2019-2020 Xilinx Inc.
0007  */
0008
0009 #ifndef EFX_NIC_COMMON_H
0010 #define EFX_NIC_COMMON_H
0011
0012 #include "net_driver.h"
0013 #include "efx_common.h"
0014 #include "mcdi.h"
0015 #include "ptp.h"
0016
0017 enum {
0018     /* Revisions 0-2 were Falcon A0, A1 and B0 respectively.
0019      * They are not supported by this driver but these revision numbers
0020      * form part of the ethtool API for register dumping.
0021      */
0022     EFX_REV_SIENA_A0 = 3,
0023     EFX_REV_HUNT_A0 = 4,
0024     EFX_REV_EF100 = 5,
0025 };
0026
0027 static inline int efx_nic_rev(struct efx_nic *efx)
0028 {
0029     return efx->type->revision;
0030 }
0031
0032 /* Read the current event from the event queue */
0033 static inline efx_qword_t *efx_event(struct efx_channel *channel,
0034                      unsigned int index)
0035 {
0036     return ((efx_qword_t *) (channel->eventq.buf.addr)) +
0037         (index & channel->eventq_mask);
0038 }
0039
0040 /* See if an event is present
0041  *
0042  * We check both the high and low dword of the event for all ones.  We
0043  * wrote all ones when we cleared the event, and no valid event can
0044  * have all ones in either its high or low dwords.  This approach is
0045  * robust against reordering.
0046  *
0047  * Note that using a single 64-bit comparison is incorrect; even
0048  * though the CPU read will be atomic, the DMA write may not be.
0049  */
0050 static inline int efx_event_present(efx_qword_t *event)
0051 {
0052     return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
0053           EFX_DWORD_IS_ALL_ONES(event->dword[1]));
0054 }
0055
0056 /* Returns a pointer to the specified transmit descriptor in the TX
0057  * descriptor queue belonging to the specified channel.
0058  */
0059 static inline efx_qword_t *
0060 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
0061 {
0062     return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index;
0063 }
0064
0065 /* Report whether this TX queue would be empty for the given write_count.
0066  * May return false negative.
0067  */
0068 static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue, unsigned int write_count)
0069 {
0070     unsigned int empty_read_count = READ_ONCE(tx_queue->empty_read_count);
0071
0072     if (empty_read_count == 0)
0073         return false;
0074
0075     return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0;
0076 }
0077
0078 /* Decide whether to push a TX descriptor to the NIC vs merely writing
0079  * the doorbell.  This can reduce latency when we are adding a single
0080  * descriptor to an empty queue, but is otherwise pointless.  Further,
0081  * Falcon and Siena have hardware bugs (SF bug 33851) that may be
0082  * triggered if we don't check this.
0083  * We use the write_count used for the last doorbell push, to get the
0084  * NIC's view of the tx queue.
0085  */
0086 static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue,
0087                         unsigned int write_count)
0088 {
0089     bool was_empty = efx_nic_tx_is_empty(tx_queue, write_count);
0090
0091     tx_queue->empty_read_count = 0;
0092     return was_empty && tx_queue->write_count - write_count == 1;
0093 }
0094
0095 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
0096 static inline efx_qword_t *
0097 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
0098 {
0099     return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index;
0100 }
0101
0102 /* Alignment of PCIe DMA boundaries (4KB) */
0103 #define EFX_PAGE_SIZE   4096
0104 /* Size and alignment of buffer table entries (same) */
0105 #define EFX_BUF_SIZE    EFX_PAGE_SIZE
0106
0107 /* NIC-generic software stats */
0108 enum {
0109     GENERIC_STAT_rx_noskb_drops,
0110     GENERIC_STAT_rx_nodesc_trunc,
0111     GENERIC_STAT_COUNT
0112 };
0113
0114 #define EFX_GENERIC_SW_STAT(ext_name)               \
0115     [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
0116
0117 /* TX data path */
0118 static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
0119 {
0120     return tx_queue->efx->type->tx_probe(tx_queue);
0121 }
0122 static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
0123 {
0124     tx_queue->efx->type->tx_init(tx_queue);
0125 }
0126 static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
0127 {
0128     if (tx_queue->efx->type->tx_remove)
0129         tx_queue->efx->type->tx_remove(tx_queue);
0130 }
0131 static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
0132 {
0133     tx_queue->efx->type->tx_write(tx_queue);
0134 }
0135
0136 /* RX data path */
0137 static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
0138 {
0139     return rx_queue->efx->type->rx_probe(rx_queue);
0140 }
0141 static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
0142 {
0143     rx_queue->efx->type->rx_init(rx_queue);
0144 }
0145 static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
0146 {
0147     rx_queue->efx->type->rx_remove(rx_queue);
0148 }
0149 static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
0150 {
0151     rx_queue->efx->type->rx_write(rx_queue);
0152 }
0153 static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
0154 {
0155     rx_queue->efx->type->rx_defer_refill(rx_queue);
0156 }
0157
0158 /* Event data path */
0159 static inline int efx_nic_probe_eventq(struct efx_channel *channel)
0160 {
0161     return channel->efx->type->ev_probe(channel);
0162 }
0163 static inline int efx_nic_init_eventq(struct efx_channel *channel)
0164 {
0165     return channel->efx->type->ev_init(channel);
0166 }
0167 static inline void efx_nic_fini_eventq(struct efx_channel *channel)
0168 {
0169     channel->efx->type->ev_fini(channel);
0170 }
0171 static inline void efx_nic_remove_eventq(struct efx_channel *channel)
0172 {
0173     channel->efx->type->ev_remove(channel);
0174 }
0175 static inline int
0176 efx_nic_process_eventq(struct efx_channel *channel, int quota)
0177 {
0178     return channel->efx->type->ev_process(channel, quota);
0179 }
0180 static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
0181 {
0182     channel->efx->type->ev_read_ack(channel);
0183 }
0184
0185 void efx_siena_event_test_start(struct efx_channel *channel);
0186
0187 bool efx_siena_event_present(struct efx_channel *channel);
0188
0189 static inline void efx_sensor_event(struct efx_nic *efx, efx_qword_t *ev)
0190 {
0191     if (efx->type->sensor_event)
0192         efx->type->sensor_event(efx, ev);
0193 }
0194
0195 static inline unsigned int efx_rx_recycle_ring_size(const struct efx_nic *efx)
0196 {
0197     return efx->type->rx_recycle_ring_size(efx);
0198 }
0199
0200 /* Some statistics are computed as A - B where A and B each increase
0201  * linearly with some hardware counter(s) and the counters are read
0202  * asynchronously.  If the counters contributing to B are always read
0203  * after those contributing to A, the computed value may be lower than
0204  * the true value by some variable amount, and may decrease between
0205  * subsequent computations.
0206  *
0207  * We should never allow statistics to decrease or to exceed the true
0208  * value.  Since the computed value will never be greater than the
0209  * true value, we can achieve this by only storing the computed value
0210  * when it increases.
0211  */
0212 static inline void efx_update_diff_stat(u64 *stat, u64 diff)
0213 {
0214     if ((s64)(diff - *stat) > 0)
0215         *stat = diff;
0216 }
0217
0218 /* Interrupts */
0219 int efx_siena_init_interrupt(struct efx_nic *efx);
0220 int efx_siena_irq_test_start(struct efx_nic *efx);
0221 void efx_siena_fini_interrupt(struct efx_nic *efx);
0222
0223 static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel)
0224 {
0225     return READ_ONCE(channel->event_test_cpu);
0226 }
0227 static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx)
0228 {
0229     return READ_ONCE(efx->last_irq_cpu);
0230 }
0231
0232 /* Global Resources */
0233 int efx_siena_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
0234                unsigned int len, gfp_t gfp_flags);
0235 void efx_siena_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer);
0236
0237 size_t efx_siena_get_regs_len(struct efx_nic *efx);
0238 void efx_siena_get_regs(struct efx_nic *efx, void *buf);
0239
0240 #define EFX_MC_STATS_GENERATION_INVALID ((__force __le64)(-1))
0241
0242 size_t efx_siena_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
0243                 const unsigned long *mask, u8 *names);
0244 void efx_siena_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
0245                 const unsigned long *mask, u64 *stats,
0246                 const void *dma_buf, bool accumulate);
0247 void efx_siena_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat);
0248
0249 #define EFX_MAX_FLUSH_TIME 5000
0250
0251 #endif /* EFX_NIC_COMMON_H */