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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /****************************************************************************
0003  * Driver for Solarflare network controllers and boards
0004  * Copyright 2005-2006 Fen Systems Ltd.
0005  * Copyright 2006-2013 Solarflare Communications Inc.
0006  */
0007 
0008 #include <linux/bitops.h>
0009 #include <linux/delay.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/pci.h>
0012 #include <linux/module.h>
0013 #include <linux/seq_file.h>
0014 #include <linux/cpu_rmap.h>
0015 #include "net_driver.h"
0016 #include "bitfield.h"
0017 #include "efx.h"
0018 #include "nic.h"
0019 #include "farch_regs.h"
0020 #include "io.h"
0021 #include "workarounds.h"
0022 #include "mcdi_pcol.h"
0023 
0024 /**************************************************************************
0025  *
0026  * Generic buffer handling
0027  * These buffers are used for interrupt status, MAC stats, etc.
0028  *
0029  **************************************************************************/
0030 
0031 int efx_siena_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
0032                unsigned int len, gfp_t gfp_flags)
0033 {
0034     buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len,
0035                       &buffer->dma_addr, gfp_flags);
0036     if (!buffer->addr)
0037         return -ENOMEM;
0038     buffer->len = len;
0039     return 0;
0040 }
0041 
0042 void efx_siena_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
0043 {
0044     if (buffer->addr) {
0045         dma_free_coherent(&efx->pci_dev->dev, buffer->len,
0046                   buffer->addr, buffer->dma_addr);
0047         buffer->addr = NULL;
0048     }
0049 }
0050 
0051 /* Check whether an event is present in the eventq at the current
0052  * read pointer.  Only useful for self-test.
0053  */
0054 bool efx_siena_event_present(struct efx_channel *channel)
0055 {
0056     return efx_event_present(efx_event(channel, channel->eventq_read_ptr));
0057 }
0058 
0059 void efx_siena_event_test_start(struct efx_channel *channel)
0060 {
0061     channel->event_test_cpu = -1;
0062     smp_wmb();
0063     channel->efx->type->ev_test_generate(channel);
0064 }
0065 
0066 int efx_siena_irq_test_start(struct efx_nic *efx)
0067 {
0068     efx->last_irq_cpu = -1;
0069     smp_wmb();
0070     return efx->type->irq_test_generate(efx);
0071 }
0072 
0073 /* Hook interrupt handler(s)
0074  * Try MSI and then legacy interrupts.
0075  */
0076 int efx_siena_init_interrupt(struct efx_nic *efx)
0077 {
0078     struct efx_channel *channel;
0079     unsigned int n_irqs;
0080     int rc;
0081 
0082     if (!EFX_INT_MODE_USE_MSI(efx)) {
0083         rc = request_irq(efx->legacy_irq,
0084                  efx->type->irq_handle_legacy, IRQF_SHARED,
0085                  efx->name, efx);
0086         if (rc) {
0087             netif_err(efx, drv, efx->net_dev,
0088                   "failed to hook legacy IRQ %d\n",
0089                   efx->pci_dev->irq);
0090             goto fail1;
0091         }
0092         efx->irqs_hooked = true;
0093         return 0;
0094     }
0095 
0096 #ifdef CONFIG_RFS_ACCEL
0097     if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
0098         efx->net_dev->rx_cpu_rmap =
0099             alloc_irq_cpu_rmap(efx->n_rx_channels);
0100         if (!efx->net_dev->rx_cpu_rmap) {
0101             rc = -ENOMEM;
0102             goto fail1;
0103         }
0104     }
0105 #endif
0106 
0107     /* Hook MSI or MSI-X interrupt */
0108     n_irqs = 0;
0109     efx_for_each_channel(channel, efx) {
0110         rc = request_irq(channel->irq, efx->type->irq_handle_msi,
0111                  IRQF_PROBE_SHARED, /* Not shared */
0112                  efx->msi_context[channel->channel].name,
0113                  &efx->msi_context[channel->channel]);
0114         if (rc) {
0115             netif_err(efx, drv, efx->net_dev,
0116                   "failed to hook IRQ %d\n", channel->irq);
0117             goto fail2;
0118         }
0119         ++n_irqs;
0120 
0121 #ifdef CONFIG_RFS_ACCEL
0122         if (efx->interrupt_mode == EFX_INT_MODE_MSIX &&
0123             channel->channel < efx->n_rx_channels) {
0124             rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
0125                           channel->irq);
0126             if (rc)
0127                 goto fail2;
0128         }
0129 #endif
0130     }
0131 
0132     efx->irqs_hooked = true;
0133     return 0;
0134 
0135  fail2:
0136 #ifdef CONFIG_RFS_ACCEL
0137     free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
0138     efx->net_dev->rx_cpu_rmap = NULL;
0139 #endif
0140     efx_for_each_channel(channel, efx) {
0141         if (n_irqs-- == 0)
0142             break;
0143         free_irq(channel->irq, &efx->msi_context[channel->channel]);
0144     }
0145  fail1:
0146     return rc;
0147 }
0148 
0149 void efx_siena_fini_interrupt(struct efx_nic *efx)
0150 {
0151     struct efx_channel *channel;
0152 
0153 #ifdef CONFIG_RFS_ACCEL
0154     free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
0155     efx->net_dev->rx_cpu_rmap = NULL;
0156 #endif
0157 
0158     if (!efx->irqs_hooked)
0159         return;
0160     if (EFX_INT_MODE_USE_MSI(efx)) {
0161         /* Disable MSI/MSI-X interrupts */
0162         efx_for_each_channel(channel, efx)
0163             free_irq(channel->irq,
0164                  &efx->msi_context[channel->channel]);
0165     } else {
0166         /* Disable legacy interrupt */
0167         free_irq(efx->legacy_irq, efx);
0168     }
0169     efx->irqs_hooked = false;
0170 }
0171 
0172 /* Register dump */
0173 
0174 #define REGISTER_REVISION_FA    1
0175 #define REGISTER_REVISION_FB    2
0176 #define REGISTER_REVISION_FC    3
0177 #define REGISTER_REVISION_FZ    3   /* last Falcon arch revision */
0178 #define REGISTER_REVISION_ED    4
0179 #define REGISTER_REVISION_EZ    4   /* latest EF10 revision */
0180 
0181 struct efx_nic_reg {
0182     u32 offset:24;
0183     u32 min_revision:3, max_revision:3;
0184 };
0185 
0186 #define REGISTER(name, arch, min_rev, max_rev) {            \
0187     arch ## R_ ## min_rev ## max_rev ## _ ## name,          \
0188     REGISTER_REVISION_ ## arch ## min_rev,              \
0189     REGISTER_REVISION_ ## arch ## max_rev               \
0190 }
0191 #define REGISTER_AA(name) REGISTER(name, F, A, A)
0192 #define REGISTER_AB(name) REGISTER(name, F, A, B)
0193 #define REGISTER_AZ(name) REGISTER(name, F, A, Z)
0194 #define REGISTER_BB(name) REGISTER(name, F, B, B)
0195 #define REGISTER_BZ(name) REGISTER(name, F, B, Z)
0196 #define REGISTER_CZ(name) REGISTER(name, F, C, Z)
0197 
0198 static const struct efx_nic_reg efx_nic_regs[] = {
0199     REGISTER_AZ(ADR_REGION),
0200     REGISTER_AZ(INT_EN_KER),
0201     REGISTER_BZ(INT_EN_CHAR),
0202     REGISTER_AZ(INT_ADR_KER),
0203     REGISTER_BZ(INT_ADR_CHAR),
0204     /* INT_ACK_KER is WO */
0205     /* INT_ISR0 is RC */
0206     REGISTER_AZ(HW_INIT),
0207     REGISTER_CZ(USR_EV_CFG),
0208     REGISTER_AB(EE_SPI_HCMD),
0209     REGISTER_AB(EE_SPI_HADR),
0210     REGISTER_AB(EE_SPI_HDATA),
0211     REGISTER_AB(EE_BASE_PAGE),
0212     REGISTER_AB(EE_VPD_CFG0),
0213     /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
0214     /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
0215     /* PCIE_CORE_INDIRECT is indirect */
0216     REGISTER_AB(NIC_STAT),
0217     REGISTER_AB(GPIO_CTL),
0218     REGISTER_AB(GLB_CTL),
0219     /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
0220     REGISTER_BZ(DP_CTRL),
0221     REGISTER_AZ(MEM_STAT),
0222     REGISTER_AZ(CS_DEBUG),
0223     REGISTER_AZ(ALTERA_BUILD),
0224     REGISTER_AZ(CSR_SPARE),
0225     REGISTER_AB(PCIE_SD_CTL0123),
0226     REGISTER_AB(PCIE_SD_CTL45),
0227     REGISTER_AB(PCIE_PCS_CTL_STAT),
0228     /* DEBUG_DATA_OUT is not used */
0229     /* DRV_EV is WO */
0230     REGISTER_AZ(EVQ_CTL),
0231     REGISTER_AZ(EVQ_CNT1),
0232     REGISTER_AZ(EVQ_CNT2),
0233     REGISTER_AZ(BUF_TBL_CFG),
0234     REGISTER_AZ(SRM_RX_DC_CFG),
0235     REGISTER_AZ(SRM_TX_DC_CFG),
0236     REGISTER_AZ(SRM_CFG),
0237     /* BUF_TBL_UPD is WO */
0238     REGISTER_AZ(SRM_UPD_EVQ),
0239     REGISTER_AZ(SRAM_PARITY),
0240     REGISTER_AZ(RX_CFG),
0241     REGISTER_BZ(RX_FILTER_CTL),
0242     /* RX_FLUSH_DESCQ is WO */
0243     REGISTER_AZ(RX_DC_CFG),
0244     REGISTER_AZ(RX_DC_PF_WM),
0245     REGISTER_BZ(RX_RSS_TKEY),
0246     /* RX_NODESC_DROP is RC */
0247     REGISTER_AA(RX_SELF_RST),
0248     /* RX_DEBUG, RX_PUSH_DROP are not used */
0249     REGISTER_CZ(RX_RSS_IPV6_REG1),
0250     REGISTER_CZ(RX_RSS_IPV6_REG2),
0251     REGISTER_CZ(RX_RSS_IPV6_REG3),
0252     /* TX_FLUSH_DESCQ is WO */
0253     REGISTER_AZ(TX_DC_CFG),
0254     REGISTER_AA(TX_CHKSM_CFG),
0255     REGISTER_AZ(TX_CFG),
0256     /* TX_PUSH_DROP is not used */
0257     REGISTER_AZ(TX_RESERVED),
0258     REGISTER_BZ(TX_PACE),
0259     /* TX_PACE_DROP_QID is RC */
0260     REGISTER_BB(TX_VLAN),
0261     REGISTER_BZ(TX_IPFIL_PORTEN),
0262     REGISTER_AB(MD_TXD),
0263     REGISTER_AB(MD_RXD),
0264     REGISTER_AB(MD_CS),
0265     REGISTER_AB(MD_PHY_ADR),
0266     REGISTER_AB(MD_ID),
0267     /* MD_STAT is RC */
0268     REGISTER_AB(MAC_STAT_DMA),
0269     REGISTER_AB(MAC_CTRL),
0270     REGISTER_BB(GEN_MODE),
0271     REGISTER_AB(MAC_MC_HASH_REG0),
0272     REGISTER_AB(MAC_MC_HASH_REG1),
0273     REGISTER_AB(GM_CFG1),
0274     REGISTER_AB(GM_CFG2),
0275     /* GM_IPG and GM_HD are not used */
0276     REGISTER_AB(GM_MAX_FLEN),
0277     /* GM_TEST is not used */
0278     REGISTER_AB(GM_ADR1),
0279     REGISTER_AB(GM_ADR2),
0280     REGISTER_AB(GMF_CFG0),
0281     REGISTER_AB(GMF_CFG1),
0282     REGISTER_AB(GMF_CFG2),
0283     REGISTER_AB(GMF_CFG3),
0284     REGISTER_AB(GMF_CFG4),
0285     REGISTER_AB(GMF_CFG5),
0286     REGISTER_BB(TX_SRC_MAC_CTL),
0287     REGISTER_AB(XM_ADR_LO),
0288     REGISTER_AB(XM_ADR_HI),
0289     REGISTER_AB(XM_GLB_CFG),
0290     REGISTER_AB(XM_TX_CFG),
0291     REGISTER_AB(XM_RX_CFG),
0292     REGISTER_AB(XM_MGT_INT_MASK),
0293     REGISTER_AB(XM_FC),
0294     REGISTER_AB(XM_PAUSE_TIME),
0295     REGISTER_AB(XM_TX_PARAM),
0296     REGISTER_AB(XM_RX_PARAM),
0297     /* XM_MGT_INT_MSK (note no 'A') is RC */
0298     REGISTER_AB(XX_PWR_RST),
0299     REGISTER_AB(XX_SD_CTL),
0300     REGISTER_AB(XX_TXDRV_CTL),
0301     /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
0302     /* XX_CORE_STAT is partly RC */
0303 };
0304 
0305 struct efx_nic_reg_table {
0306     u32 offset:24;
0307     u32 min_revision:3, max_revision:3;
0308     u32 step:6, rows:21;
0309 };
0310 
0311 #define REGISTER_TABLE_DIMENSIONS(_, offset, arch, min_rev, max_rev, step, rows) { \
0312     offset,                             \
0313     REGISTER_REVISION_ ## arch ## min_rev,              \
0314     REGISTER_REVISION_ ## arch ## max_rev,              \
0315     step, rows                          \
0316 }
0317 #define REGISTER_TABLE(name, arch, min_rev, max_rev)            \
0318     REGISTER_TABLE_DIMENSIONS(                  \
0319         name, arch ## R_ ## min_rev ## max_rev ## _ ## name,    \
0320         arch, min_rev, max_rev,                 \
0321         arch ## R_ ## min_rev ## max_rev ## _ ## name ## _STEP, \
0322         arch ## R_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
0323 #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, F, A, A)
0324 #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, F, A, Z)
0325 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, F, B, B)
0326 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, F, B, Z)
0327 #define REGISTER_TABLE_BB_CZ(name)                  \
0328     REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, B, B,    \
0329                   FR_BZ_ ## name ## _STEP,      \
0330                   FR_BB_ ## name ## _ROWS),     \
0331     REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, C, Z,    \
0332                   FR_BZ_ ## name ## _STEP,      \
0333                   FR_CZ_ ## name ## _ROWS)
0334 #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, F, C, Z)
0335 
0336 static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
0337     /* DRIVER is not used */
0338     /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
0339     REGISTER_TABLE_BB(TX_IPFIL_TBL),
0340     REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
0341     REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
0342     REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
0343     REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
0344     REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
0345     REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
0346     REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
0347     /* We can't reasonably read all of the buffer table (up to 8MB!).
0348      * However this driver will only use a few entries.  Reading
0349      * 1K entries allows for some expansion of queue count and
0350      * size before we need to change the version. */
0351     REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
0352                   F, A, A, 8, 1024),
0353     REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
0354                   F, B, Z, 8, 1024),
0355     REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
0356     REGISTER_TABLE_BB_CZ(TIMER_TBL),
0357     REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
0358     REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
0359     /* TX_FILTER_TBL0 is huge and not used by this driver */
0360     REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
0361     REGISTER_TABLE_CZ(MC_TREG_SMEM),
0362     /* MSIX_PBA_TABLE is not mapped */
0363     /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
0364     REGISTER_TABLE_BZ(RX_FILTER_TBL0),
0365 };
0366 
0367 size_t efx_siena_get_regs_len(struct efx_nic *efx)
0368 {
0369     const struct efx_nic_reg *reg;
0370     const struct efx_nic_reg_table *table;
0371     size_t len = 0;
0372 
0373     for (reg = efx_nic_regs;
0374          reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
0375          reg++)
0376         if (efx->type->revision >= reg->min_revision &&
0377             efx->type->revision <= reg->max_revision)
0378             len += sizeof(efx_oword_t);
0379 
0380     for (table = efx_nic_reg_tables;
0381          table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
0382          table++)
0383         if (efx->type->revision >= table->min_revision &&
0384             efx->type->revision <= table->max_revision)
0385             len += table->rows * min_t(size_t, table->step, 16);
0386 
0387     return len;
0388 }
0389 
0390 void efx_siena_get_regs(struct efx_nic *efx, void *buf)
0391 {
0392     const struct efx_nic_reg *reg;
0393     const struct efx_nic_reg_table *table;
0394 
0395     for (reg = efx_nic_regs;
0396          reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
0397          reg++) {
0398         if (efx->type->revision >= reg->min_revision &&
0399             efx->type->revision <= reg->max_revision) {
0400             efx_reado(efx, (efx_oword_t *)buf, reg->offset);
0401             buf += sizeof(efx_oword_t);
0402         }
0403     }
0404 
0405     for (table = efx_nic_reg_tables;
0406          table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
0407          table++) {
0408         size_t size, i;
0409 
0410         if (!(efx->type->revision >= table->min_revision &&
0411               efx->type->revision <= table->max_revision))
0412             continue;
0413 
0414         size = min_t(size_t, table->step, 16);
0415 
0416         for (i = 0; i < table->rows; i++) {
0417             switch (table->step) {
0418             case 4: /* 32-bit SRAM */
0419                 efx_readd(efx, buf, table->offset + 4 * i);
0420                 break;
0421             case 8: /* 64-bit SRAM */
0422                 efx_sram_readq(efx,
0423                            efx->membase + table->offset,
0424                            buf, i);
0425                 break;
0426             case 16: /* 128-bit-readable register */
0427                 efx_reado_table(efx, buf, table->offset, i);
0428                 break;
0429             case 32: /* 128-bit register, interleaved */
0430                 efx_reado_table(efx, buf, table->offset, 2 * i);
0431                 break;
0432             default:
0433                 WARN_ON(1);
0434                 return;
0435             }
0436             buf += size;
0437         }
0438     }
0439 }
0440 
0441 /**
0442  * efx_siena_describe_stats - Describe supported statistics for ethtool
0443  * @desc: Array of &struct efx_hw_stat_desc describing the statistics
0444  * @count: Length of the @desc array
0445  * @mask: Bitmask of which elements of @desc are enabled
0446  * @names: Buffer to copy names to, or %NULL.  The names are copied
0447  *  starting at intervals of %ETH_GSTRING_LEN bytes.
0448  *
0449  * Returns the number of visible statistics, i.e. the number of set
0450  * bits in the first @count bits of @mask for which a name is defined.
0451  */
0452 size_t efx_siena_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
0453                 const unsigned long *mask, u8 *names)
0454 {
0455     size_t visible = 0;
0456     size_t index;
0457 
0458     for_each_set_bit(index, mask, count) {
0459         if (desc[index].name) {
0460             if (names) {
0461                 strlcpy(names, desc[index].name,
0462                     ETH_GSTRING_LEN);
0463                 names += ETH_GSTRING_LEN;
0464             }
0465             ++visible;
0466         }
0467     }
0468 
0469     return visible;
0470 }
0471 
0472 /**
0473  * efx_siena_update_stats - Convert statistics DMA buffer to array of u64
0474  * @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer
0475  *  layout.  DMA widths of 0, 16, 32 and 64 are supported; where
0476  *  the width is specified as 0 the corresponding element of
0477  *  @stats is not updated.
0478  * @count: Length of the @desc array
0479  * @mask: Bitmask of which elements of @desc are enabled
0480  * @stats: Buffer to update with the converted statistics.  The length
0481  *  of this array must be at least @count.
0482  * @dma_buf: DMA buffer containing hardware statistics
0483  * @accumulate: If set, the converted values will be added rather than
0484  *  directly stored to the corresponding elements of @stats
0485  */
0486 void efx_siena_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
0487                 const unsigned long *mask,
0488                 u64 *stats, const void *dma_buf, bool accumulate)
0489 {
0490     size_t index;
0491 
0492     for_each_set_bit(index, mask, count) {
0493         if (desc[index].dma_width) {
0494             const void *addr = dma_buf + desc[index].offset;
0495             u64 val;
0496 
0497             switch (desc[index].dma_width) {
0498             case 16:
0499                 val = le16_to_cpup((__le16 *)addr);
0500                 break;
0501             case 32:
0502                 val = le32_to_cpup((__le32 *)addr);
0503                 break;
0504             case 64:
0505                 val = le64_to_cpup((__le64 *)addr);
0506                 break;
0507             default:
0508                 WARN_ON(1);
0509                 val = 0;
0510                 break;
0511             }
0512 
0513             if (accumulate)
0514                 stats[index] += val;
0515             else
0516                 stats[index] = val;
0517         }
0518     }
0519 }
0520 
0521 void efx_siena_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *rx_nodesc_drops)
0522 {
0523     /* if down, or this is the first update after coming up */
0524     if (!(efx->net_dev->flags & IFF_UP) || !efx->rx_nodesc_drops_prev_state)
0525         efx->rx_nodesc_drops_while_down +=
0526             *rx_nodesc_drops - efx->rx_nodesc_drops_total;
0527     efx->rx_nodesc_drops_total = *rx_nodesc_drops;
0528     efx->rx_nodesc_drops_prev_state = !!(efx->net_dev->flags & IFF_UP);
0529     *rx_nodesc_drops -= efx->rx_nodesc_drops_while_down;
0530 }
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