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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /****************************************************************************
0003  * Driver for Solarflare network controllers and boards
0004  * Copyright 2018 Solarflare Communications Inc.
0005  *
0006  * This program is free software; you can redistribute it and/or modify it
0007  * under the terms of the GNU General Public License version 2 as published
0008  * by the Free Software Foundation, incorporated herein by reference.
0009  */
0010 
0011 #include "net_driver.h"
0012 #include <linux/filter.h>
0013 #include <linux/module.h>
0014 #include <linux/netdevice.h>
0015 #include <net/gre.h>
0016 #include "efx_common.h"
0017 #include "efx_channels.h"
0018 #include "efx.h"
0019 #include "mcdi.h"
0020 #include "selftest.h"
0021 #include "rx_common.h"
0022 #include "tx_common.h"
0023 #include "nic.h"
0024 #include "mcdi_port_common.h"
0025 #include "io.h"
0026 #include "mcdi_pcol.h"
0027 
0028 static unsigned int debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
0029                  NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
0030                  NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
0031                  NETIF_MSG_TX_ERR | NETIF_MSG_HW);
0032 module_param(debug, uint, 0);
0033 MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
0034 
0035 /* This is the time (in jiffies) between invocations of the hardware
0036  * monitor.
0037  * On Falcon-based NICs, this will:
0038  * - Check the on-board hardware monitor;
0039  * - Poll the link state and reconfigure the hardware as necessary.
0040  * On Siena-based NICs for power systems with EEH support, this will give EEH a
0041  * chance to start.
0042  */
0043 static unsigned int efx_monitor_interval = 1 * HZ;
0044 
0045 /* How often and how many times to poll for a reset while waiting for a
0046  * BIST that another function started to complete.
0047  */
0048 #define BIST_WAIT_DELAY_MS  100
0049 #define BIST_WAIT_DELAY_COUNT   100
0050 
0051 /* Default stats update time */
0052 #define STATS_PERIOD_MS_DEFAULT 1000
0053 
0054 static const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
0055 static const char *const efx_reset_type_names[] = {
0056     [RESET_TYPE_INVISIBLE]          = "INVISIBLE",
0057     [RESET_TYPE_ALL]                = "ALL",
0058     [RESET_TYPE_RECOVER_OR_ALL]     = "RECOVER_OR_ALL",
0059     [RESET_TYPE_WORLD]              = "WORLD",
0060     [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
0061     [RESET_TYPE_DATAPATH]           = "DATAPATH",
0062     [RESET_TYPE_MC_BIST]        = "MC_BIST",
0063     [RESET_TYPE_DISABLE]            = "DISABLE",
0064     [RESET_TYPE_TX_WATCHDOG]        = "TX_WATCHDOG",
0065     [RESET_TYPE_INT_ERROR]          = "INT_ERROR",
0066     [RESET_TYPE_DMA_ERROR]          = "DMA_ERROR",
0067     [RESET_TYPE_TX_SKIP]            = "TX_SKIP",
0068     [RESET_TYPE_MC_FAILURE]         = "MC_FAILURE",
0069     [RESET_TYPE_MCDI_TIMEOUT]   = "MCDI_TIMEOUT (FLR)",
0070 };
0071 
0072 #define RESET_TYPE(type) \
0073     STRING_TABLE_LOOKUP(type, efx_reset_type)
0074 
0075 /* Loopback mode names (see LOOPBACK_MODE()) */
0076 const unsigned int efx_siena_loopback_mode_max = LOOPBACK_MAX;
0077 const char *const efx_siena_loopback_mode_names[] = {
0078     [LOOPBACK_NONE]     = "NONE",
0079     [LOOPBACK_DATA]     = "DATAPATH",
0080     [LOOPBACK_GMAC]     = "GMAC",
0081     [LOOPBACK_XGMII]    = "XGMII",
0082     [LOOPBACK_XGXS]     = "XGXS",
0083     [LOOPBACK_XAUI]     = "XAUI",
0084     [LOOPBACK_GMII]     = "GMII",
0085     [LOOPBACK_SGMII]    = "SGMII",
0086     [LOOPBACK_XGBR]     = "XGBR",
0087     [LOOPBACK_XFI]      = "XFI",
0088     [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
0089     [LOOPBACK_GMII_FAR] = "GMII_FAR",
0090     [LOOPBACK_SGMII_FAR]    = "SGMII_FAR",
0091     [LOOPBACK_XFI_FAR]  = "XFI_FAR",
0092     [LOOPBACK_GPHY]     = "GPHY",
0093     [LOOPBACK_PHYXS]    = "PHYXS",
0094     [LOOPBACK_PCS]      = "PCS",
0095     [LOOPBACK_PMAPMD]   = "PMA/PMD",
0096     [LOOPBACK_XPORT]    = "XPORT",
0097     [LOOPBACK_XGMII_WS] = "XGMII_WS",
0098     [LOOPBACK_XAUI_WS]  = "XAUI_WS",
0099     [LOOPBACK_XAUI_WS_FAR]  = "XAUI_WS_FAR",
0100     [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
0101     [LOOPBACK_GMII_WS]  = "GMII_WS",
0102     [LOOPBACK_XFI_WS]   = "XFI_WS",
0103     [LOOPBACK_XFI_WS_FAR]   = "XFI_WS_FAR",
0104     [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
0105 };
0106 
0107 /* Reset workqueue. If any NIC has a hardware failure then a reset will be
0108  * queued onto this work queue. This is not a per-nic work queue, because
0109  * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
0110  */
0111 static struct workqueue_struct *reset_workqueue;
0112 
0113 int efx_siena_create_reset_workqueue(void)
0114 {
0115     reset_workqueue = create_singlethread_workqueue("sfc_siena_reset");
0116     if (!reset_workqueue) {
0117         printk(KERN_ERR "Failed to create reset workqueue\n");
0118         return -ENOMEM;
0119     }
0120 
0121     return 0;
0122 }
0123 
0124 void efx_siena_queue_reset_work(struct efx_nic *efx)
0125 {
0126     queue_work(reset_workqueue, &efx->reset_work);
0127 }
0128 
0129 void efx_siena_flush_reset_workqueue(struct efx_nic *efx)
0130 {
0131     cancel_work_sync(&efx->reset_work);
0132 }
0133 
0134 void efx_siena_destroy_reset_workqueue(void)
0135 {
0136     if (reset_workqueue) {
0137         destroy_workqueue(reset_workqueue);
0138         reset_workqueue = NULL;
0139     }
0140 }
0141 
0142 /* We assume that efx->type->reconfigure_mac will always try to sync RX
0143  * filters and therefore needs to read-lock the filter table against freeing
0144  */
0145 void efx_siena_mac_reconfigure(struct efx_nic *efx, bool mtu_only)
0146 {
0147     if (efx->type->reconfigure_mac) {
0148         down_read(&efx->filter_sem);
0149         efx->type->reconfigure_mac(efx, mtu_only);
0150         up_read(&efx->filter_sem);
0151     }
0152 }
0153 
0154 /* Asynchronous work item for changing MAC promiscuity and multicast
0155  * hash.  Avoid a drain/rx_ingress enable by reconfiguring the current
0156  * MAC directly.
0157  */
0158 static void efx_mac_work(struct work_struct *data)
0159 {
0160     struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
0161 
0162     mutex_lock(&efx->mac_lock);
0163     if (efx->port_enabled)
0164         efx_siena_mac_reconfigure(efx, false);
0165     mutex_unlock(&efx->mac_lock);
0166 }
0167 
0168 int efx_siena_set_mac_address(struct net_device *net_dev, void *data)
0169 {
0170     struct efx_nic *efx = netdev_priv(net_dev);
0171     struct sockaddr *addr = data;
0172     u8 *new_addr = addr->sa_data;
0173     u8 old_addr[6];
0174     int rc;
0175 
0176     if (!is_valid_ether_addr(new_addr)) {
0177         netif_err(efx, drv, efx->net_dev,
0178               "invalid ethernet MAC address requested: %pM\n",
0179               new_addr);
0180         return -EADDRNOTAVAIL;
0181     }
0182 
0183     /* save old address */
0184     ether_addr_copy(old_addr, net_dev->dev_addr);
0185     eth_hw_addr_set(net_dev, new_addr);
0186     if (efx->type->set_mac_address) {
0187         rc = efx->type->set_mac_address(efx);
0188         if (rc) {
0189             eth_hw_addr_set(net_dev, old_addr);
0190             return rc;
0191         }
0192     }
0193 
0194     /* Reconfigure the MAC */
0195     mutex_lock(&efx->mac_lock);
0196     efx_siena_mac_reconfigure(efx, false);
0197     mutex_unlock(&efx->mac_lock);
0198 
0199     return 0;
0200 }
0201 
0202 /* Context: netif_addr_lock held, BHs disabled. */
0203 void efx_siena_set_rx_mode(struct net_device *net_dev)
0204 {
0205     struct efx_nic *efx = netdev_priv(net_dev);
0206 
0207     if (efx->port_enabled)
0208         queue_work(efx->workqueue, &efx->mac_work);
0209     /* Otherwise efx_start_port() will do this */
0210 }
0211 
0212 int efx_siena_set_features(struct net_device *net_dev, netdev_features_t data)
0213 {
0214     struct efx_nic *efx = netdev_priv(net_dev);
0215     int rc;
0216 
0217     /* If disabling RX n-tuple filtering, clear existing filters */
0218     if (net_dev->features & ~data & NETIF_F_NTUPLE) {
0219         rc = efx->type->filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
0220         if (rc)
0221             return rc;
0222     }
0223 
0224     /* If Rx VLAN filter is changed, update filters via mac_reconfigure.
0225      * If rx-fcs is changed, mac_reconfigure updates that too.
0226      */
0227     if ((net_dev->features ^ data) & (NETIF_F_HW_VLAN_CTAG_FILTER |
0228                       NETIF_F_RXFCS)) {
0229         /* efx_siena_set_rx_mode() will schedule MAC work to update filters
0230          * when a new features are finally set in net_dev.
0231          */
0232         efx_siena_set_rx_mode(net_dev);
0233     }
0234 
0235     return 0;
0236 }
0237 
0238 /* This ensures that the kernel is kept informed (via
0239  * netif_carrier_on/off) of the link status, and also maintains the
0240  * link status's stop on the port's TX queue.
0241  */
0242 void efx_siena_link_status_changed(struct efx_nic *efx)
0243 {
0244     struct efx_link_state *link_state = &efx->link_state;
0245 
0246     /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
0247      * that no events are triggered between unregister_netdev() and the
0248      * driver unloading. A more general condition is that NETDEV_CHANGE
0249      * can only be generated between NETDEV_UP and NETDEV_DOWN
0250      */
0251     if (!netif_running(efx->net_dev))
0252         return;
0253 
0254     if (link_state->up != netif_carrier_ok(efx->net_dev)) {
0255         efx->n_link_state_changes++;
0256 
0257         if (link_state->up)
0258             netif_carrier_on(efx->net_dev);
0259         else
0260             netif_carrier_off(efx->net_dev);
0261     }
0262 
0263     /* Status message for kernel log */
0264     if (link_state->up)
0265         netif_info(efx, link, efx->net_dev,
0266                "link up at %uMbps %s-duplex (MTU %d)\n",
0267                link_state->speed, link_state->fd ? "full" : "half",
0268                efx->net_dev->mtu);
0269     else
0270         netif_info(efx, link, efx->net_dev, "link down\n");
0271 }
0272 
0273 unsigned int efx_siena_xdp_max_mtu(struct efx_nic *efx)
0274 {
0275     /* The maximum MTU that we can fit in a single page, allowing for
0276      * framing, overhead and XDP headroom + tailroom.
0277      */
0278     int overhead = EFX_MAX_FRAME_LEN(0) + sizeof(struct efx_rx_page_state) +
0279                efx->rx_prefix_size + efx->type->rx_buffer_padding +
0280                efx->rx_ip_align + EFX_XDP_HEADROOM + EFX_XDP_TAILROOM;
0281 
0282     return PAGE_SIZE - overhead;
0283 }
0284 
0285 /* Context: process, rtnl_lock() held. */
0286 int efx_siena_change_mtu(struct net_device *net_dev, int new_mtu)
0287 {
0288     struct efx_nic *efx = netdev_priv(net_dev);
0289     int rc;
0290 
0291     rc = efx_check_disabled(efx);
0292     if (rc)
0293         return rc;
0294 
0295     if (rtnl_dereference(efx->xdp_prog) &&
0296         new_mtu > efx_siena_xdp_max_mtu(efx)) {
0297         netif_err(efx, drv, efx->net_dev,
0298               "Requested MTU of %d too big for XDP (max: %d)\n",
0299               new_mtu, efx_siena_xdp_max_mtu(efx));
0300         return -EINVAL;
0301     }
0302 
0303     netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
0304 
0305     efx_device_detach_sync(efx);
0306     efx_siena_stop_all(efx);
0307 
0308     mutex_lock(&efx->mac_lock);
0309     net_dev->mtu = new_mtu;
0310     efx_siena_mac_reconfigure(efx, true);
0311     mutex_unlock(&efx->mac_lock);
0312 
0313     efx_siena_start_all(efx);
0314     efx_device_attach_if_not_resetting(efx);
0315     return 0;
0316 }
0317 
0318 /**************************************************************************
0319  *
0320  * Hardware monitor
0321  *
0322  **************************************************************************/
0323 
0324 /* Run periodically off the general workqueue */
0325 static void efx_monitor(struct work_struct *data)
0326 {
0327     struct efx_nic *efx = container_of(data, struct efx_nic,
0328                        monitor_work.work);
0329 
0330     netif_vdbg(efx, timer, efx->net_dev,
0331            "hardware monitor executing on CPU %d\n",
0332            raw_smp_processor_id());
0333     BUG_ON(efx->type->monitor == NULL);
0334 
0335     /* If the mac_lock is already held then it is likely a port
0336      * reconfiguration is already in place, which will likely do
0337      * most of the work of monitor() anyway.
0338      */
0339     if (mutex_trylock(&efx->mac_lock)) {
0340         if (efx->port_enabled && efx->type->monitor)
0341             efx->type->monitor(efx);
0342         mutex_unlock(&efx->mac_lock);
0343     }
0344 
0345     efx_siena_start_monitor(efx);
0346 }
0347 
0348 void efx_siena_start_monitor(struct efx_nic *efx)
0349 {
0350     if (efx->type->monitor)
0351         queue_delayed_work(efx->workqueue, &efx->monitor_work,
0352                    efx_monitor_interval);
0353 }
0354 
0355 /**************************************************************************
0356  *
0357  * Event queue processing
0358  *
0359  *************************************************************************/
0360 
0361 /* Channels are shutdown and reinitialised whilst the NIC is running
0362  * to propagate configuration changes (mtu, checksum offload), or
0363  * to clear hardware error conditions
0364  */
0365 static void efx_start_datapath(struct efx_nic *efx)
0366 {
0367     netdev_features_t old_features = efx->net_dev->features;
0368     bool old_rx_scatter = efx->rx_scatter;
0369     size_t rx_buf_len;
0370 
0371     /* Calculate the rx buffer allocation parameters required to
0372      * support the current MTU, including padding for header
0373      * alignment and overruns.
0374      */
0375     efx->rx_dma_len = (efx->rx_prefix_size +
0376                EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
0377                efx->type->rx_buffer_padding);
0378     rx_buf_len = (sizeof(struct efx_rx_page_state)   + EFX_XDP_HEADROOM +
0379               efx->rx_ip_align + efx->rx_dma_len + EFX_XDP_TAILROOM);
0380 
0381     if (rx_buf_len <= PAGE_SIZE) {
0382         efx->rx_scatter = efx->type->always_rx_scatter;
0383         efx->rx_buffer_order = 0;
0384     } else if (efx->type->can_rx_scatter) {
0385         BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);
0386         BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
0387                  2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE,
0388                        EFX_RX_BUF_ALIGNMENT) >
0389                  PAGE_SIZE);
0390         efx->rx_scatter = true;
0391         efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
0392         efx->rx_buffer_order = 0;
0393     } else {
0394         efx->rx_scatter = false;
0395         efx->rx_buffer_order = get_order(rx_buf_len);
0396     }
0397 
0398     efx_siena_rx_config_page_split(efx);
0399     if (efx->rx_buffer_order)
0400         netif_dbg(efx, drv, efx->net_dev,
0401               "RX buf len=%u; page order=%u batch=%u\n",
0402               efx->rx_dma_len, efx->rx_buffer_order,
0403               efx->rx_pages_per_batch);
0404     else
0405         netif_dbg(efx, drv, efx->net_dev,
0406               "RX buf len=%u step=%u bpp=%u; page batch=%u\n",
0407               efx->rx_dma_len, efx->rx_page_buf_step,
0408               efx->rx_bufs_per_page, efx->rx_pages_per_batch);
0409 
0410     /* Restore previously fixed features in hw_features and remove
0411      * features which are fixed now
0412      */
0413     efx->net_dev->hw_features |= efx->net_dev->features;
0414     efx->net_dev->hw_features &= ~efx->fixed_features;
0415     efx->net_dev->features |= efx->fixed_features;
0416     if (efx->net_dev->features != old_features)
0417         netdev_features_change(efx->net_dev);
0418 
0419     /* RX filters may also have scatter-enabled flags */
0420     if ((efx->rx_scatter != old_rx_scatter) &&
0421         efx->type->filter_update_rx_scatter)
0422         efx->type->filter_update_rx_scatter(efx);
0423 
0424     /* We must keep at least one descriptor in a TX ring empty.
0425      * We could avoid this when the queue size does not exactly
0426      * match the hardware ring size, but it's not that important.
0427      * Therefore we stop the queue when one more skb might fill
0428      * the ring completely.  We wake it when half way back to
0429      * empty.
0430      */
0431     efx->txq_stop_thresh = efx->txq_entries - efx_siena_tx_max_skb_descs(efx);
0432     efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
0433 
0434     /* Initialise the channels */
0435     efx_siena_start_channels(efx);
0436 
0437     efx_siena_ptp_start_datapath(efx);
0438 
0439     if (netif_device_present(efx->net_dev))
0440         netif_tx_wake_all_queues(efx->net_dev);
0441 }
0442 
0443 static void efx_stop_datapath(struct efx_nic *efx)
0444 {
0445     EFX_ASSERT_RESET_SERIALISED(efx);
0446     BUG_ON(efx->port_enabled);
0447 
0448     efx_siena_ptp_stop_datapath(efx);
0449 
0450     efx_siena_stop_channels(efx);
0451 }
0452 
0453 /**************************************************************************
0454  *
0455  * Port handling
0456  *
0457  **************************************************************************/
0458 
0459 /* Equivalent to efx_siena_link_set_advertising with all-zeroes, except does not
0460  * force the Autoneg bit on.
0461  */
0462 void efx_siena_link_clear_advertising(struct efx_nic *efx)
0463 {
0464     bitmap_zero(efx->link_advertising, __ETHTOOL_LINK_MODE_MASK_NBITS);
0465     efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
0466 }
0467 
0468 void efx_siena_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
0469 {
0470     efx->wanted_fc = wanted_fc;
0471     if (efx->link_advertising[0]) {
0472         if (wanted_fc & EFX_FC_RX)
0473             efx->link_advertising[0] |= (ADVERTISED_Pause |
0474                              ADVERTISED_Asym_Pause);
0475         else
0476             efx->link_advertising[0] &= ~(ADVERTISED_Pause |
0477                               ADVERTISED_Asym_Pause);
0478         if (wanted_fc & EFX_FC_TX)
0479             efx->link_advertising[0] ^= ADVERTISED_Asym_Pause;
0480     }
0481 }
0482 
0483 static void efx_start_port(struct efx_nic *efx)
0484 {
0485     netif_dbg(efx, ifup, efx->net_dev, "start port\n");
0486     BUG_ON(efx->port_enabled);
0487 
0488     mutex_lock(&efx->mac_lock);
0489     efx->port_enabled = true;
0490 
0491     /* Ensure MAC ingress/egress is enabled */
0492     efx_siena_mac_reconfigure(efx, false);
0493 
0494     mutex_unlock(&efx->mac_lock);
0495 }
0496 
0497 /* Cancel work for MAC reconfiguration, periodic hardware monitoring
0498  * and the async self-test, wait for them to finish and prevent them
0499  * being scheduled again.  This doesn't cover online resets, which
0500  * should only be cancelled when removing the device.
0501  */
0502 static void efx_stop_port(struct efx_nic *efx)
0503 {
0504     netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
0505 
0506     EFX_ASSERT_RESET_SERIALISED(efx);
0507 
0508     mutex_lock(&efx->mac_lock);
0509     efx->port_enabled = false;
0510     mutex_unlock(&efx->mac_lock);
0511 
0512     /* Serialise against efx_set_multicast_list() */
0513     netif_addr_lock_bh(efx->net_dev);
0514     netif_addr_unlock_bh(efx->net_dev);
0515 
0516     cancel_delayed_work_sync(&efx->monitor_work);
0517     efx_siena_selftest_async_cancel(efx);
0518     cancel_work_sync(&efx->mac_work);
0519 }
0520 
0521 /* If the interface is supposed to be running but is not, start
0522  * the hardware and software data path, regular activity for the port
0523  * (MAC statistics, link polling, etc.) and schedule the port to be
0524  * reconfigured.  Interrupts must already be enabled.  This function
0525  * is safe to call multiple times, so long as the NIC is not disabled.
0526  * Requires the RTNL lock.
0527  */
0528 void efx_siena_start_all(struct efx_nic *efx)
0529 {
0530     EFX_ASSERT_RESET_SERIALISED(efx);
0531     BUG_ON(efx->state == STATE_DISABLED);
0532 
0533     /* Check that it is appropriate to restart the interface. All
0534      * of these flags are safe to read under just the rtnl lock
0535      */
0536     if (efx->port_enabled || !netif_running(efx->net_dev) ||
0537         efx->reset_pending)
0538         return;
0539 
0540     efx_start_port(efx);
0541     efx_start_datapath(efx);
0542 
0543     /* Start the hardware monitor if there is one */
0544     efx_siena_start_monitor(efx);
0545 
0546     /* Link state detection is normally event-driven; we have
0547      * to poll now because we could have missed a change
0548      */
0549     mutex_lock(&efx->mac_lock);
0550     if (efx_siena_mcdi_phy_poll(efx))
0551         efx_siena_link_status_changed(efx);
0552     mutex_unlock(&efx->mac_lock);
0553 
0554     if (efx->type->start_stats) {
0555         efx->type->start_stats(efx);
0556         efx->type->pull_stats(efx);
0557         spin_lock_bh(&efx->stats_lock);
0558         efx->type->update_stats(efx, NULL, NULL);
0559         spin_unlock_bh(&efx->stats_lock);
0560     }
0561 }
0562 
0563 /* Quiesce the hardware and software data path, and regular activity
0564  * for the port without bringing the link down.  Safe to call multiple
0565  * times with the NIC in almost any state, but interrupts should be
0566  * enabled.  Requires the RTNL lock.
0567  */
0568 void efx_siena_stop_all(struct efx_nic *efx)
0569 {
0570     EFX_ASSERT_RESET_SERIALISED(efx);
0571 
0572     /* port_enabled can be read safely under the rtnl lock */
0573     if (!efx->port_enabled)
0574         return;
0575 
0576     if (efx->type->update_stats) {
0577         /* update stats before we go down so we can accurately count
0578          * rx_nodesc_drops
0579          */
0580         efx->type->pull_stats(efx);
0581         spin_lock_bh(&efx->stats_lock);
0582         efx->type->update_stats(efx, NULL, NULL);
0583         spin_unlock_bh(&efx->stats_lock);
0584         efx->type->stop_stats(efx);
0585     }
0586 
0587     efx_stop_port(efx);
0588 
0589     /* Stop the kernel transmit interface.  This is only valid if
0590      * the device is stopped or detached; otherwise the watchdog
0591      * may fire immediately.
0592      */
0593     WARN_ON(netif_running(efx->net_dev) &&
0594         netif_device_present(efx->net_dev));
0595     netif_tx_disable(efx->net_dev);
0596 
0597     efx_stop_datapath(efx);
0598 }
0599 
0600 static size_t efx_siena_update_stats_atomic(struct efx_nic *efx, u64 *full_stats,
0601                         struct rtnl_link_stats64 *core_stats)
0602 {
0603     if (efx->type->update_stats_atomic)
0604         return efx->type->update_stats_atomic(efx, full_stats, core_stats);
0605     return efx->type->update_stats(efx, full_stats, core_stats);
0606 }
0607 
0608 /* Context: process, dev_base_lock or RTNL held, non-blocking. */
0609 void efx_siena_net_stats(struct net_device *net_dev,
0610              struct rtnl_link_stats64 *stats)
0611 {
0612     struct efx_nic *efx = netdev_priv(net_dev);
0613 
0614     spin_lock_bh(&efx->stats_lock);
0615     efx_siena_update_stats_atomic(efx, NULL, stats);
0616     spin_unlock_bh(&efx->stats_lock);
0617 }
0618 
0619 /* Push loopback/power/transmit disable settings to the PHY, and reconfigure
0620  * the MAC appropriately. All other PHY configuration changes are pushed
0621  * through phy_op->set_settings(), and pushed asynchronously to the MAC
0622  * through efx_monitor().
0623  *
0624  * Callers must hold the mac_lock
0625  */
0626 int __efx_siena_reconfigure_port(struct efx_nic *efx)
0627 {
0628     enum efx_phy_mode phy_mode;
0629     int rc = 0;
0630 
0631     WARN_ON(!mutex_is_locked(&efx->mac_lock));
0632 
0633     /* Disable PHY transmit in mac level loopbacks */
0634     phy_mode = efx->phy_mode;
0635     if (LOOPBACK_INTERNAL(efx))
0636         efx->phy_mode |= PHY_MODE_TX_DISABLED;
0637     else
0638         efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
0639 
0640     if (efx->type->reconfigure_port)
0641         rc = efx->type->reconfigure_port(efx);
0642 
0643     if (rc)
0644         efx->phy_mode = phy_mode;
0645 
0646     return rc;
0647 }
0648 
0649 /* Reinitialise the MAC to pick up new PHY settings, even if the port is
0650  * disabled.
0651  */
0652 int efx_siena_reconfigure_port(struct efx_nic *efx)
0653 {
0654     int rc;
0655 
0656     EFX_ASSERT_RESET_SERIALISED(efx);
0657 
0658     mutex_lock(&efx->mac_lock);
0659     rc = __efx_siena_reconfigure_port(efx);
0660     mutex_unlock(&efx->mac_lock);
0661 
0662     return rc;
0663 }
0664 
0665 /**************************************************************************
0666  *
0667  * Device reset and suspend
0668  *
0669  **************************************************************************/
0670 
0671 static void efx_wait_for_bist_end(struct efx_nic *efx)
0672 {
0673     int i;
0674 
0675     for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) {
0676         if (efx_siena_mcdi_poll_reboot(efx))
0677             goto out;
0678         msleep(BIST_WAIT_DELAY_MS);
0679     }
0680 
0681     netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n");
0682 out:
0683     /* Either way unset the BIST flag. If we found no reboot we probably
0684      * won't recover, but we should try.
0685      */
0686     efx->mc_bist_for_other_fn = false;
0687 }
0688 
0689 /* Try recovery mechanisms.
0690  * For now only EEH is supported.
0691  * Returns 0 if the recovery mechanisms are unsuccessful.
0692  * Returns a non-zero value otherwise.
0693  */
0694 int efx_siena_try_recovery(struct efx_nic *efx)
0695 {
0696 #ifdef CONFIG_EEH
0697     /* A PCI error can occur and not be seen by EEH because nothing
0698      * happens on the PCI bus. In this case the driver may fail and
0699      * schedule a 'recover or reset', leading to this recovery handler.
0700      * Manually call the eeh failure check function.
0701      */
0702     struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
0703     if (eeh_dev_check_failure(eehdev)) {
0704         /* The EEH mechanisms will handle the error and reset the
0705          * device if necessary.
0706          */
0707         return 1;
0708     }
0709 #endif
0710     return 0;
0711 }
0712 
0713 /* Tears down the entire software state and most of the hardware state
0714  * before reset.
0715  */
0716 void efx_siena_reset_down(struct efx_nic *efx, enum reset_type method)
0717 {
0718     EFX_ASSERT_RESET_SERIALISED(efx);
0719 
0720     if (method == RESET_TYPE_MCDI_TIMEOUT)
0721         efx->type->prepare_flr(efx);
0722 
0723     efx_siena_stop_all(efx);
0724     efx_siena_disable_interrupts(efx);
0725 
0726     mutex_lock(&efx->mac_lock);
0727     down_write(&efx->filter_sem);
0728     mutex_lock(&efx->rss_lock);
0729     efx->type->fini(efx);
0730 }
0731 
0732 /* Context: netif_tx_lock held, BHs disabled. */
0733 void efx_siena_watchdog(struct net_device *net_dev, unsigned int txqueue)
0734 {
0735     struct efx_nic *efx = netdev_priv(net_dev);
0736 
0737     netif_err(efx, tx_err, efx->net_dev,
0738           "TX stuck with port_enabled=%d: resetting channels\n",
0739           efx->port_enabled);
0740 
0741     efx_siena_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
0742 }
0743 
0744 /* This function will always ensure that the locks acquired in
0745  * efx_siena_reset_down() are released. A failure return code indicates
0746  * that we were unable to reinitialise the hardware, and the
0747  * driver should be disabled. If ok is false, then the rx and tx
0748  * engines are not restarted, pending a RESET_DISABLE.
0749  */
0750 int efx_siena_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
0751 {
0752     int rc;
0753 
0754     EFX_ASSERT_RESET_SERIALISED(efx);
0755 
0756     if (method == RESET_TYPE_MCDI_TIMEOUT)
0757         efx->type->finish_flr(efx);
0758 
0759     /* Ensure that SRAM is initialised even if we're disabling the device */
0760     rc = efx->type->init(efx);
0761     if (rc) {
0762         netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
0763         goto fail;
0764     }
0765 
0766     if (!ok)
0767         goto fail;
0768 
0769     if (efx->port_initialized && method != RESET_TYPE_INVISIBLE &&
0770         method != RESET_TYPE_DATAPATH) {
0771         rc = efx_siena_mcdi_port_reconfigure(efx);
0772         if (rc && rc != -EPERM)
0773             netif_err(efx, drv, efx->net_dev,
0774                   "could not restore PHY settings\n");
0775     }
0776 
0777     rc = efx_siena_enable_interrupts(efx);
0778     if (rc)
0779         goto fail;
0780 
0781 #ifdef CONFIG_SFC_SIENA_SRIOV
0782     rc = efx->type->vswitching_restore(efx);
0783     if (rc) /* not fatal; the PF will still work fine */
0784         netif_warn(efx, probe, efx->net_dev,
0785                "failed to restore vswitching rc=%d;"
0786                " VFs may not function\n", rc);
0787 #endif
0788 
0789     if (efx->type->rx_restore_rss_contexts)
0790         efx->type->rx_restore_rss_contexts(efx);
0791     mutex_unlock(&efx->rss_lock);
0792     efx->type->filter_table_restore(efx);
0793     up_write(&efx->filter_sem);
0794     if (efx->type->sriov_reset)
0795         efx->type->sriov_reset(efx);
0796 
0797     mutex_unlock(&efx->mac_lock);
0798 
0799     efx_siena_start_all(efx);
0800 
0801     if (efx->type->udp_tnl_push_ports)
0802         efx->type->udp_tnl_push_ports(efx);
0803 
0804     return 0;
0805 
0806 fail:
0807     efx->port_initialized = false;
0808 
0809     mutex_unlock(&efx->rss_lock);
0810     up_write(&efx->filter_sem);
0811     mutex_unlock(&efx->mac_lock);
0812 
0813     return rc;
0814 }
0815 
0816 /* Reset the NIC using the specified method.  Note that the reset may
0817  * fail, in which case the card will be left in an unusable state.
0818  *
0819  * Caller must hold the rtnl_lock.
0820  */
0821 int efx_siena_reset(struct efx_nic *efx, enum reset_type method)
0822 {
0823     int rc, rc2 = 0;
0824     bool disabled;
0825 
0826     netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
0827            RESET_TYPE(method));
0828 
0829     efx_device_detach_sync(efx);
0830     /* efx_siena_reset_down() grabs locks that prevent recovery on EF100.
0831      * EF100 reset is handled in the efx_nic_type callback below.
0832      */
0833     if (efx_nic_rev(efx) != EFX_REV_EF100)
0834         efx_siena_reset_down(efx, method);
0835 
0836     rc = efx->type->reset(efx, method);
0837     if (rc) {
0838         netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
0839         goto out;
0840     }
0841 
0842     /* Clear flags for the scopes we covered.  We assume the NIC and
0843      * driver are now quiescent so that there is no race here.
0844      */
0845     if (method < RESET_TYPE_MAX_METHOD)
0846         efx->reset_pending &= -(1 << (method + 1));
0847     else /* it doesn't fit into the well-ordered scope hierarchy */
0848         __clear_bit(method, &efx->reset_pending);
0849 
0850     /* Reinitialise bus-mastering, which may have been turned off before
0851      * the reset was scheduled. This is still appropriate, even in the
0852      * RESET_TYPE_DISABLE since this driver generally assumes the hardware
0853      * can respond to requests.
0854      */
0855     pci_set_master(efx->pci_dev);
0856 
0857 out:
0858     /* Leave device stopped if necessary */
0859     disabled = rc ||
0860         method == RESET_TYPE_DISABLE ||
0861         method == RESET_TYPE_RECOVER_OR_DISABLE;
0862     if (efx_nic_rev(efx) != EFX_REV_EF100)
0863         rc2 = efx_siena_reset_up(efx, method, !disabled);
0864     if (rc2) {
0865         disabled = true;
0866         if (!rc)
0867             rc = rc2;
0868     }
0869 
0870     if (disabled) {
0871         dev_close(efx->net_dev);
0872         netif_err(efx, drv, efx->net_dev, "has been disabled\n");
0873         efx->state = STATE_DISABLED;
0874     } else {
0875         netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
0876         efx_device_attach_if_not_resetting(efx);
0877     }
0878     return rc;
0879 }
0880 
0881 /* The worker thread exists so that code that cannot sleep can
0882  * schedule a reset for later.
0883  */
0884 static void efx_reset_work(struct work_struct *data)
0885 {
0886     struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
0887     unsigned long pending;
0888     enum reset_type method;
0889 
0890     pending = READ_ONCE(efx->reset_pending);
0891     method = fls(pending) - 1;
0892 
0893     if (method == RESET_TYPE_MC_BIST)
0894         efx_wait_for_bist_end(efx);
0895 
0896     if ((method == RESET_TYPE_RECOVER_OR_DISABLE ||
0897          method == RESET_TYPE_RECOVER_OR_ALL) &&
0898         efx_siena_try_recovery(efx))
0899         return;
0900 
0901     if (!pending)
0902         return;
0903 
0904     rtnl_lock();
0905 
0906     /* We checked the state in efx_siena_schedule_reset() but it may
0907      * have changed by now.  Now that we have the RTNL lock,
0908      * it cannot change again.
0909      */
0910     if (efx->state == STATE_READY)
0911         (void)efx_siena_reset(efx, method);
0912 
0913     rtnl_unlock();
0914 }
0915 
0916 void efx_siena_schedule_reset(struct efx_nic *efx, enum reset_type type)
0917 {
0918     enum reset_type method;
0919 
0920     if (efx->state == STATE_RECOVERY) {
0921         netif_dbg(efx, drv, efx->net_dev,
0922               "recovering: skip scheduling %s reset\n",
0923               RESET_TYPE(type));
0924         return;
0925     }
0926 
0927     switch (type) {
0928     case RESET_TYPE_INVISIBLE:
0929     case RESET_TYPE_ALL:
0930     case RESET_TYPE_RECOVER_OR_ALL:
0931     case RESET_TYPE_WORLD:
0932     case RESET_TYPE_DISABLE:
0933     case RESET_TYPE_RECOVER_OR_DISABLE:
0934     case RESET_TYPE_DATAPATH:
0935     case RESET_TYPE_MC_BIST:
0936     case RESET_TYPE_MCDI_TIMEOUT:
0937         method = type;
0938         netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
0939               RESET_TYPE(method));
0940         break;
0941     default:
0942         method = efx->type->map_reset_reason(type);
0943         netif_dbg(efx, drv, efx->net_dev,
0944               "scheduling %s reset for %s\n",
0945               RESET_TYPE(method), RESET_TYPE(type));
0946         break;
0947     }
0948 
0949     set_bit(method, &efx->reset_pending);
0950     smp_mb(); /* ensure we change reset_pending before checking state */
0951 
0952     /* If we're not READY then just leave the flags set as the cue
0953      * to abort probing or reschedule the reset later.
0954      */
0955     if (READ_ONCE(efx->state) != STATE_READY)
0956         return;
0957 
0958     /* efx_process_channel() will no longer read events once a
0959      * reset is scheduled. So switch back to poll'd MCDI completions.
0960      */
0961     efx_siena_mcdi_mode_poll(efx);
0962 
0963     efx_siena_queue_reset_work(efx);
0964 }
0965 
0966 /**************************************************************************
0967  *
0968  * Dummy NIC operations
0969  *
0970  * Can be used for some unimplemented operations
0971  * Needed so all function pointers are valid and do not have to be tested
0972  * before use
0973  *
0974  **************************************************************************/
0975 int efx_siena_port_dummy_op_int(struct efx_nic *efx)
0976 {
0977     return 0;
0978 }
0979 
0980 void efx_siena_port_dummy_op_void(struct efx_nic *efx) {}
0981 
0982 /**************************************************************************
0983  *
0984  * Data housekeeping
0985  *
0986  **************************************************************************/
0987 
0988 /* This zeroes out and then fills in the invariants in a struct
0989  * efx_nic (including all sub-structures).
0990  */
0991 int efx_siena_init_struct(struct efx_nic *efx,
0992               struct pci_dev *pci_dev, struct net_device *net_dev)
0993 {
0994     int rc = -ENOMEM;
0995 
0996     /* Initialise common structures */
0997     INIT_LIST_HEAD(&efx->node);
0998     INIT_LIST_HEAD(&efx->secondary_list);
0999     spin_lock_init(&efx->biu_lock);
1000 #ifdef CONFIG_SFC_SIENA_MTD
1001     INIT_LIST_HEAD(&efx->mtd_list);
1002 #endif
1003     INIT_WORK(&efx->reset_work, efx_reset_work);
1004     INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
1005     efx_siena_selftest_async_init(efx);
1006     efx->pci_dev = pci_dev;
1007     efx->msg_enable = debug;
1008     efx->state = STATE_UNINIT;
1009     strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
1010 
1011     efx->net_dev = net_dev;
1012     efx->rx_prefix_size = efx->type->rx_prefix_size;
1013     efx->rx_ip_align =
1014         NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0;
1015     efx->rx_packet_hash_offset =
1016         efx->type->rx_hash_offset - efx->type->rx_prefix_size;
1017     efx->rx_packet_ts_offset =
1018         efx->type->rx_ts_offset - efx->type->rx_prefix_size;
1019     INIT_LIST_HEAD(&efx->rss_context.list);
1020     efx->rss_context.context_id = EFX_MCDI_RSS_CONTEXT_INVALID;
1021     mutex_init(&efx->rss_lock);
1022     efx->vport_id = EVB_PORT_ID_ASSIGNED;
1023     spin_lock_init(&efx->stats_lock);
1024     efx->vi_stride = EFX_DEFAULT_VI_STRIDE;
1025     efx->num_mac_stats = MC_CMD_MAC_NSTATS;
1026     BUILD_BUG_ON(MC_CMD_MAC_NSTATS - 1 != MC_CMD_MAC_GENERATION_END);
1027     mutex_init(&efx->mac_lock);
1028     init_rwsem(&efx->filter_sem);
1029 #ifdef CONFIG_RFS_ACCEL
1030     mutex_init(&efx->rps_mutex);
1031     spin_lock_init(&efx->rps_hash_lock);
1032     /* Failure to allocate is not fatal, but may degrade ARFS performance */
1033     efx->rps_hash_table = kcalloc(EFX_ARFS_HASH_TABLE_SIZE,
1034                       sizeof(*efx->rps_hash_table), GFP_KERNEL);
1035 #endif
1036     efx->mdio.dev = net_dev;
1037     INIT_WORK(&efx->mac_work, efx_mac_work);
1038     init_waitqueue_head(&efx->flush_wq);
1039 
1040     efx->tx_queues_per_channel = 1;
1041     efx->rxq_entries = EFX_DEFAULT_DMAQ_SIZE;
1042     efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
1043 
1044     efx->mem_bar = UINT_MAX;
1045 
1046     rc = efx_siena_init_channels(efx);
1047     if (rc)
1048         goto fail;
1049 
1050     /* Would be good to use the net_dev name, but we're too early */
1051     snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
1052          pci_name(pci_dev));
1053     efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
1054     if (!efx->workqueue) {
1055         rc = -ENOMEM;
1056         goto fail;
1057     }
1058 
1059     return 0;
1060 
1061 fail:
1062     efx_siena_fini_struct(efx);
1063     return rc;
1064 }
1065 
1066 void efx_siena_fini_struct(struct efx_nic *efx)
1067 {
1068 #ifdef CONFIG_RFS_ACCEL
1069     kfree(efx->rps_hash_table);
1070 #endif
1071 
1072     efx_siena_fini_channels(efx);
1073 
1074     kfree(efx->vpd_sn);
1075 
1076     if (efx->workqueue) {
1077         destroy_workqueue(efx->workqueue);
1078         efx->workqueue = NULL;
1079     }
1080 }
1081 
1082 /* This configures the PCI device to enable I/O and DMA. */
1083 int efx_siena_init_io(struct efx_nic *efx, int bar, dma_addr_t dma_mask,
1084               unsigned int mem_map_size)
1085 {
1086     struct pci_dev *pci_dev = efx->pci_dev;
1087     int rc;
1088 
1089     efx->mem_bar = UINT_MAX;
1090 
1091     netif_dbg(efx, probe, efx->net_dev, "initialising I/O bar=%d\n", bar);
1092 
1093     rc = pci_enable_device(pci_dev);
1094     if (rc) {
1095         netif_err(efx, probe, efx->net_dev,
1096               "failed to enable PCI device\n");
1097         goto fail1;
1098     }
1099 
1100     pci_set_master(pci_dev);
1101 
1102     rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask);
1103     if (rc) {
1104         netif_err(efx, probe, efx->net_dev,
1105               "could not find a suitable DMA mask\n");
1106         goto fail2;
1107     }
1108     netif_dbg(efx, probe, efx->net_dev,
1109           "using DMA mask %llx\n", (unsigned long long)dma_mask);
1110 
1111     efx->membase_phys = pci_resource_start(efx->pci_dev, bar);
1112     if (!efx->membase_phys) {
1113         netif_err(efx, probe, efx->net_dev,
1114               "ERROR: No BAR%d mapping from the BIOS. "
1115               "Try pci=realloc on the kernel command line\n", bar);
1116         rc = -ENODEV;
1117         goto fail3;
1118     }
1119 
1120     rc = pci_request_region(pci_dev, bar, "sfc");
1121     if (rc) {
1122         netif_err(efx, probe, efx->net_dev,
1123               "request for memory BAR[%d] failed\n", bar);
1124         rc = -EIO;
1125         goto fail3;
1126     }
1127     efx->mem_bar = bar;
1128     efx->membase = ioremap(efx->membase_phys, mem_map_size);
1129     if (!efx->membase) {
1130         netif_err(efx, probe, efx->net_dev,
1131               "could not map memory BAR[%d] at %llx+%x\n", bar,
1132               (unsigned long long)efx->membase_phys, mem_map_size);
1133         rc = -ENOMEM;
1134         goto fail4;
1135     }
1136     netif_dbg(efx, probe, efx->net_dev,
1137           "memory BAR[%d] at %llx+%x (virtual %p)\n", bar,
1138           (unsigned long long)efx->membase_phys, mem_map_size,
1139           efx->membase);
1140 
1141     return 0;
1142 
1143 fail4:
1144     pci_release_region(efx->pci_dev, bar);
1145 fail3:
1146     efx->membase_phys = 0;
1147 fail2:
1148     pci_disable_device(efx->pci_dev);
1149 fail1:
1150     return rc;
1151 }
1152 
1153 void efx_siena_fini_io(struct efx_nic *efx)
1154 {
1155     netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
1156 
1157     if (efx->membase) {
1158         iounmap(efx->membase);
1159         efx->membase = NULL;
1160     }
1161 
1162     if (efx->membase_phys) {
1163         pci_release_region(efx->pci_dev, efx->mem_bar);
1164         efx->membase_phys = 0;
1165         efx->mem_bar = UINT_MAX;
1166     }
1167 
1168     /* Don't disable bus-mastering if VFs are assigned */
1169     if (!pci_vfs_assigned(efx->pci_dev))
1170         pci_disable_device(efx->pci_dev);
1171 }
1172 
1173 #ifdef CONFIG_SFC_SIENA_MCDI_LOGGING
1174 static ssize_t mcdi_logging_show(struct device *dev,
1175                  struct device_attribute *attr,
1176                  char *buf)
1177 {
1178     struct efx_nic *efx = dev_get_drvdata(dev);
1179     struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
1180 
1181     return scnprintf(buf, PAGE_SIZE, "%d\n", mcdi->logging_enabled);
1182 }
1183 
1184 static ssize_t mcdi_logging_store(struct device *dev,
1185                   struct device_attribute *attr,
1186                   const char *buf, size_t count)
1187 {
1188     struct efx_nic *efx = dev_get_drvdata(dev);
1189     struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
1190     bool enable = count > 0 && *buf != '0';
1191 
1192     mcdi->logging_enabled = enable;
1193     return count;
1194 }
1195 
1196 static DEVICE_ATTR_RW(mcdi_logging);
1197 
1198 void efx_siena_init_mcdi_logging(struct efx_nic *efx)
1199 {
1200     int rc = device_create_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging);
1201 
1202     if (rc) {
1203         netif_warn(efx, drv, efx->net_dev,
1204                "failed to init net dev attributes\n");
1205     }
1206 }
1207 
1208 void efx_siena_fini_mcdi_logging(struct efx_nic *efx)
1209 {
1210     device_remove_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging);
1211 }
1212 #endif
1213 
1214 /* A PCI error affecting this device was detected.
1215  * At this point MMIO and DMA may be disabled.
1216  * Stop the software path and request a slot reset.
1217  */
1218 static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
1219                           pci_channel_state_t state)
1220 {
1221     pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
1222     struct efx_nic *efx = pci_get_drvdata(pdev);
1223 
1224     if (state == pci_channel_io_perm_failure)
1225         return PCI_ERS_RESULT_DISCONNECT;
1226 
1227     rtnl_lock();
1228 
1229     if (efx->state != STATE_DISABLED) {
1230         efx->state = STATE_RECOVERY;
1231         efx->reset_pending = 0;
1232 
1233         efx_device_detach_sync(efx);
1234 
1235         efx_siena_stop_all(efx);
1236         efx_siena_disable_interrupts(efx);
1237 
1238         status = PCI_ERS_RESULT_NEED_RESET;
1239     } else {
1240         /* If the interface is disabled we don't want to do anything
1241          * with it.
1242          */
1243         status = PCI_ERS_RESULT_RECOVERED;
1244     }
1245 
1246     rtnl_unlock();
1247 
1248     pci_disable_device(pdev);
1249 
1250     return status;
1251 }
1252 
1253 /* Fake a successful reset, which will be performed later in efx_io_resume. */
1254 static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
1255 {
1256     struct efx_nic *efx = pci_get_drvdata(pdev);
1257     pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
1258 
1259     if (pci_enable_device(pdev)) {
1260         netif_err(efx, hw, efx->net_dev,
1261               "Cannot re-enable PCI device after reset.\n");
1262         status =  PCI_ERS_RESULT_DISCONNECT;
1263     }
1264 
1265     return status;
1266 }
1267 
1268 /* Perform the actual reset and resume I/O operations. */
1269 static void efx_io_resume(struct pci_dev *pdev)
1270 {
1271     struct efx_nic *efx = pci_get_drvdata(pdev);
1272     int rc;
1273 
1274     rtnl_lock();
1275 
1276     if (efx->state == STATE_DISABLED)
1277         goto out;
1278 
1279     rc = efx_siena_reset(efx, RESET_TYPE_ALL);
1280     if (rc) {
1281         netif_err(efx, hw, efx->net_dev,
1282               "efx_siena_reset failed after PCI error (%d)\n", rc);
1283     } else {
1284         efx->state = STATE_READY;
1285         netif_dbg(efx, hw, efx->net_dev,
1286               "Done resetting and resuming IO after PCI error.\n");
1287     }
1288 
1289 out:
1290     rtnl_unlock();
1291 }
1292 
1293 /* For simplicity and reliability, we always require a slot reset and try to
1294  * reset the hardware when a pci error affecting the device is detected.
1295  * We leave both the link_reset and mmio_enabled callback unimplemented:
1296  * with our request for slot reset the mmio_enabled callback will never be
1297  * called, and the link_reset callback is not used by AER or EEH mechanisms.
1298  */
1299 const struct pci_error_handlers efx_siena_err_handlers = {
1300     .error_detected = efx_io_error_detected,
1301     .slot_reset = efx_io_slot_reset,
1302     .resume     = efx_io_resume,
1303 };
1304 
1305 /* Determine whether the NIC will be able to handle TX offloads for a given
1306  * encapsulated packet.
1307  */
1308 static bool efx_can_encap_offloads(struct efx_nic *efx, struct sk_buff *skb)
1309 {
1310     struct gre_base_hdr *greh;
1311     __be16 dst_port;
1312     u8 ipproto;
1313 
1314     /* Does the NIC support encap offloads?
1315      * If not, we should never get here, because we shouldn't have
1316      * advertised encap offload feature flags in the first place.
1317      */
1318     if (WARN_ON_ONCE(!efx->type->udp_tnl_has_port))
1319         return false;
1320 
1321     /* Determine encapsulation protocol in use */
1322     switch (skb->protocol) {
1323     case htons(ETH_P_IP):
1324         ipproto = ip_hdr(skb)->protocol;
1325         break;
1326     case htons(ETH_P_IPV6):
1327         /* If there are extension headers, this will cause us to
1328          * think we can't offload something that we maybe could have.
1329          */
1330         ipproto = ipv6_hdr(skb)->nexthdr;
1331         break;
1332     default:
1333         /* Not IP, so can't offload it */
1334         return false;
1335     }
1336     switch (ipproto) {
1337     case IPPROTO_GRE:
1338         /* We support NVGRE but not IP over GRE or random gretaps.
1339          * Specifically, the NIC will accept GRE as encapsulated if
1340          * the inner protocol is Ethernet, but only handle it
1341          * correctly if the GRE header is 8 bytes long.  Moreover,
1342          * it will not update the Checksum or Sequence Number fields
1343          * if they are present.  (The Routing Present flag,
1344          * GRE_ROUTING, cannot be set else the header would be more
1345          * than 8 bytes long; so we don't have to worry about it.)
1346          */
1347         if (skb->inner_protocol_type != ENCAP_TYPE_ETHER)
1348             return false;
1349         if (ntohs(skb->inner_protocol) != ETH_P_TEB)
1350             return false;
1351         if (skb_inner_mac_header(skb) - skb_transport_header(skb) != 8)
1352             return false;
1353         greh = (struct gre_base_hdr *)skb_transport_header(skb);
1354         return !(greh->flags & (GRE_CSUM | GRE_SEQ));
1355     case IPPROTO_UDP:
1356         /* If the port is registered for a UDP tunnel, we assume the
1357          * packet is for that tunnel, and the NIC will handle it as
1358          * such.  If not, the NIC won't know what to do with it.
1359          */
1360         dst_port = udp_hdr(skb)->dest;
1361         return efx->type->udp_tnl_has_port(efx, dst_port);
1362     default:
1363         return false;
1364     }
1365 }
1366 
1367 netdev_features_t efx_siena_features_check(struct sk_buff *skb,
1368                        struct net_device *dev,
1369                        netdev_features_t features)
1370 {
1371     struct efx_nic *efx = netdev_priv(dev);
1372 
1373     if (skb->encapsulation) {
1374         if (features & NETIF_F_GSO_MASK)
1375             /* Hardware can only do TSO with at most 208 bytes
1376              * of headers.
1377              */
1378             if (skb_inner_transport_offset(skb) >
1379                 EFX_TSO2_MAX_HDRLEN)
1380                 features &= ~(NETIF_F_GSO_MASK);
1381         if (features & (NETIF_F_GSO_MASK | NETIF_F_CSUM_MASK))
1382             if (!efx_can_encap_offloads(efx, skb))
1383                 features &= ~(NETIF_F_GSO_MASK |
1384                           NETIF_F_CSUM_MASK);
1385     }
1386     return features;
1387 }
1388 
1389 int efx_siena_get_phys_port_id(struct net_device *net_dev,
1390                    struct netdev_phys_item_id *ppid)
1391 {
1392     struct efx_nic *efx = netdev_priv(net_dev);
1393 
1394     if (efx->type->get_phys_port_id)
1395         return efx->type->get_phys_port_id(efx, ppid);
1396     else
1397         return -EOPNOTSUPP;
1398 }
1399 
1400 int efx_siena_get_phys_port_name(struct net_device *net_dev,
1401                  char *name, size_t len)
1402 {
1403     struct efx_nic *efx = netdev_priv(net_dev);
1404 
1405     if (snprintf(name, len, "p%u", efx->port_num) >= len)
1406         return -EINVAL;
1407     return 0;
1408 }
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