ethernet/sfc/nic_common.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /****************************************************************************
0003  * Driver for Solarflare network controllers and boards
0004  * Copyright 2005-2006 Fen Systems Ltd.
0005  * Copyright 2006-2013 Solarflare Communications Inc.
0006  * Copyright 2019-2020 Xilinx Inc.
0007  */
0008
0009 #ifndef EFX_NIC_COMMON_H
0010 #define EFX_NIC_COMMON_H
0011
0012 #include "net_driver.h"
0013 #include "efx_common.h"
0014 #include "mcdi.h"
0015 #include "ptp.h"
0016
0017 enum {
0018     /* Revisions 0-2 were Falcon A0, A1 and B0 respectively.
0019      * They are not supported by this driver but these revision numbers
0020      * form part of the ethtool API for register dumping.
0021      */
0022     EFX_REV_SIENA_A0 = 3,
0023     EFX_REV_HUNT_A0 = 4,
0024     EFX_REV_EF100 = 5,
0025 };
0026
0027 static inline int efx_nic_rev(struct efx_nic *efx)
0028 {
0029     return efx->type->revision;
0030 }
0031
0032 /* Read the current event from the event queue */
0033 static inline efx_qword_t *efx_event(struct efx_channel *channel,
0034                      unsigned int index)
0035 {
0036     return ((efx_qword_t *) (channel->eventq.buf.addr)) +
0037         (index & channel->eventq_mask);
0038 }
0039
0040 /* See if an event is present
0041  *
0042  * We check both the high and low dword of the event for all ones.  We
0043  * wrote all ones when we cleared the event, and no valid event can
0044  * have all ones in either its high or low dwords.  This approach is
0045  * robust against reordering.
0046  *
0047  * Note that using a single 64-bit comparison is incorrect; even
0048  * though the CPU read will be atomic, the DMA write may not be.
0049  */
0050 static inline int efx_event_present(efx_qword_t *event)
0051 {
0052     return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
0053           EFX_DWORD_IS_ALL_ONES(event->dword[1]));
0054 }
0055
0056 /* Returns a pointer to the specified transmit descriptor in the TX
0057  * descriptor queue belonging to the specified channel.
0058  */
0059 static inline efx_qword_t *
0060 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
0061 {
0062     return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index;
0063 }
0064
0065 /* Report whether this TX queue would be empty for the given write_count.
0066  * May return false negative.
0067  */
0068 static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue, unsigned int write_count)
0069 {
0070     unsigned int empty_read_count = READ_ONCE(tx_queue->empty_read_count);
0071
0072     if (empty_read_count == 0)
0073         return false;
0074
0075     return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0;
0076 }
0077
0078 int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
0079             bool *data_mapped);
0080
0081 /* Decide whether to push a TX descriptor to the NIC vs merely writing
0082  * the doorbell.  This can reduce latency when we are adding a single
0083  * descriptor to an empty queue, but is otherwise pointless.  Further,
0084  * Falcon and Siena have hardware bugs (SF bug 33851) that may be
0085  * triggered if we don't check this.
0086  * We use the write_count used for the last doorbell push, to get the
0087  * NIC's view of the tx queue.
0088  */
0089 static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue,
0090                         unsigned int write_count)
0091 {
0092     bool was_empty = efx_nic_tx_is_empty(tx_queue, write_count);
0093
0094     tx_queue->empty_read_count = 0;
0095     return was_empty && tx_queue->write_count - write_count == 1;
0096 }
0097
0098 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
0099 static inline efx_qword_t *
0100 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
0101 {
0102     return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index;
0103 }
0104
0105 /* Alignment of PCIe DMA boundaries (4KB) */
0106 #define EFX_PAGE_SIZE   4096
0107 /* Size and alignment of buffer table entries (same) */
0108 #define EFX_BUF_SIZE    EFX_PAGE_SIZE
0109
0110 /* NIC-generic software stats */
0111 enum {
0112     GENERIC_STAT_rx_noskb_drops,
0113     GENERIC_STAT_rx_nodesc_trunc,
0114     GENERIC_STAT_COUNT
0115 };
0116
0117 #define EFX_GENERIC_SW_STAT(ext_name)               \
0118     [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
0119
0120 /* TX data path */
0121 static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
0122 {
0123     return tx_queue->efx->type->tx_probe(tx_queue);
0124 }
0125 static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
0126 {
0127     tx_queue->efx->type->tx_init(tx_queue);
0128 }
0129 static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
0130 {
0131     if (tx_queue->efx->type->tx_remove)
0132         tx_queue->efx->type->tx_remove(tx_queue);
0133 }
0134 static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
0135 {
0136     tx_queue->efx->type->tx_write(tx_queue);
0137 }
0138
0139 /* RX data path */
0140 static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
0141 {
0142     return rx_queue->efx->type->rx_probe(rx_queue);
0143 }
0144 static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
0145 {
0146     rx_queue->efx->type->rx_init(rx_queue);
0147 }
0148 static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
0149 {
0150     rx_queue->efx->type->rx_remove(rx_queue);
0151 }
0152 static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
0153 {
0154     rx_queue->efx->type->rx_write(rx_queue);
0155 }
0156 static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
0157 {
0158     rx_queue->efx->type->rx_defer_refill(rx_queue);
0159 }
0160
0161 /* Event data path */
0162 static inline int efx_nic_probe_eventq(struct efx_channel *channel)
0163 {
0164     return channel->efx->type->ev_probe(channel);
0165 }
0166 static inline int efx_nic_init_eventq(struct efx_channel *channel)
0167 {
0168     return channel->efx->type->ev_init(channel);
0169 }
0170 static inline void efx_nic_fini_eventq(struct efx_channel *channel)
0171 {
0172     channel->efx->type->ev_fini(channel);
0173 }
0174 static inline void efx_nic_remove_eventq(struct efx_channel *channel)
0175 {
0176     channel->efx->type->ev_remove(channel);
0177 }
0178 static inline int
0179 efx_nic_process_eventq(struct efx_channel *channel, int quota)
0180 {
0181     return channel->efx->type->ev_process(channel, quota);
0182 }
0183 static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
0184 {
0185     channel->efx->type->ev_read_ack(channel);
0186 }
0187
0188 void efx_nic_event_test_start(struct efx_channel *channel);
0189
0190 bool efx_nic_event_present(struct efx_channel *channel);
0191
0192 static inline void efx_sensor_event(struct efx_nic *efx, efx_qword_t *ev)
0193 {
0194     if (efx->type->sensor_event)
0195         efx->type->sensor_event(efx, ev);
0196 }
0197
0198 static inline unsigned int efx_rx_recycle_ring_size(const struct efx_nic *efx)
0199 {
0200     return efx->type->rx_recycle_ring_size(efx);
0201 }
0202
0203 /* Some statistics are computed as A - B where A and B each increase
0204  * linearly with some hardware counter(s) and the counters are read
0205  * asynchronously.  If the counters contributing to B are always read
0206  * after those contributing to A, the computed value may be lower than
0207  * the true value by some variable amount, and may decrease between
0208  * subsequent computations.
0209  *
0210  * We should never allow statistics to decrease or to exceed the true
0211  * value.  Since the computed value will never be greater than the
0212  * true value, we can achieve this by only storing the computed value
0213  * when it increases.
0214  */
0215 static inline void efx_update_diff_stat(u64 *stat, u64 diff)
0216 {
0217     if ((s64)(diff - *stat) > 0)
0218         *stat = diff;
0219 }
0220
0221 /* Interrupts */
0222 int efx_nic_init_interrupt(struct efx_nic *efx);
0223 int efx_nic_irq_test_start(struct efx_nic *efx);
0224 void efx_nic_fini_interrupt(struct efx_nic *efx);
0225
0226 static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel)
0227 {
0228     return READ_ONCE(channel->event_test_cpu);
0229 }
0230 static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx)
0231 {
0232     return READ_ONCE(efx->last_irq_cpu);
0233 }
0234
0235 /* Global Resources */
0236 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
0237              unsigned int len, gfp_t gfp_flags);
0238 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer);
0239
0240 size_t efx_nic_get_regs_len(struct efx_nic *efx);
0241 void efx_nic_get_regs(struct efx_nic *efx, void *buf);
0242
0243 #define EFX_MC_STATS_GENERATION_INVALID ((__force __le64)(-1))
0244
0245 size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
0246                   const unsigned long *mask, u8 *names);
0247 int efx_nic_copy_stats(struct efx_nic *efx, __le64 *dest);
0248 void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
0249               const unsigned long *mask, u64 *stats,
0250               const void *dma_buf, bool accumulate);
0251 void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat);
0252 static inline size_t efx_nic_update_stats_atomic(struct efx_nic *efx, u64 *full_stats,
0253                          struct rtnl_link_stats64 *core_stats)
0254 {
0255     if (efx->type->update_stats_atomic)
0256         return efx->type->update_stats_atomic(efx, full_stats, core_stats);
0257     return efx->type->update_stats(efx, full_stats, core_stats);
0258 }
0259
0260 #define EFX_MAX_FLUSH_TIME 5000
0261
0262 #endif /* EFX_NIC_COMMON_H */