ethernet/sfc/nic.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /****************************************************************************
0003  * Driver for Solarflare network controllers and boards
0004  * Copyright 2005-2006 Fen Systems Ltd.
0005  * Copyright 2006-2013 Solarflare Communications Inc.
0006  */
0007
0008 #ifndef EFX_NIC_H
0009 #define EFX_NIC_H
0010
0011 #include "nic_common.h"
0012 #include "efx.h"
0013
0014 u32 efx_farch_fpga_ver(struct efx_nic *efx);
0015
0016 enum {
0017     PHY_TYPE_NONE = 0,
0018     PHY_TYPE_TXC43128 = 1,
0019     PHY_TYPE_88E1111 = 2,
0020     PHY_TYPE_SFX7101 = 3,
0021     PHY_TYPE_QT2022C2 = 4,
0022     PHY_TYPE_PM8358 = 6,
0023     PHY_TYPE_SFT9001A = 8,
0024     PHY_TYPE_QT2025C = 9,
0025     PHY_TYPE_SFT9001B = 10,
0026 };
0027
0028 enum {
0029     SIENA_STAT_tx_bytes = GENERIC_STAT_COUNT,
0030     SIENA_STAT_tx_good_bytes,
0031     SIENA_STAT_tx_bad_bytes,
0032     SIENA_STAT_tx_packets,
0033     SIENA_STAT_tx_bad,
0034     SIENA_STAT_tx_pause,
0035     SIENA_STAT_tx_control,
0036     SIENA_STAT_tx_unicast,
0037     SIENA_STAT_tx_multicast,
0038     SIENA_STAT_tx_broadcast,
0039     SIENA_STAT_tx_lt64,
0040     SIENA_STAT_tx_64,
0041     SIENA_STAT_tx_65_to_127,
0042     SIENA_STAT_tx_128_to_255,
0043     SIENA_STAT_tx_256_to_511,
0044     SIENA_STAT_tx_512_to_1023,
0045     SIENA_STAT_tx_1024_to_15xx,
0046     SIENA_STAT_tx_15xx_to_jumbo,
0047     SIENA_STAT_tx_gtjumbo,
0048     SIENA_STAT_tx_collision,
0049     SIENA_STAT_tx_single_collision,
0050     SIENA_STAT_tx_multiple_collision,
0051     SIENA_STAT_tx_excessive_collision,
0052     SIENA_STAT_tx_deferred,
0053     SIENA_STAT_tx_late_collision,
0054     SIENA_STAT_tx_excessive_deferred,
0055     SIENA_STAT_tx_non_tcpudp,
0056     SIENA_STAT_tx_mac_src_error,
0057     SIENA_STAT_tx_ip_src_error,
0058     SIENA_STAT_rx_bytes,
0059     SIENA_STAT_rx_good_bytes,
0060     SIENA_STAT_rx_bad_bytes,
0061     SIENA_STAT_rx_packets,
0062     SIENA_STAT_rx_good,
0063     SIENA_STAT_rx_bad,
0064     SIENA_STAT_rx_pause,
0065     SIENA_STAT_rx_control,
0066     SIENA_STAT_rx_unicast,
0067     SIENA_STAT_rx_multicast,
0068     SIENA_STAT_rx_broadcast,
0069     SIENA_STAT_rx_lt64,
0070     SIENA_STAT_rx_64,
0071     SIENA_STAT_rx_65_to_127,
0072     SIENA_STAT_rx_128_to_255,
0073     SIENA_STAT_rx_256_to_511,
0074     SIENA_STAT_rx_512_to_1023,
0075     SIENA_STAT_rx_1024_to_15xx,
0076     SIENA_STAT_rx_15xx_to_jumbo,
0077     SIENA_STAT_rx_gtjumbo,
0078     SIENA_STAT_rx_bad_gtjumbo,
0079     SIENA_STAT_rx_overflow,
0080     SIENA_STAT_rx_false_carrier,
0081     SIENA_STAT_rx_symbol_error,
0082     SIENA_STAT_rx_align_error,
0083     SIENA_STAT_rx_length_error,
0084     SIENA_STAT_rx_internal_error,
0085     SIENA_STAT_rx_nodesc_drop_cnt,
0086     SIENA_STAT_COUNT
0087 };
0088
0089 /**
0090  * struct siena_nic_data - Siena NIC state
0091  * @efx: Pointer back to main interface structure
0092  * @wol_filter_id: Wake-on-LAN packet filter id
0093  * @stats: Hardware statistics
0094  * @vf: Array of &struct siena_vf objects
0095  * @vf_buftbl_base: The zeroth buffer table index used to back VF queues.
0096  * @vfdi_status: Common VFDI status page to be dmad to VF address space.
0097  * @local_addr_list: List of local addresses. Protected by %local_lock.
0098  * @local_page_list: List of DMA addressable pages used to broadcast
0099  *  %local_addr_list. Protected by %local_lock.
0100  * @local_lock: Mutex protecting %local_addr_list and %local_page_list.
0101  * @peer_work: Work item to broadcast peer addresses to VMs.
0102  */
0103 struct siena_nic_data {
0104     struct efx_nic *efx;
0105     int wol_filter_id;
0106     u64 stats[SIENA_STAT_COUNT];
0107 #ifdef CONFIG_SFC_SRIOV
0108     struct siena_vf *vf;
0109     struct efx_channel *vfdi_channel;
0110     unsigned vf_buftbl_base;
0111     struct efx_buffer vfdi_status;
0112     struct list_head local_addr_list;
0113     struct list_head local_page_list;
0114     struct mutex local_lock;
0115     struct work_struct peer_work;
0116 #endif
0117 };
0118
0119 enum {
0120     EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT,
0121     EF10_STAT_port_tx_packets,
0122     EF10_STAT_port_tx_pause,
0123     EF10_STAT_port_tx_control,
0124     EF10_STAT_port_tx_unicast,
0125     EF10_STAT_port_tx_multicast,
0126     EF10_STAT_port_tx_broadcast,
0127     EF10_STAT_port_tx_lt64,
0128     EF10_STAT_port_tx_64,
0129     EF10_STAT_port_tx_65_to_127,
0130     EF10_STAT_port_tx_128_to_255,
0131     EF10_STAT_port_tx_256_to_511,
0132     EF10_STAT_port_tx_512_to_1023,
0133     EF10_STAT_port_tx_1024_to_15xx,
0134     EF10_STAT_port_tx_15xx_to_jumbo,
0135     EF10_STAT_port_rx_bytes,
0136     EF10_STAT_port_rx_bytes_minus_good_bytes,
0137     EF10_STAT_port_rx_good_bytes,
0138     EF10_STAT_port_rx_bad_bytes,
0139     EF10_STAT_port_rx_packets,
0140     EF10_STAT_port_rx_good,
0141     EF10_STAT_port_rx_bad,
0142     EF10_STAT_port_rx_pause,
0143     EF10_STAT_port_rx_control,
0144     EF10_STAT_port_rx_unicast,
0145     EF10_STAT_port_rx_multicast,
0146     EF10_STAT_port_rx_broadcast,
0147     EF10_STAT_port_rx_lt64,
0148     EF10_STAT_port_rx_64,
0149     EF10_STAT_port_rx_65_to_127,
0150     EF10_STAT_port_rx_128_to_255,
0151     EF10_STAT_port_rx_256_to_511,
0152     EF10_STAT_port_rx_512_to_1023,
0153     EF10_STAT_port_rx_1024_to_15xx,
0154     EF10_STAT_port_rx_15xx_to_jumbo,
0155     EF10_STAT_port_rx_gtjumbo,
0156     EF10_STAT_port_rx_bad_gtjumbo,
0157     EF10_STAT_port_rx_overflow,
0158     EF10_STAT_port_rx_align_error,
0159     EF10_STAT_port_rx_length_error,
0160     EF10_STAT_port_rx_nodesc_drops,
0161     EF10_STAT_port_rx_pm_trunc_bb_overflow,
0162     EF10_STAT_port_rx_pm_discard_bb_overflow,
0163     EF10_STAT_port_rx_pm_trunc_vfifo_full,
0164     EF10_STAT_port_rx_pm_discard_vfifo_full,
0165     EF10_STAT_port_rx_pm_trunc_qbb,
0166     EF10_STAT_port_rx_pm_discard_qbb,
0167     EF10_STAT_port_rx_pm_discard_mapping,
0168     EF10_STAT_port_rx_dp_q_disabled_packets,
0169     EF10_STAT_port_rx_dp_di_dropped_packets,
0170     EF10_STAT_port_rx_dp_streaming_packets,
0171     EF10_STAT_port_rx_dp_hlb_fetch,
0172     EF10_STAT_port_rx_dp_hlb_wait,
0173     EF10_STAT_rx_unicast,
0174     EF10_STAT_rx_unicast_bytes,
0175     EF10_STAT_rx_multicast,
0176     EF10_STAT_rx_multicast_bytes,
0177     EF10_STAT_rx_broadcast,
0178     EF10_STAT_rx_broadcast_bytes,
0179     EF10_STAT_rx_bad,
0180     EF10_STAT_rx_bad_bytes,
0181     EF10_STAT_rx_overflow,
0182     EF10_STAT_tx_unicast,
0183     EF10_STAT_tx_unicast_bytes,
0184     EF10_STAT_tx_multicast,
0185     EF10_STAT_tx_multicast_bytes,
0186     EF10_STAT_tx_broadcast,
0187     EF10_STAT_tx_broadcast_bytes,
0188     EF10_STAT_tx_bad,
0189     EF10_STAT_tx_bad_bytes,
0190     EF10_STAT_tx_overflow,
0191     EF10_STAT_V1_COUNT,
0192     EF10_STAT_fec_uncorrected_errors = EF10_STAT_V1_COUNT,
0193     EF10_STAT_fec_corrected_errors,
0194     EF10_STAT_fec_corrected_symbols_lane0,
0195     EF10_STAT_fec_corrected_symbols_lane1,
0196     EF10_STAT_fec_corrected_symbols_lane2,
0197     EF10_STAT_fec_corrected_symbols_lane3,
0198     EF10_STAT_ctpio_vi_busy_fallback,
0199     EF10_STAT_ctpio_long_write_success,
0200     EF10_STAT_ctpio_missing_dbell_fail,
0201     EF10_STAT_ctpio_overflow_fail,
0202     EF10_STAT_ctpio_underflow_fail,
0203     EF10_STAT_ctpio_timeout_fail,
0204     EF10_STAT_ctpio_noncontig_wr_fail,
0205     EF10_STAT_ctpio_frm_clobber_fail,
0206     EF10_STAT_ctpio_invalid_wr_fail,
0207     EF10_STAT_ctpio_vi_clobber_fallback,
0208     EF10_STAT_ctpio_unqualified_fallback,
0209     EF10_STAT_ctpio_runt_fallback,
0210     EF10_STAT_ctpio_success,
0211     EF10_STAT_ctpio_fallback,
0212     EF10_STAT_ctpio_poison,
0213     EF10_STAT_ctpio_erase,
0214     EF10_STAT_COUNT
0215 };
0216
0217 /* Maximum number of TX PIO buffers we may allocate to a function.
0218  * This matches the total number of buffers on each SFC9100-family
0219  * controller.
0220  */
0221 #define EF10_TX_PIOBUF_COUNT 16
0222
0223 /**
0224  * struct efx_ef10_nic_data - EF10 architecture NIC state
0225  * @mcdi_buf: DMA buffer for MCDI
0226  * @warm_boot_count: Last seen MC warm boot count
0227  * @vi_base: Absolute index of first VI in this function
0228  * @n_allocated_vis: Number of VIs allocated to this function
0229  * @n_piobufs: Number of PIO buffers allocated to this function
0230  * @wc_membase: Base address of write-combining mapping of the memory BAR
0231  * @pio_write_base: Base address for writing PIO buffers
0232  * @pio_write_vi_base: Relative VI number for @pio_write_base
0233  * @piobuf_handle: Handle of each PIO buffer allocated
0234  * @piobuf_size: size of a single PIO buffer
0235  * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
0236  *  reboot
0237  * @mc_stats: Scratch buffer for converting statistics to the kernel's format
0238  * @stats: Hardware statistics
0239  * @workaround_35388: Flag: firmware supports workaround for bug 35388
0240  * @workaround_26807: Flag: firmware supports workaround for bug 26807
0241  * @workaround_61265: Flag: firmware supports workaround for bug 61265
0242  * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
0243  *  after MC reboot
0244  * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
0245  *  %MC_CMD_GET_CAPABILITIES response)
0246  * @datapath_caps2: Further Capabilities of datapath firmware (FLAGS2 field of
0247  * %MC_CMD_GET_CAPABILITIES response)
0248  * @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU
0249  * @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU
0250  * @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot
0251  * @pf_index: The number for this PF, or the parent PF if this is a VF
0252 #ifdef CONFIG_SFC_SRIOV
0253  * @vf: Pointer to VF data structure
0254 #endif
0255  * @vport_mac: The MAC address on the vport, only for PFs; VFs will be zero
0256  * @vlan_list: List of VLANs added over the interface. Serialised by vlan_lock.
0257  * @vlan_lock: Lock to serialize access to vlan_list.
0258  * @udp_tunnels: UDP tunnel port numbers and types.
0259  * @udp_tunnels_dirty: flag indicating a reboot occurred while pushing
0260  *  @udp_tunnels to hardware and thus the push must be re-done.
0261  * @udp_tunnels_lock: Serialises writes to @udp_tunnels and @udp_tunnels_dirty.
0262  */
0263 struct efx_ef10_nic_data {
0264     struct efx_buffer mcdi_buf;
0265     u16 warm_boot_count;
0266     unsigned int vi_base;
0267     unsigned int n_allocated_vis;
0268     unsigned int n_piobufs;
0269     void __iomem *wc_membase, *pio_write_base;
0270     unsigned int pio_write_vi_base;
0271     unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
0272     u16 piobuf_size;
0273     bool must_restore_piobufs;
0274     __le64 *mc_stats;
0275     u64 stats[EF10_STAT_COUNT];
0276     bool workaround_35388;
0277     bool workaround_26807;
0278     bool workaround_61265;
0279     bool must_check_datapath_caps;
0280     u32 datapath_caps;
0281     u32 datapath_caps2;
0282     unsigned int rx_dpcpu_fw_id;
0283     unsigned int tx_dpcpu_fw_id;
0284     bool must_probe_vswitching;
0285     unsigned int pf_index;
0286     u8 port_id[ETH_ALEN];
0287 #ifdef CONFIG_SFC_SRIOV
0288     unsigned int vf_index;
0289     struct ef10_vf *vf;
0290 #endif
0291     u8 vport_mac[ETH_ALEN];
0292     struct list_head vlan_list;
0293     struct mutex vlan_lock;
0294     struct efx_udp_tunnel udp_tunnels[16];
0295     bool udp_tunnels_dirty;
0296     struct mutex udp_tunnels_lock;
0297     u64 licensed_features;
0298 };
0299
0300 /* TSOv2 */
0301 int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
0302              bool *data_mapped);
0303
0304 extern const struct efx_nic_type efx_hunt_a0_nic_type;
0305 extern const struct efx_nic_type efx_hunt_a0_vf_nic_type;
0306
0307 int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
0308
0309 /* Falcon/Siena queue operations */
0310 int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
0311 void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
0312 void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
0313 void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
0314 void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
0315 unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue,
0316                     dma_addr_t dma_addr, unsigned int len);
0317 int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
0318 void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
0319 void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
0320 void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
0321 void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
0322 void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
0323 int efx_farch_ev_probe(struct efx_channel *channel);
0324 int efx_farch_ev_init(struct efx_channel *channel);
0325 void efx_farch_ev_fini(struct efx_channel *channel);
0326 void efx_farch_ev_remove(struct efx_channel *channel);
0327 int efx_farch_ev_process(struct efx_channel *channel, int quota);
0328 void efx_farch_ev_read_ack(struct efx_channel *channel);
0329 void efx_farch_ev_test_generate(struct efx_channel *channel);
0330
0331 /* Falcon/Siena filter operations */
0332 int efx_farch_filter_table_probe(struct efx_nic *efx);
0333 void efx_farch_filter_table_restore(struct efx_nic *efx);
0334 void efx_farch_filter_table_remove(struct efx_nic *efx);
0335 void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
0336 s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec,
0337                 bool replace);
0338 int efx_farch_filter_remove_safe(struct efx_nic *efx,
0339                  enum efx_filter_priority priority,
0340                  u32 filter_id);
0341 int efx_farch_filter_get_safe(struct efx_nic *efx,
0342                   enum efx_filter_priority priority, u32 filter_id,
0343                   struct efx_filter_spec *);
0344 int efx_farch_filter_clear_rx(struct efx_nic *efx,
0345                   enum efx_filter_priority priority);
0346 u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
0347                    enum efx_filter_priority priority);
0348 u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
0349 s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
0350                 enum efx_filter_priority priority, u32 *buf,
0351                 u32 size);
0352 #ifdef CONFIG_RFS_ACCEL
0353 bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
0354                      unsigned int index);
0355 #endif
0356 void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
0357
0358 /* Falcon/Siena interrupts */
0359 void efx_farch_irq_enable_master(struct efx_nic *efx);
0360 int efx_farch_irq_test_generate(struct efx_nic *efx);
0361 void efx_farch_irq_disable_master(struct efx_nic *efx);
0362 irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
0363 irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
0364 irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
0365
0366 /* Global Resources */
0367 void siena_prepare_flush(struct efx_nic *efx);
0368 int efx_farch_fini_dmaq(struct efx_nic *efx);
0369 void efx_farch_finish_flr(struct efx_nic *efx);
0370 void siena_finish_flush(struct efx_nic *efx);
0371 void falcon_start_nic_stats(struct efx_nic *efx);
0372 void falcon_stop_nic_stats(struct efx_nic *efx);
0373 int falcon_reset_xaui(struct efx_nic *efx);
0374 void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
0375 void efx_farch_init_common(struct efx_nic *efx);
0376 void efx_farch_rx_push_indir_table(struct efx_nic *efx);
0377 void efx_farch_rx_pull_indir_table(struct efx_nic *efx);
0378
0379 /* Tests */
0380 struct efx_farch_register_test {
0381     unsigned address;
0382     efx_oword_t mask;
0383 };
0384
0385 int efx_farch_test_registers(struct efx_nic *efx,
0386                  const struct efx_farch_register_test *regs,
0387                  size_t n_regs);
0388
0389 void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
0390                   efx_qword_t *event);
0391
0392 #endif /* EFX_NIC_H */