Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /****************************************************************************
0003  * Driver for Solarflare network controllers and boards
0004  * Copyright 2006-2011 Solarflare Communications Inc.
0005  */
0006 
0007 /*
0008  * Driver for Transwitch/Mysticom CX4 retimer
0009  * see www.transwitch.com, part is TXC-43128
0010  */
0011 
0012 #include <linux/delay.h>
0013 #include <linux/slab.h>
0014 #include "efx.h"
0015 #include "mdio_10g.h"
0016 #include "phy.h"
0017 #include "nic.h"
0018 
0019 /* We expect these MMDs to be in the package */
0020 #define TXC_REQUIRED_DEVS (MDIO_DEVS_PCS |  \
0021                MDIO_DEVS_PMAPMD |   \
0022                MDIO_DEVS_PHYXS)
0023 
0024 #define TXC_LOOPBACKS ((1 << LOOPBACK_PCS) |    \
0025                (1 << LOOPBACK_PMAPMD) | \
0026                (1 << LOOPBACK_PHYXS_WS))
0027 
0028 /**************************************************************************
0029  *
0030  * Compile-time config
0031  *
0032  **************************************************************************
0033  */
0034 #define TXCNAME "TXC43128"
0035 /* Total length of time we'll wait for the PHY to come out of reset (ms) */
0036 #define TXC_MAX_RESET_TIME  500
0037 /* Interval between checks (ms) */
0038 #define TXC_RESET_WAIT      10
0039 /* How long to run BIST (us) */
0040 #define TXC_BIST_DURATION   50
0041 
0042 /**************************************************************************
0043  *
0044  * Register definitions
0045  *
0046  **************************************************************************
0047  */
0048 
0049 /* Command register */
0050 #define TXC_GLRGS_GLCMD     0xc004
0051 /* Useful bits in command register */
0052 /* Lane power-down */
0053 #define TXC_GLCMD_L01PD_LBN 5
0054 #define TXC_GLCMD_L23PD_LBN 6
0055 /* Limited SW reset: preserves configuration but
0056  * initiates a logic reset. Self-clearing */
0057 #define TXC_GLCMD_LMTSWRST_LBN  14
0058 
0059 /* Signal Quality Control */
0060 #define TXC_GLRGS_GSGQLCTL  0xc01a
0061 /* Enable bit */
0062 #define TXC_GSGQLCT_SGQLEN_LBN  15
0063 /* Lane selection */
0064 #define TXC_GSGQLCT_LNSL_LBN    13
0065 #define TXC_GSGQLCT_LNSL_WIDTH  2
0066 
0067 /* Analog TX control */
0068 #define TXC_ALRGS_ATXCTL    0xc040
0069 /* Lane power-down */
0070 #define TXC_ATXCTL_TXPD3_LBN    15
0071 #define TXC_ATXCTL_TXPD2_LBN    14
0072 #define TXC_ATXCTL_TXPD1_LBN    13
0073 #define TXC_ATXCTL_TXPD0_LBN    12
0074 
0075 /* Amplitude on lanes 0, 1 */
0076 #define TXC_ALRGS_ATXAMP0   0xc041
0077 /* Amplitude on lanes 2, 3 */
0078 #define TXC_ALRGS_ATXAMP1   0xc042
0079 /* Bit position of value for lane 0 (or 2) */
0080 #define TXC_ATXAMP_LANE02_LBN   3
0081 /* Bit position of value for lane 1 (or 3) */
0082 #define TXC_ATXAMP_LANE13_LBN   11
0083 
0084 #define TXC_ATXAMP_1280_mV  0
0085 #define TXC_ATXAMP_1200_mV  8
0086 #define TXC_ATXAMP_1120_mV  12
0087 #define TXC_ATXAMP_1060_mV  14
0088 #define TXC_ATXAMP_0820_mV  25
0089 #define TXC_ATXAMP_0720_mV  26
0090 #define TXC_ATXAMP_0580_mV  27
0091 #define TXC_ATXAMP_0440_mV  28
0092 
0093 #define TXC_ATXAMP_0820_BOTH                    \
0094     ((TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE02_LBN)      \
0095      | (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE13_LBN))
0096 
0097 #define TXC_ATXAMP_DEFAULT  0x6060 /* From databook */
0098 
0099 /* Preemphasis on lanes 0, 1 */
0100 #define TXC_ALRGS_ATXPRE0   0xc043
0101 /* Preemphasis on lanes 2, 3 */
0102 #define TXC_ALRGS_ATXPRE1   0xc044
0103 
0104 #define TXC_ATXPRE_NONE 0
0105 #define TXC_ATXPRE_DEFAULT  0x1010 /* From databook */
0106 
0107 #define TXC_ALRGS_ARXCTL    0xc045
0108 /* Lane power-down */
0109 #define TXC_ARXCTL_RXPD3_LBN    15
0110 #define TXC_ARXCTL_RXPD2_LBN    14
0111 #define TXC_ARXCTL_RXPD1_LBN    13
0112 #define TXC_ARXCTL_RXPD0_LBN    12
0113 
0114 /* Main control */
0115 #define TXC_MRGS_CTL        0xc340
0116 /* Bits in main control */
0117 #define TXC_MCTL_RESET_LBN  15  /* Self clear */
0118 #define TXC_MCTL_TXLED_LBN  14  /* 1 to show align status */
0119 #define TXC_MCTL_RXLED_LBN  13  /* 1 to show align status */
0120 
0121 /* GPIO output */
0122 #define TXC_GPIO_OUTPUT     0xc346
0123 #define TXC_GPIO_DIR        0xc348
0124 
0125 /* Vendor-specific BIST registers */
0126 #define TXC_BIST_CTL        0xc280
0127 #define TXC_BIST_TXFRMCNT   0xc281
0128 #define TXC_BIST_RX0FRMCNT  0xc282
0129 #define TXC_BIST_RX1FRMCNT  0xc283
0130 #define TXC_BIST_RX2FRMCNT  0xc284
0131 #define TXC_BIST_RX3FRMCNT  0xc285
0132 #define TXC_BIST_RX0ERRCNT  0xc286
0133 #define TXC_BIST_RX1ERRCNT  0xc287
0134 #define TXC_BIST_RX2ERRCNT  0xc288
0135 #define TXC_BIST_RX3ERRCNT  0xc289
0136 
0137 /* BIST type (controls bit patter in test) */
0138 #define TXC_BIST_CTRL_TYPE_LBN  10
0139 #define TXC_BIST_CTRL_TYPE_TSD  0   /* TranSwitch Deterministic */
0140 #define TXC_BIST_CTRL_TYPE_CRP  1   /* CRPAT standard */
0141 #define TXC_BIST_CTRL_TYPE_CJP  2   /* CJPAT standard */
0142 #define TXC_BIST_CTRL_TYPE_TSR  3   /* TranSwitch pseudo-random */
0143 /* Set this to 1 for 10 bit and 0 for 8 bit */
0144 #define TXC_BIST_CTRL_B10EN_LBN 12
0145 /* Enable BIST (write 0 to disable) */
0146 #define TXC_BIST_CTRL_ENAB_LBN  13
0147 /* Stop BIST (self-clears when stop complete) */
0148 #define TXC_BIST_CTRL_STOP_LBN  14
0149 /* Start BIST (cleared by writing 1 to STOP) */
0150 #define TXC_BIST_CTRL_STRT_LBN  15
0151 
0152 /* Mt. Diablo test configuration */
0153 #define TXC_MTDIABLO_CTRL   0xc34f
0154 #define TXC_MTDIABLO_CTRL_PMA_LOOP_LBN  10
0155 
0156 struct txc43128_data {
0157     unsigned long bug10934_timer;
0158     enum ef4_phy_mode phy_mode;
0159     enum ef4_loopback_mode loopback_mode;
0160 };
0161 
0162 /* The PHY sometimes needs a reset to bring the link back up.  So long as
0163  * it reports link down, we reset it every 5 seconds.
0164  */
0165 #define BUG10934_RESET_INTERVAL (5 * HZ)
0166 
0167 /* Perform a reset that doesn't clear configuration changes */
0168 static void txc_reset_logic(struct ef4_nic *efx);
0169 
0170 /* Set the output value of a gpio */
0171 void falcon_txc_set_gpio_val(struct ef4_nic *efx, int pin, int on)
0172 {
0173     ef4_mdio_set_flag(efx, MDIO_MMD_PHYXS, TXC_GPIO_OUTPUT, 1 << pin, on);
0174 }
0175 
0176 /* Set up the GPIO direction register */
0177 void falcon_txc_set_gpio_dir(struct ef4_nic *efx, int pin, int dir)
0178 {
0179     ef4_mdio_set_flag(efx, MDIO_MMD_PHYXS, TXC_GPIO_DIR, 1 << pin, dir);
0180 }
0181 
0182 /* Reset the PMA/PMD MMD. The documentation is explicit that this does a
0183  * global reset (it's less clear what reset of other MMDs does).*/
0184 static int txc_reset_phy(struct ef4_nic *efx)
0185 {
0186     int rc = ef4_mdio_reset_mmd(efx, MDIO_MMD_PMAPMD,
0187                     TXC_MAX_RESET_TIME / TXC_RESET_WAIT,
0188                     TXC_RESET_WAIT);
0189     if (rc < 0)
0190         goto fail;
0191 
0192     /* Check that all the MMDs we expect are present and responding. */
0193     rc = ef4_mdio_check_mmds(efx, TXC_REQUIRED_DEVS);
0194     if (rc < 0)
0195         goto fail;
0196 
0197     return 0;
0198 
0199 fail:
0200     netif_err(efx, hw, efx->net_dev, TXCNAME ": reset timed out!\n");
0201     return rc;
0202 }
0203 
0204 /* Run a single BIST on one MMD */
0205 static int txc_bist_one(struct ef4_nic *efx, int mmd, int test)
0206 {
0207     int ctrl, bctl;
0208     int lane;
0209     int rc = 0;
0210 
0211     /* Set PMA to test into loopback using Mt Diablo reg as per app note */
0212     ctrl = ef4_mdio_read(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL);
0213     ctrl |= (1 << TXC_MTDIABLO_CTRL_PMA_LOOP_LBN);
0214     ef4_mdio_write(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL, ctrl);
0215 
0216     /* The BIST app. note lists these  as 3 distinct steps. */
0217     /* Set the BIST type */
0218     bctl = (test << TXC_BIST_CTRL_TYPE_LBN);
0219     ef4_mdio_write(efx, mmd, TXC_BIST_CTL, bctl);
0220 
0221     /* Set the BSTEN bit in the BIST Control register to enable */
0222     bctl |= (1 << TXC_BIST_CTRL_ENAB_LBN);
0223     ef4_mdio_write(efx, mmd, TXC_BIST_CTL, bctl);
0224 
0225     /* Set the BSTRT bit in the BIST Control register */
0226     ef4_mdio_write(efx, mmd, TXC_BIST_CTL,
0227                bctl | (1 << TXC_BIST_CTRL_STRT_LBN));
0228 
0229     /* Wait. */
0230     udelay(TXC_BIST_DURATION);
0231 
0232     /* Set the BSTOP bit in the BIST Control register */
0233     bctl |= (1 << TXC_BIST_CTRL_STOP_LBN);
0234     ef4_mdio_write(efx, mmd, TXC_BIST_CTL, bctl);
0235 
0236     /* The STOP bit should go off when things have stopped */
0237     while (bctl & (1 << TXC_BIST_CTRL_STOP_LBN))
0238         bctl = ef4_mdio_read(efx, mmd, TXC_BIST_CTL);
0239 
0240     /* Check all the error counts are 0 and all the frame counts are
0241        non-zero */
0242     for (lane = 0; lane < 4; lane++) {
0243         int count = ef4_mdio_read(efx, mmd, TXC_BIST_RX0ERRCNT + lane);
0244         if (count != 0) {
0245             netif_err(efx, hw, efx->net_dev, TXCNAME": BIST error. "
0246                   "Lane %d had %d errs\n", lane, count);
0247             rc = -EIO;
0248         }
0249         count = ef4_mdio_read(efx, mmd, TXC_BIST_RX0FRMCNT + lane);
0250         if (count == 0) {
0251             netif_err(efx, hw, efx->net_dev, TXCNAME": BIST error. "
0252                   "Lane %d got 0 frames\n", lane);
0253             rc = -EIO;
0254         }
0255     }
0256 
0257     if (rc == 0)
0258         netif_info(efx, hw, efx->net_dev, TXCNAME": BIST pass\n");
0259 
0260     /* Disable BIST */
0261     ef4_mdio_write(efx, mmd, TXC_BIST_CTL, 0);
0262 
0263     /* Turn off loopback */
0264     ctrl &= ~(1 << TXC_MTDIABLO_CTRL_PMA_LOOP_LBN);
0265     ef4_mdio_write(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL, ctrl);
0266 
0267     return rc;
0268 }
0269 
0270 static int txc_bist(struct ef4_nic *efx)
0271 {
0272     return txc_bist_one(efx, MDIO_MMD_PCS, TXC_BIST_CTRL_TYPE_TSD);
0273 }
0274 
0275 /* Push the non-configurable defaults into the PHY. This must be
0276  * done after every full reset */
0277 static void txc_apply_defaults(struct ef4_nic *efx)
0278 {
0279     int mctrl;
0280 
0281     /* Turn amplitude down and preemphasis off on the host side
0282      * (PHY<->MAC) as this is believed less likely to upset Falcon
0283      * and no adverse effects have been noted. It probably also
0284      * saves a picowatt or two */
0285 
0286     /* Turn off preemphasis */
0287     ef4_mdio_write(efx, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE0, TXC_ATXPRE_NONE);
0288     ef4_mdio_write(efx, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE1, TXC_ATXPRE_NONE);
0289 
0290     /* Turn down the amplitude */
0291     ef4_mdio_write(efx, MDIO_MMD_PHYXS,
0292                TXC_ALRGS_ATXAMP0, TXC_ATXAMP_0820_BOTH);
0293     ef4_mdio_write(efx, MDIO_MMD_PHYXS,
0294                TXC_ALRGS_ATXAMP1, TXC_ATXAMP_0820_BOTH);
0295 
0296     /* Set the line side amplitude and preemphasis to the databook
0297      * defaults as an erratum causes them to be 0 on at least some
0298      * PHY rev.s */
0299     ef4_mdio_write(efx, MDIO_MMD_PMAPMD,
0300                TXC_ALRGS_ATXPRE0, TXC_ATXPRE_DEFAULT);
0301     ef4_mdio_write(efx, MDIO_MMD_PMAPMD,
0302                TXC_ALRGS_ATXPRE1, TXC_ATXPRE_DEFAULT);
0303     ef4_mdio_write(efx, MDIO_MMD_PMAPMD,
0304                TXC_ALRGS_ATXAMP0, TXC_ATXAMP_DEFAULT);
0305     ef4_mdio_write(efx, MDIO_MMD_PMAPMD,
0306                TXC_ALRGS_ATXAMP1, TXC_ATXAMP_DEFAULT);
0307 
0308     /* Set up the LEDs  */
0309     mctrl = ef4_mdio_read(efx, MDIO_MMD_PHYXS, TXC_MRGS_CTL);
0310 
0311     /* Set the Green and Red LEDs to their default modes */
0312     mctrl &= ~((1 << TXC_MCTL_TXLED_LBN) | (1 << TXC_MCTL_RXLED_LBN));
0313     ef4_mdio_write(efx, MDIO_MMD_PHYXS, TXC_MRGS_CTL, mctrl);
0314 
0315     /* Databook recommends doing this after configuration changes */
0316     txc_reset_logic(efx);
0317 
0318     falcon_board(efx)->type->init_phy(efx);
0319 }
0320 
0321 static int txc43128_phy_probe(struct ef4_nic *efx)
0322 {
0323     struct txc43128_data *phy_data;
0324 
0325     /* Allocate phy private storage */
0326     phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
0327     if (!phy_data)
0328         return -ENOMEM;
0329     efx->phy_data = phy_data;
0330     phy_data->phy_mode = efx->phy_mode;
0331 
0332     efx->mdio.mmds = TXC_REQUIRED_DEVS;
0333     efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
0334 
0335     efx->loopback_modes = TXC_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
0336 
0337     return 0;
0338 }
0339 
0340 /* Initialisation entry point for this PHY driver */
0341 static int txc43128_phy_init(struct ef4_nic *efx)
0342 {
0343     int rc;
0344 
0345     rc = txc_reset_phy(efx);
0346     if (rc < 0)
0347         return rc;
0348 
0349     rc = txc_bist(efx);
0350     if (rc < 0)
0351         return rc;
0352 
0353     txc_apply_defaults(efx);
0354 
0355     return 0;
0356 }
0357 
0358 /* Set the lane power down state in the global registers */
0359 static void txc_glrgs_lane_power(struct ef4_nic *efx, int mmd)
0360 {
0361     int pd = (1 << TXC_GLCMD_L01PD_LBN) | (1 << TXC_GLCMD_L23PD_LBN);
0362     int ctl = ef4_mdio_read(efx, mmd, TXC_GLRGS_GLCMD);
0363 
0364     if (!(efx->phy_mode & PHY_MODE_LOW_POWER))
0365         ctl &= ~pd;
0366     else
0367         ctl |= pd;
0368 
0369     ef4_mdio_write(efx, mmd, TXC_GLRGS_GLCMD, ctl);
0370 }
0371 
0372 /* Set the lane power down state in the analog control registers */
0373 static void txc_analog_lane_power(struct ef4_nic *efx, int mmd)
0374 {
0375     int txpd = (1 << TXC_ATXCTL_TXPD3_LBN) | (1 << TXC_ATXCTL_TXPD2_LBN)
0376         | (1 << TXC_ATXCTL_TXPD1_LBN) | (1 << TXC_ATXCTL_TXPD0_LBN);
0377     int rxpd = (1 << TXC_ARXCTL_RXPD3_LBN) | (1 << TXC_ARXCTL_RXPD2_LBN)
0378         | (1 << TXC_ARXCTL_RXPD1_LBN) | (1 << TXC_ARXCTL_RXPD0_LBN);
0379     int txctl = ef4_mdio_read(efx, mmd, TXC_ALRGS_ATXCTL);
0380     int rxctl = ef4_mdio_read(efx, mmd, TXC_ALRGS_ARXCTL);
0381 
0382     if (!(efx->phy_mode & PHY_MODE_LOW_POWER)) {
0383         txctl &= ~txpd;
0384         rxctl &= ~rxpd;
0385     } else {
0386         txctl |= txpd;
0387         rxctl |= rxpd;
0388     }
0389 
0390     ef4_mdio_write(efx, mmd, TXC_ALRGS_ATXCTL, txctl);
0391     ef4_mdio_write(efx, mmd, TXC_ALRGS_ARXCTL, rxctl);
0392 }
0393 
0394 static void txc_set_power(struct ef4_nic *efx)
0395 {
0396     /* According to the data book, all the MMDs can do low power */
0397     ef4_mdio_set_mmds_lpower(efx,
0398                  !!(efx->phy_mode & PHY_MODE_LOW_POWER),
0399                  TXC_REQUIRED_DEVS);
0400 
0401     /* Global register bank is in PCS, PHY XS. These control the host
0402      * side and line side settings respectively. */
0403     txc_glrgs_lane_power(efx, MDIO_MMD_PCS);
0404     txc_glrgs_lane_power(efx, MDIO_MMD_PHYXS);
0405 
0406     /* Analog register bank in PMA/PMD, PHY XS */
0407     txc_analog_lane_power(efx, MDIO_MMD_PMAPMD);
0408     txc_analog_lane_power(efx, MDIO_MMD_PHYXS);
0409 }
0410 
0411 static void txc_reset_logic_mmd(struct ef4_nic *efx, int mmd)
0412 {
0413     int val = ef4_mdio_read(efx, mmd, TXC_GLRGS_GLCMD);
0414     int tries = 50;
0415 
0416     val |= (1 << TXC_GLCMD_LMTSWRST_LBN);
0417     ef4_mdio_write(efx, mmd, TXC_GLRGS_GLCMD, val);
0418     while (--tries) {
0419         val = ef4_mdio_read(efx, mmd, TXC_GLRGS_GLCMD);
0420         if (!(val & (1 << TXC_GLCMD_LMTSWRST_LBN)))
0421             break;
0422         udelay(1);
0423     }
0424     if (!tries)
0425         netif_info(efx, hw, efx->net_dev,
0426                TXCNAME " Logic reset timed out!\n");
0427 }
0428 
0429 /* Perform a logic reset. This preserves the configuration registers
0430  * and is needed for some configuration changes to take effect */
0431 static void txc_reset_logic(struct ef4_nic *efx)
0432 {
0433     /* The data sheet claims we can do the logic reset on either the
0434      * PCS or the PHYXS and the result is a reset of both host- and
0435      * line-side logic. */
0436     txc_reset_logic_mmd(efx, MDIO_MMD_PCS);
0437 }
0438 
0439 static bool txc43128_phy_read_link(struct ef4_nic *efx)
0440 {
0441     return ef4_mdio_links_ok(efx, TXC_REQUIRED_DEVS);
0442 }
0443 
0444 static int txc43128_phy_reconfigure(struct ef4_nic *efx)
0445 {
0446     struct txc43128_data *phy_data = efx->phy_data;
0447     enum ef4_phy_mode mode_change = efx->phy_mode ^ phy_data->phy_mode;
0448     bool loop_change = LOOPBACK_CHANGED(phy_data, efx, TXC_LOOPBACKS);
0449 
0450     if (efx->phy_mode & mode_change & PHY_MODE_TX_DISABLED) {
0451         txc_reset_phy(efx);
0452         txc_apply_defaults(efx);
0453         falcon_reset_xaui(efx);
0454         mode_change &= ~PHY_MODE_TX_DISABLED;
0455     }
0456 
0457     ef4_mdio_transmit_disable(efx);
0458     ef4_mdio_phy_reconfigure(efx);
0459     if (mode_change & PHY_MODE_LOW_POWER)
0460         txc_set_power(efx);
0461 
0462     /* The data sheet claims this is required after every reconfiguration
0463      * (note at end of 7.1), but we mustn't do it when nothing changes as
0464      * it glitches the link, and reconfigure gets called on link change,
0465      * so we get an IRQ storm on link up. */
0466     if (loop_change || mode_change)
0467         txc_reset_logic(efx);
0468 
0469     phy_data->phy_mode = efx->phy_mode;
0470     phy_data->loopback_mode = efx->loopback_mode;
0471 
0472     return 0;
0473 }
0474 
0475 static void txc43128_phy_fini(struct ef4_nic *efx)
0476 {
0477     /* Disable link events */
0478     ef4_mdio_write(efx, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, 0);
0479 }
0480 
0481 static void txc43128_phy_remove(struct ef4_nic *efx)
0482 {
0483     kfree(efx->phy_data);
0484     efx->phy_data = NULL;
0485 }
0486 
0487 /* Periodic callback: this exists mainly to poll link status as we
0488  * don't use LASI interrupts */
0489 static bool txc43128_phy_poll(struct ef4_nic *efx)
0490 {
0491     struct txc43128_data *data = efx->phy_data;
0492     bool was_up = efx->link_state.up;
0493 
0494     efx->link_state.up = txc43128_phy_read_link(efx);
0495     efx->link_state.speed = 10000;
0496     efx->link_state.fd = true;
0497     efx->link_state.fc = efx->wanted_fc;
0498 
0499     if (efx->link_state.up || (efx->loopback_mode != LOOPBACK_NONE)) {
0500         data->bug10934_timer = jiffies;
0501     } else {
0502         if (time_after_eq(jiffies, (data->bug10934_timer +
0503                         BUG10934_RESET_INTERVAL))) {
0504             data->bug10934_timer = jiffies;
0505             txc_reset_logic(efx);
0506         }
0507     }
0508 
0509     return efx->link_state.up != was_up;
0510 }
0511 
0512 static const char *const txc43128_test_names[] = {
0513     "bist"
0514 };
0515 
0516 static const char *txc43128_test_name(struct ef4_nic *efx, unsigned int index)
0517 {
0518     if (index < ARRAY_SIZE(txc43128_test_names))
0519         return txc43128_test_names[index];
0520     return NULL;
0521 }
0522 
0523 static int txc43128_run_tests(struct ef4_nic *efx, int *results, unsigned flags)
0524 {
0525     int rc;
0526 
0527     if (!(flags & ETH_TEST_FL_OFFLINE))
0528         return 0;
0529 
0530     rc = txc_reset_phy(efx);
0531     if (rc < 0)
0532         return rc;
0533 
0534     rc = txc_bist(efx);
0535     txc_apply_defaults(efx);
0536     results[0] = rc ? -1 : 1;
0537     return rc;
0538 }
0539 
0540 static void txc43128_get_link_ksettings(struct ef4_nic *efx,
0541                     struct ethtool_link_ksettings *cmd)
0542 {
0543     mdio45_ethtool_ksettings_get(&efx->mdio, cmd);
0544 }
0545 
0546 const struct ef4_phy_operations falcon_txc_phy_ops = {
0547     .probe      = txc43128_phy_probe,
0548     .init       = txc43128_phy_init,
0549     .reconfigure    = txc43128_phy_reconfigure,
0550     .poll       = txc43128_phy_poll,
0551     .fini       = txc43128_phy_fini,
0552     .remove     = txc43128_phy_remove,
0553     .get_link_ksettings = txc43128_get_link_ksettings,
0554     .set_link_ksettings = ef4_mdio_set_link_ksettings,
0555     .test_alive = ef4_mdio_test_alive,
0556     .run_tests  = txc43128_run_tests,
0557     .test_name  = txc43128_test_name,
0558 };
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!