sfc/falcon/qt202x_phy.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /****************************************************************************
0003  * Driver for Solarflare network controllers and boards
0004  * Copyright 2006-2012 Solarflare Communications Inc.
0005  */
0006 /*
0007  * Driver for AMCC QT202x SFP+ and XFP adapters; see www.amcc.com for details
0008  */
0009
0010 #include <linux/slab.h>
0011 #include <linux/timer.h>
0012 #include <linux/delay.h>
0013 #include "efx.h"
0014 #include "mdio_10g.h"
0015 #include "phy.h"
0016 #include "nic.h"
0017
0018 #define QT202X_REQUIRED_DEVS (MDIO_DEVS_PCS |       \
0019                   MDIO_DEVS_PMAPMD |    \
0020                   MDIO_DEVS_PHYXS)
0021
0022 #define QT202X_LOOPBACKS ((1 << LOOPBACK_PCS) |     \
0023               (1 << LOOPBACK_PMAPMD) |  \
0024               (1 << LOOPBACK_PHYXS_WS))
0025
0026 /****************************************************************************/
0027 /* Quake-specific MDIO registers */
0028 #define MDIO_QUAKE_LED0_REG (0xD006)
0029
0030 /* QT2025C only */
0031 #define PCS_FW_HEARTBEAT_REG    0xd7ee
0032 #define PCS_FW_HEARTB_LBN   0
0033 #define PCS_FW_HEARTB_WIDTH 8
0034 #define PCS_FW_PRODUCT_CODE_1   0xd7f0
0035 #define PCS_FW_VERSION_1    0xd7f3
0036 #define PCS_FW_BUILD_1      0xd7f6
0037 #define PCS_UC8051_STATUS_REG   0xd7fd
0038 #define PCS_UC_STATUS_LBN   0
0039 #define PCS_UC_STATUS_WIDTH 8
0040 #define PCS_UC_STATUS_FW_SAVE   0x20
0041 #define PMA_PMD_MODE_REG    0xc301
0042 #define PMA_PMD_RXIN_SEL_LBN    6
0043 #define PMA_PMD_FTX_CTRL2_REG   0xc309
0044 #define PMA_PMD_FTX_STATIC_LBN  13
0045 #define PMA_PMD_VEND1_REG   0xc001
0046 #define PMA_PMD_VEND1_LBTXD_LBN 15
0047 #define PCS_VEND1_REG       0xc000
0048 #define PCS_VEND1_LBTXD_LBN 5
0049
0050 void falcon_qt202x_set_led(struct ef4_nic *p, int led, int mode)
0051 {
0052     int addr = MDIO_QUAKE_LED0_REG + led;
0053     ef4_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
0054 }
0055
0056 struct qt202x_phy_data {
0057     enum ef4_phy_mode phy_mode;
0058     bool bug17190_in_bad_state;
0059     unsigned long bug17190_timer;
0060     u32 firmware_ver;
0061 };
0062
0063 #define QT2022C2_MAX_RESET_TIME 500
0064 #define QT2022C2_RESET_WAIT 10
0065
0066 #define QT2025C_MAX_HEARTB_TIME (5 * HZ)
0067 #define QT2025C_HEARTB_WAIT 100
0068 #define QT2025C_MAX_FWSTART_TIME (25 * HZ / 10)
0069 #define QT2025C_FWSTART_WAIT 100
0070
0071 #define BUG17190_INTERVAL (2 * HZ)
0072
0073 static int qt2025c_wait_heartbeat(struct ef4_nic *efx)
0074 {
0075     unsigned long timeout = jiffies + QT2025C_MAX_HEARTB_TIME;
0076     int reg, old_counter = 0;
0077
0078     /* Wait for firmware heartbeat to start */
0079     for (;;) {
0080         int counter;
0081         reg = ef4_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
0082         if (reg < 0)
0083             return reg;
0084         counter = ((reg >> PCS_FW_HEARTB_LBN) &
0085                 ((1 << PCS_FW_HEARTB_WIDTH) - 1));
0086         if (old_counter == 0)
0087             old_counter = counter;
0088         else if (counter != old_counter)
0089             break;
0090         if (time_after(jiffies, timeout)) {
0091             /* Some cables have EEPROMs that conflict with the
0092              * PHY's on-board EEPROM so it cannot load firmware */
0093             netif_err(efx, hw, efx->net_dev,
0094                   "If an SFP+ direct attach cable is"
0095                   " connected, please check that it complies"
0096                   " with the SFP+ specification\n");
0097             return -ETIMEDOUT;
0098         }
0099         msleep(QT2025C_HEARTB_WAIT);
0100     }
0101
0102     return 0;
0103 }
0104
0105 static int qt2025c_wait_fw_status_good(struct ef4_nic *efx)
0106 {
0107     unsigned long timeout = jiffies + QT2025C_MAX_FWSTART_TIME;
0108     int reg;
0109
0110     /* Wait for firmware status to look good */
0111     for (;;) {
0112         reg = ef4_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
0113         if (reg < 0)
0114             return reg;
0115         if ((reg &
0116              ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
0117             PCS_UC_STATUS_FW_SAVE)
0118             break;
0119         if (time_after(jiffies, timeout))
0120             return -ETIMEDOUT;
0121         msleep(QT2025C_FWSTART_WAIT);
0122     }
0123
0124     return 0;
0125 }
0126
0127 static void qt2025c_restart_firmware(struct ef4_nic *efx)
0128 {
0129     /* Restart microcontroller execution of firmware from RAM */
0130     ef4_mdio_write(efx, 3, 0xe854, 0x00c0);
0131     ef4_mdio_write(efx, 3, 0xe854, 0x0040);
0132     msleep(50);
0133 }
0134
0135 static int qt2025c_wait_reset(struct ef4_nic *efx)
0136 {
0137     int rc;
0138
0139     rc = qt2025c_wait_heartbeat(efx);
0140     if (rc != 0)
0141         return rc;
0142
0143     rc = qt2025c_wait_fw_status_good(efx);
0144     if (rc == -ETIMEDOUT) {
0145         /* Bug 17689: occasionally heartbeat starts but firmware status
0146          * code never progresses beyond 0x00.  Try again, once, after
0147          * restarting execution of the firmware image. */
0148         netif_dbg(efx, hw, efx->net_dev,
0149               "bashing QT2025C microcontroller\n");
0150         qt2025c_restart_firmware(efx);
0151         rc = qt2025c_wait_heartbeat(efx);
0152         if (rc != 0)
0153             return rc;
0154         rc = qt2025c_wait_fw_status_good(efx);
0155     }
0156
0157     return rc;
0158 }
0159
0160 static void qt2025c_firmware_id(struct ef4_nic *efx)
0161 {
0162     struct qt202x_phy_data *phy_data = efx->phy_data;
0163     u8 firmware_id[9];
0164     size_t i;
0165
0166     for (i = 0; i < sizeof(firmware_id); i++)
0167         firmware_id[i] = ef4_mdio_read(efx, MDIO_MMD_PCS,
0168                            PCS_FW_PRODUCT_CODE_1 + i);
0169     netif_info(efx, probe, efx->net_dev,
0170            "QT2025C firmware %xr%d v%d.%d.%d.%d [20%02d-%02d-%02d]\n",
0171            (firmware_id[0] << 8) | firmware_id[1], firmware_id[2],
0172            firmware_id[3] >> 4, firmware_id[3] & 0xf,
0173            firmware_id[4], firmware_id[5],
0174            firmware_id[6], firmware_id[7], firmware_id[8]);
0175     phy_data->firmware_ver = ((firmware_id[3] & 0xf0) << 20) |
0176                  ((firmware_id[3] & 0x0f) << 16) |
0177                  (firmware_id[4] << 8) | firmware_id[5];
0178 }
0179
0180 static void qt2025c_bug17190_workaround(struct ef4_nic *efx)
0181 {
0182     struct qt202x_phy_data *phy_data = efx->phy_data;
0183
0184     /* The PHY can get stuck in a state where it reports PHY_XS and PMA/PMD
0185      * layers up, but PCS down (no block_lock).  If we notice this state
0186      * persisting for a couple of seconds, we switch PMA/PMD loopback
0187      * briefly on and then off again, which is normally sufficient to
0188      * recover it.
0189      */
0190     if (efx->link_state.up ||
0191         !ef4_mdio_links_ok(efx, MDIO_DEVS_PMAPMD | MDIO_DEVS_PHYXS)) {
0192         phy_data->bug17190_in_bad_state = false;
0193         return;
0194     }
0195
0196     if (!phy_data->bug17190_in_bad_state) {
0197         phy_data->bug17190_in_bad_state = true;
0198         phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL;
0199         return;
0200     }
0201
0202     if (time_after_eq(jiffies, phy_data->bug17190_timer)) {
0203         netif_dbg(efx, hw, efx->net_dev, "bashing QT2025C PMA/PMD\n");
0204         ef4_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
0205                   MDIO_PMA_CTRL1_LOOPBACK, true);
0206         msleep(100);
0207         ef4_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
0208                   MDIO_PMA_CTRL1_LOOPBACK, false);
0209         phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL;
0210     }
0211 }
0212
0213 static int qt2025c_select_phy_mode(struct ef4_nic *efx)
0214 {
0215     struct qt202x_phy_data *phy_data = efx->phy_data;
0216     struct falcon_board *board = falcon_board(efx);
0217     int reg, rc, i;
0218     uint16_t phy_op_mode;
0219
0220     /* Only 2.0.1.0+ PHY firmware supports the more optimal SFP+
0221      * Self-Configure mode.  Don't attempt any switching if we encounter
0222      * older firmware. */
0223     if (phy_data->firmware_ver < 0x02000100)
0224         return 0;
0225
0226     /* In general we will get optimal behaviour in "SFP+ Self-Configure"
0227      * mode; however, that powers down most of the PHY when no module is
0228      * present, so we must use a different mode (any fixed mode will do)
0229      * to be sure that loopbacks will work. */
0230     phy_op_mode = (efx->loopback_mode == LOOPBACK_NONE) ? 0x0038 : 0x0020;
0231
0232     /* Only change mode if really necessary */
0233     reg = ef4_mdio_read(efx, 1, 0xc319);
0234     if ((reg & 0x0038) == phy_op_mode)
0235         return 0;
0236     netif_dbg(efx, hw, efx->net_dev, "Switching PHY to mode 0x%04x\n",
0237           phy_op_mode);
0238
0239     /* This sequence replicates the register writes configured in the boot
0240      * EEPROM (including the differences between board revisions), except
0241      * that the operating mode is changed, and the PHY is prevented from
0242      * unnecessarily reloading the main firmware image again. */
0243     ef4_mdio_write(efx, 1, 0xc300, 0x0000);
0244     /* (Note: this portion of the boot EEPROM sequence, which bit-bashes 9
0245      * STOPs onto the firmware/module I2C bus to reset it, varies across
0246      * board revisions, as the bus is connected to different GPIO/LED
0247      * outputs on the PHY.) */
0248     if (board->major == 0 && board->minor < 2) {
0249         ef4_mdio_write(efx, 1, 0xc303, 0x4498);
0250         for (i = 0; i < 9; i++) {
0251             ef4_mdio_write(efx, 1, 0xc303, 0x4488);
0252             ef4_mdio_write(efx, 1, 0xc303, 0x4480);
0253             ef4_mdio_write(efx, 1, 0xc303, 0x4490);
0254             ef4_mdio_write(efx, 1, 0xc303, 0x4498);
0255         }
0256     } else {
0257         ef4_mdio_write(efx, 1, 0xc303, 0x0920);
0258         ef4_mdio_write(efx, 1, 0xd008, 0x0004);
0259         for (i = 0; i < 9; i++) {
0260             ef4_mdio_write(efx, 1, 0xc303, 0x0900);
0261             ef4_mdio_write(efx, 1, 0xd008, 0x0005);
0262             ef4_mdio_write(efx, 1, 0xc303, 0x0920);
0263             ef4_mdio_write(efx, 1, 0xd008, 0x0004);
0264         }
0265         ef4_mdio_write(efx, 1, 0xc303, 0x4900);
0266     }
0267     ef4_mdio_write(efx, 1, 0xc303, 0x4900);
0268     ef4_mdio_write(efx, 1, 0xc302, 0x0004);
0269     ef4_mdio_write(efx, 1, 0xc316, 0x0013);
0270     ef4_mdio_write(efx, 1, 0xc318, 0x0054);
0271     ef4_mdio_write(efx, 1, 0xc319, phy_op_mode);
0272     ef4_mdio_write(efx, 1, 0xc31a, 0x0098);
0273     ef4_mdio_write(efx, 3, 0x0026, 0x0e00);
0274     ef4_mdio_write(efx, 3, 0x0027, 0x0013);
0275     ef4_mdio_write(efx, 3, 0x0028, 0xa528);
0276     ef4_mdio_write(efx, 1, 0xd006, 0x000a);
0277     ef4_mdio_write(efx, 1, 0xd007, 0x0009);
0278     ef4_mdio_write(efx, 1, 0xd008, 0x0004);
0279     /* This additional write is not present in the boot EEPROM.  It
0280      * prevents the PHY's internal boot ROM doing another pointless (and
0281      * slow) reload of the firmware image (the microcontroller's code
0282      * memory is not affected by the microcontroller reset). */
0283     ef4_mdio_write(efx, 1, 0xc317, 0x00ff);
0284     /* PMA/PMD loopback sets RXIN to inverse polarity and the firmware
0285      * restart doesn't reset it. We need to do that ourselves. */
0286     ef4_mdio_set_flag(efx, 1, PMA_PMD_MODE_REG,
0287               1 << PMA_PMD_RXIN_SEL_LBN, false);
0288     ef4_mdio_write(efx, 1, 0xc300, 0x0002);
0289     msleep(20);
0290
0291     /* Restart microcontroller execution of firmware from RAM */
0292     qt2025c_restart_firmware(efx);
0293
0294     /* Wait for the microcontroller to be ready again */
0295     rc = qt2025c_wait_reset(efx);
0296     if (rc < 0) {
0297         netif_err(efx, hw, efx->net_dev,
0298               "PHY microcontroller reset during mode switch "
0299               "timed out\n");
0300         return rc;
0301     }
0302
0303     return 0;
0304 }
0305
0306 static int qt202x_reset_phy(struct ef4_nic *efx)
0307 {
0308     int rc;
0309
0310     if (efx->phy_type == PHY_TYPE_QT2025C) {
0311         /* Wait for the reset triggered by falcon_reset_hw()
0312          * to complete */
0313         rc = qt2025c_wait_reset(efx);
0314         if (rc < 0)
0315             goto fail;
0316     } else {
0317         /* Reset the PHYXS MMD. This is documented as doing
0318          * a complete soft reset. */
0319         rc = ef4_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
0320                     QT2022C2_MAX_RESET_TIME /
0321                     QT2022C2_RESET_WAIT,
0322                     QT2022C2_RESET_WAIT);
0323         if (rc < 0)
0324             goto fail;
0325     }
0326
0327     /* Wait 250ms for the PHY to complete bootup */
0328     msleep(250);
0329
0330     falcon_board(efx)->type->init_phy(efx);
0331
0332     return 0;
0333
0334  fail:
0335     netif_err(efx, hw, efx->net_dev, "PHY reset timed out\n");
0336     return rc;
0337 }
0338
0339 static int qt202x_phy_probe(struct ef4_nic *efx)
0340 {
0341     struct qt202x_phy_data *phy_data;
0342
0343     phy_data = kzalloc(sizeof(struct qt202x_phy_data), GFP_KERNEL);
0344     if (!phy_data)
0345         return -ENOMEM;
0346     efx->phy_data = phy_data;
0347     phy_data->phy_mode = efx->phy_mode;
0348     phy_data->bug17190_in_bad_state = false;
0349     phy_data->bug17190_timer = 0;
0350
0351     efx->mdio.mmds = QT202X_REQUIRED_DEVS;
0352     efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
0353     efx->loopback_modes = QT202X_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
0354     return 0;
0355 }
0356
0357 static int qt202x_phy_init(struct ef4_nic *efx)
0358 {
0359     u32 devid;
0360     int rc;
0361
0362     rc = qt202x_reset_phy(efx);
0363     if (rc) {
0364         netif_err(efx, probe, efx->net_dev, "PHY init failed\n");
0365         return rc;
0366     }
0367
0368     devid = ef4_mdio_read_id(efx, MDIO_MMD_PHYXS);
0369     netif_info(efx, probe, efx->net_dev,
0370            "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
0371            devid, ef4_mdio_id_oui(devid), ef4_mdio_id_model(devid),
0372            ef4_mdio_id_rev(devid));
0373
0374     if (efx->phy_type == PHY_TYPE_QT2025C)
0375         qt2025c_firmware_id(efx);
0376
0377     return 0;
0378 }
0379
0380 static int qt202x_link_ok(struct ef4_nic *efx)
0381 {
0382     return ef4_mdio_links_ok(efx, QT202X_REQUIRED_DEVS);
0383 }
0384
0385 static bool qt202x_phy_poll(struct ef4_nic *efx)
0386 {
0387     bool was_up = efx->link_state.up;
0388
0389     efx->link_state.up = qt202x_link_ok(efx);
0390     efx->link_state.speed = 10000;
0391     efx->link_state.fd = true;
0392     efx->link_state.fc = efx->wanted_fc;
0393
0394     if (efx->phy_type == PHY_TYPE_QT2025C)
0395         qt2025c_bug17190_workaround(efx);
0396
0397     return efx->link_state.up != was_up;
0398 }
0399
0400 static int qt202x_phy_reconfigure(struct ef4_nic *efx)
0401 {
0402     struct qt202x_phy_data *phy_data = efx->phy_data;
0403
0404     if (efx->phy_type == PHY_TYPE_QT2025C) {
0405         int rc = qt2025c_select_phy_mode(efx);
0406         if (rc)
0407             return rc;
0408
0409         /* There are several different register bits which can
0410          * disable TX (and save power) on direct-attach cables
0411          * or optical transceivers, varying somewhat between
0412          * firmware versions.  Only 'static mode' appears to
0413          * cover everything. */
0414         mdio_set_flag(
0415             &efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
0416             PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
0417             efx->phy_mode & PHY_MODE_TX_DISABLED ||
0418             efx->phy_mode & PHY_MODE_LOW_POWER ||
0419             efx->loopback_mode == LOOPBACK_PCS ||
0420             efx->loopback_mode == LOOPBACK_PMAPMD);
0421     } else {
0422         /* Reset the PHY when moving from tx off to tx on */
0423         if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
0424             (phy_data->phy_mode & PHY_MODE_TX_DISABLED))
0425             qt202x_reset_phy(efx);
0426
0427         ef4_mdio_transmit_disable(efx);
0428     }
0429
0430     ef4_mdio_phy_reconfigure(efx);
0431
0432     phy_data->phy_mode = efx->phy_mode;
0433
0434     return 0;
0435 }
0436
0437 static void qt202x_phy_get_link_ksettings(struct ef4_nic *efx,
0438                       struct ethtool_link_ksettings *cmd)
0439 {
0440     mdio45_ethtool_ksettings_get(&efx->mdio, cmd);
0441 }
0442
0443 static void qt202x_phy_remove(struct ef4_nic *efx)
0444 {
0445     /* Free the context block */
0446     kfree(efx->phy_data);
0447     efx->phy_data = NULL;
0448 }
0449
0450 static int qt202x_phy_get_module_info(struct ef4_nic *efx,
0451                       struct ethtool_modinfo *modinfo)
0452 {
0453     modinfo->type = ETH_MODULE_SFF_8079;
0454     modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
0455     return 0;
0456 }
0457
0458 static int qt202x_phy_get_module_eeprom(struct ef4_nic *efx,
0459                     struct ethtool_eeprom *ee, u8 *data)
0460 {
0461     int mmd, reg_base, rc, i;
0462
0463     if (efx->phy_type == PHY_TYPE_QT2025C) {
0464         mmd = MDIO_MMD_PCS;
0465         reg_base = 0xd000;
0466     } else {
0467         mmd = MDIO_MMD_PMAPMD;
0468         reg_base = 0x8007;
0469     }
0470
0471     for (i = 0; i < ee->len; i++) {
0472         rc = ef4_mdio_read(efx, mmd, reg_base + ee->offset + i);
0473         if (rc < 0)
0474             return rc;
0475         data[i] = rc;
0476     }
0477
0478     return 0;
0479 }
0480
0481 const struct ef4_phy_operations falcon_qt202x_phy_ops = {
0482     .probe       = qt202x_phy_probe,
0483     .init        = qt202x_phy_init,
0484     .reconfigure     = qt202x_phy_reconfigure,
0485     .poll        = qt202x_phy_poll,
0486     .fini        = ef4_port_dummy_op_void,
0487     .remove      = qt202x_phy_remove,
0488     .get_link_ksettings = qt202x_phy_get_link_ksettings,
0489     .set_link_ksettings = ef4_mdio_set_link_ksettings,
0490     .test_alive  = ef4_mdio_test_alive,
0491     .get_module_eeprom = qt202x_phy_get_module_eeprom,
0492     .get_module_info = qt202x_phy_get_module_info,
0493 };