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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /****************************************************************************
0003  * Driver for Solarflare network controllers and boards
0004  * Copyright 2005-2006 Fen Systems Ltd.
0005  * Copyright 2006-2013 Solarflare Communications Inc.
0006  */
0007 
0008 #ifndef EF4_NIC_H
0009 #define EF4_NIC_H
0010 
0011 #include <linux/net_tstamp.h>
0012 #include <linux/i2c-algo-bit.h>
0013 #include "net_driver.h"
0014 #include "efx.h"
0015 
0016 enum {
0017     EF4_REV_FALCON_A0 = 0,
0018     EF4_REV_FALCON_A1 = 1,
0019     EF4_REV_FALCON_B0 = 2,
0020 };
0021 
0022 static inline int ef4_nic_rev(struct ef4_nic *efx)
0023 {
0024     return efx->type->revision;
0025 }
0026 
0027 u32 ef4_farch_fpga_ver(struct ef4_nic *efx);
0028 
0029 /* NIC has two interlinked PCI functions for the same port. */
0030 static inline bool ef4_nic_is_dual_func(struct ef4_nic *efx)
0031 {
0032     return ef4_nic_rev(efx) < EF4_REV_FALCON_B0;
0033 }
0034 
0035 /* Read the current event from the event queue */
0036 static inline ef4_qword_t *ef4_event(struct ef4_channel *channel,
0037                      unsigned int index)
0038 {
0039     return ((ef4_qword_t *) (channel->eventq.buf.addr)) +
0040         (index & channel->eventq_mask);
0041 }
0042 
0043 /* See if an event is present
0044  *
0045  * We check both the high and low dword of the event for all ones.  We
0046  * wrote all ones when we cleared the event, and no valid event can
0047  * have all ones in either its high or low dwords.  This approach is
0048  * robust against reordering.
0049  *
0050  * Note that using a single 64-bit comparison is incorrect; even
0051  * though the CPU read will be atomic, the DMA write may not be.
0052  */
0053 static inline int ef4_event_present(ef4_qword_t *event)
0054 {
0055     return !(EF4_DWORD_IS_ALL_ONES(event->dword[0]) |
0056           EF4_DWORD_IS_ALL_ONES(event->dword[1]));
0057 }
0058 
0059 /* Returns a pointer to the specified transmit descriptor in the TX
0060  * descriptor queue belonging to the specified channel.
0061  */
0062 static inline ef4_qword_t *
0063 ef4_tx_desc(struct ef4_tx_queue *tx_queue, unsigned int index)
0064 {
0065     return ((ef4_qword_t *) (tx_queue->txd.buf.addr)) + index;
0066 }
0067 
0068 /* Get partner of a TX queue, seen as part of the same net core queue */
0069 static inline struct ef4_tx_queue *ef4_tx_queue_partner(struct ef4_tx_queue *tx_queue)
0070 {
0071     if (tx_queue->queue & EF4_TXQ_TYPE_OFFLOAD)
0072         return tx_queue - EF4_TXQ_TYPE_OFFLOAD;
0073     else
0074         return tx_queue + EF4_TXQ_TYPE_OFFLOAD;
0075 }
0076 
0077 /* Report whether this TX queue would be empty for the given write_count.
0078  * May return false negative.
0079  */
0080 static inline bool __ef4_nic_tx_is_empty(struct ef4_tx_queue *tx_queue,
0081                      unsigned int write_count)
0082 {
0083     unsigned int empty_read_count = READ_ONCE(tx_queue->empty_read_count);
0084 
0085     if (empty_read_count == 0)
0086         return false;
0087 
0088     return ((empty_read_count ^ write_count) & ~EF4_EMPTY_COUNT_VALID) == 0;
0089 }
0090 
0091 /* Decide whether to push a TX descriptor to the NIC vs merely writing
0092  * the doorbell.  This can reduce latency when we are adding a single
0093  * descriptor to an empty queue, but is otherwise pointless.  Further,
0094  * Falcon and Siena have hardware bugs (SF bug 33851) that may be
0095  * triggered if we don't check this.
0096  * We use the write_count used for the last doorbell push, to get the
0097  * NIC's view of the tx queue.
0098  */
0099 static inline bool ef4_nic_may_push_tx_desc(struct ef4_tx_queue *tx_queue,
0100                         unsigned int write_count)
0101 {
0102     bool was_empty = __ef4_nic_tx_is_empty(tx_queue, write_count);
0103 
0104     tx_queue->empty_read_count = 0;
0105     return was_empty && tx_queue->write_count - write_count == 1;
0106 }
0107 
0108 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
0109 static inline ef4_qword_t *
0110 ef4_rx_desc(struct ef4_rx_queue *rx_queue, unsigned int index)
0111 {
0112     return ((ef4_qword_t *) (rx_queue->rxd.buf.addr)) + index;
0113 }
0114 
0115 enum {
0116     PHY_TYPE_NONE = 0,
0117     PHY_TYPE_TXC43128 = 1,
0118     PHY_TYPE_88E1111 = 2,
0119     PHY_TYPE_SFX7101 = 3,
0120     PHY_TYPE_QT2022C2 = 4,
0121     PHY_TYPE_PM8358 = 6,
0122     PHY_TYPE_SFT9001A = 8,
0123     PHY_TYPE_QT2025C = 9,
0124     PHY_TYPE_SFT9001B = 10,
0125 };
0126 
0127 #define FALCON_XMAC_LOOPBACKS           \
0128     ((1 << LOOPBACK_XGMII) |        \
0129      (1 << LOOPBACK_XGXS) |         \
0130      (1 << LOOPBACK_XAUI))
0131 
0132 /* Alignment of PCIe DMA boundaries (4KB) */
0133 #define EF4_PAGE_SIZE   4096
0134 /* Size and alignment of buffer table entries (same) */
0135 #define EF4_BUF_SIZE    EF4_PAGE_SIZE
0136 
0137 /* NIC-generic software stats */
0138 enum {
0139     GENERIC_STAT_rx_noskb_drops,
0140     GENERIC_STAT_rx_nodesc_trunc,
0141     GENERIC_STAT_COUNT
0142 };
0143 
0144 /**
0145  * struct falcon_board_type - board operations and type information
0146  * @id: Board type id, as found in NVRAM
0147  * @init: Allocate resources and initialise peripheral hardware
0148  * @init_phy: Do board-specific PHY initialisation
0149  * @fini: Shut down hardware and free resources
0150  * @set_id_led: Set state of identifying LED or revert to automatic function
0151  * @monitor: Board-specific health check function
0152  */
0153 struct falcon_board_type {
0154     u8 id;
0155     int (*init) (struct ef4_nic *nic);
0156     void (*init_phy) (struct ef4_nic *efx);
0157     void (*fini) (struct ef4_nic *nic);
0158     void (*set_id_led) (struct ef4_nic *efx, enum ef4_led_mode mode);
0159     int (*monitor) (struct ef4_nic *nic);
0160 };
0161 
0162 /**
0163  * struct falcon_board - board information
0164  * @type: Type of board
0165  * @major: Major rev. ('A', 'B' ...)
0166  * @minor: Minor rev. (0, 1, ...)
0167  * @i2c_adap: I2C adapter for on-board peripherals
0168  * @i2c_data: Data for bit-banging algorithm
0169  * @hwmon_client: I2C client for hardware monitor
0170  * @ioexp_client: I2C client for power/port control
0171  */
0172 struct falcon_board {
0173     const struct falcon_board_type *type;
0174     int major;
0175     int minor;
0176     struct i2c_adapter i2c_adap;
0177     struct i2c_algo_bit_data i2c_data;
0178     struct i2c_client *hwmon_client, *ioexp_client;
0179 };
0180 
0181 /**
0182  * struct falcon_spi_device - a Falcon SPI (Serial Peripheral Interface) device
0183  * @device_id:      Controller's id for the device
0184  * @size:       Size (in bytes)
0185  * @addr_len:       Number of address bytes in read/write commands
0186  * @munge_address:  Flag whether addresses should be munged.
0187  *  Some devices with 9-bit addresses (e.g. AT25040A EEPROM)
0188  *  use bit 3 of the command byte as address bit A8, rather
0189  *  than having a two-byte address.  If this flag is set, then
0190  *  commands should be munged in this way.
0191  * @erase_command:  Erase command (or 0 if sector erase not needed).
0192  * @erase_size:     Erase sector size (in bytes)
0193  *  Erase commands affect sectors with this size and alignment.
0194  *  This must be a power of two.
0195  * @block_size:     Write block size (in bytes).
0196  *  Write commands are limited to blocks with this size and alignment.
0197  */
0198 struct falcon_spi_device {
0199     int device_id;
0200     unsigned int size;
0201     unsigned int addr_len;
0202     unsigned int munge_address:1;
0203     u8 erase_command;
0204     unsigned int erase_size;
0205     unsigned int block_size;
0206 };
0207 
0208 static inline bool falcon_spi_present(const struct falcon_spi_device *spi)
0209 {
0210     return spi->size != 0;
0211 }
0212 
0213 enum {
0214     FALCON_STAT_tx_bytes = GENERIC_STAT_COUNT,
0215     FALCON_STAT_tx_packets,
0216     FALCON_STAT_tx_pause,
0217     FALCON_STAT_tx_control,
0218     FALCON_STAT_tx_unicast,
0219     FALCON_STAT_tx_multicast,
0220     FALCON_STAT_tx_broadcast,
0221     FALCON_STAT_tx_lt64,
0222     FALCON_STAT_tx_64,
0223     FALCON_STAT_tx_65_to_127,
0224     FALCON_STAT_tx_128_to_255,
0225     FALCON_STAT_tx_256_to_511,
0226     FALCON_STAT_tx_512_to_1023,
0227     FALCON_STAT_tx_1024_to_15xx,
0228     FALCON_STAT_tx_15xx_to_jumbo,
0229     FALCON_STAT_tx_gtjumbo,
0230     FALCON_STAT_tx_non_tcpudp,
0231     FALCON_STAT_tx_mac_src_error,
0232     FALCON_STAT_tx_ip_src_error,
0233     FALCON_STAT_rx_bytes,
0234     FALCON_STAT_rx_good_bytes,
0235     FALCON_STAT_rx_bad_bytes,
0236     FALCON_STAT_rx_packets,
0237     FALCON_STAT_rx_good,
0238     FALCON_STAT_rx_bad,
0239     FALCON_STAT_rx_pause,
0240     FALCON_STAT_rx_control,
0241     FALCON_STAT_rx_unicast,
0242     FALCON_STAT_rx_multicast,
0243     FALCON_STAT_rx_broadcast,
0244     FALCON_STAT_rx_lt64,
0245     FALCON_STAT_rx_64,
0246     FALCON_STAT_rx_65_to_127,
0247     FALCON_STAT_rx_128_to_255,
0248     FALCON_STAT_rx_256_to_511,
0249     FALCON_STAT_rx_512_to_1023,
0250     FALCON_STAT_rx_1024_to_15xx,
0251     FALCON_STAT_rx_15xx_to_jumbo,
0252     FALCON_STAT_rx_gtjumbo,
0253     FALCON_STAT_rx_bad_lt64,
0254     FALCON_STAT_rx_bad_gtjumbo,
0255     FALCON_STAT_rx_overflow,
0256     FALCON_STAT_rx_symbol_error,
0257     FALCON_STAT_rx_align_error,
0258     FALCON_STAT_rx_length_error,
0259     FALCON_STAT_rx_internal_error,
0260     FALCON_STAT_rx_nodesc_drop_cnt,
0261     FALCON_STAT_COUNT
0262 };
0263 
0264 /**
0265  * struct falcon_nic_data - Falcon NIC state
0266  * @pci_dev2: Secondary function of Falcon A
0267  * @efx: ef4_nic pointer
0268  * @board: Board state and functions
0269  * @stats: Hardware statistics
0270  * @stats_disable_count: Nest count for disabling statistics fetches
0271  * @stats_pending: Is there a pending DMA of MAC statistics.
0272  * @stats_timer: A timer for regularly fetching MAC statistics.
0273  * @spi_flash: SPI flash device
0274  * @spi_eeprom: SPI EEPROM device
0275  * @spi_lock: SPI bus lock
0276  * @mdio_lock: MDIO bus lock
0277  * @xmac_poll_required: XMAC link state needs polling
0278  */
0279 struct falcon_nic_data {
0280     struct pci_dev *pci_dev2;
0281     struct ef4_nic *efx;
0282     struct falcon_board board;
0283     u64 stats[FALCON_STAT_COUNT];
0284     unsigned int stats_disable_count;
0285     bool stats_pending;
0286     struct timer_list stats_timer;
0287     struct falcon_spi_device spi_flash;
0288     struct falcon_spi_device spi_eeprom;
0289     struct mutex spi_lock;
0290     struct mutex mdio_lock;
0291     bool xmac_poll_required;
0292 };
0293 
0294 static inline struct falcon_board *falcon_board(struct ef4_nic *efx)
0295 {
0296     struct falcon_nic_data *data = efx->nic_data;
0297     return &data->board;
0298 }
0299 
0300 struct ethtool_ts_info;
0301 
0302 extern const struct ef4_nic_type falcon_a1_nic_type;
0303 extern const struct ef4_nic_type falcon_b0_nic_type;
0304 
0305 /**************************************************************************
0306  *
0307  * Externs
0308  *
0309  **************************************************************************
0310  */
0311 
0312 int falcon_probe_board(struct ef4_nic *efx, u16 revision_info);
0313 
0314 /* TX data path */
0315 static inline int ef4_nic_probe_tx(struct ef4_tx_queue *tx_queue)
0316 {
0317     return tx_queue->efx->type->tx_probe(tx_queue);
0318 }
0319 static inline void ef4_nic_init_tx(struct ef4_tx_queue *tx_queue)
0320 {
0321     tx_queue->efx->type->tx_init(tx_queue);
0322 }
0323 static inline void ef4_nic_remove_tx(struct ef4_tx_queue *tx_queue)
0324 {
0325     tx_queue->efx->type->tx_remove(tx_queue);
0326 }
0327 static inline void ef4_nic_push_buffers(struct ef4_tx_queue *tx_queue)
0328 {
0329     tx_queue->efx->type->tx_write(tx_queue);
0330 }
0331 
0332 /* RX data path */
0333 static inline int ef4_nic_probe_rx(struct ef4_rx_queue *rx_queue)
0334 {
0335     return rx_queue->efx->type->rx_probe(rx_queue);
0336 }
0337 static inline void ef4_nic_init_rx(struct ef4_rx_queue *rx_queue)
0338 {
0339     rx_queue->efx->type->rx_init(rx_queue);
0340 }
0341 static inline void ef4_nic_remove_rx(struct ef4_rx_queue *rx_queue)
0342 {
0343     rx_queue->efx->type->rx_remove(rx_queue);
0344 }
0345 static inline void ef4_nic_notify_rx_desc(struct ef4_rx_queue *rx_queue)
0346 {
0347     rx_queue->efx->type->rx_write(rx_queue);
0348 }
0349 static inline void ef4_nic_generate_fill_event(struct ef4_rx_queue *rx_queue)
0350 {
0351     rx_queue->efx->type->rx_defer_refill(rx_queue);
0352 }
0353 
0354 /* Event data path */
0355 static inline int ef4_nic_probe_eventq(struct ef4_channel *channel)
0356 {
0357     return channel->efx->type->ev_probe(channel);
0358 }
0359 static inline int ef4_nic_init_eventq(struct ef4_channel *channel)
0360 {
0361     return channel->efx->type->ev_init(channel);
0362 }
0363 static inline void ef4_nic_fini_eventq(struct ef4_channel *channel)
0364 {
0365     channel->efx->type->ev_fini(channel);
0366 }
0367 static inline void ef4_nic_remove_eventq(struct ef4_channel *channel)
0368 {
0369     channel->efx->type->ev_remove(channel);
0370 }
0371 static inline int
0372 ef4_nic_process_eventq(struct ef4_channel *channel, int quota)
0373 {
0374     return channel->efx->type->ev_process(channel, quota);
0375 }
0376 static inline void ef4_nic_eventq_read_ack(struct ef4_channel *channel)
0377 {
0378     channel->efx->type->ev_read_ack(channel);
0379 }
0380 void ef4_nic_event_test_start(struct ef4_channel *channel);
0381 
0382 /* queue operations */
0383 int ef4_farch_tx_probe(struct ef4_tx_queue *tx_queue);
0384 void ef4_farch_tx_init(struct ef4_tx_queue *tx_queue);
0385 void ef4_farch_tx_fini(struct ef4_tx_queue *tx_queue);
0386 void ef4_farch_tx_remove(struct ef4_tx_queue *tx_queue);
0387 void ef4_farch_tx_write(struct ef4_tx_queue *tx_queue);
0388 unsigned int ef4_farch_tx_limit_len(struct ef4_tx_queue *tx_queue,
0389                     dma_addr_t dma_addr, unsigned int len);
0390 int ef4_farch_rx_probe(struct ef4_rx_queue *rx_queue);
0391 void ef4_farch_rx_init(struct ef4_rx_queue *rx_queue);
0392 void ef4_farch_rx_fini(struct ef4_rx_queue *rx_queue);
0393 void ef4_farch_rx_remove(struct ef4_rx_queue *rx_queue);
0394 void ef4_farch_rx_write(struct ef4_rx_queue *rx_queue);
0395 void ef4_farch_rx_defer_refill(struct ef4_rx_queue *rx_queue);
0396 int ef4_farch_ev_probe(struct ef4_channel *channel);
0397 int ef4_farch_ev_init(struct ef4_channel *channel);
0398 void ef4_farch_ev_fini(struct ef4_channel *channel);
0399 void ef4_farch_ev_remove(struct ef4_channel *channel);
0400 int ef4_farch_ev_process(struct ef4_channel *channel, int quota);
0401 void ef4_farch_ev_read_ack(struct ef4_channel *channel);
0402 void ef4_farch_ev_test_generate(struct ef4_channel *channel);
0403 
0404 /* filter operations */
0405 int ef4_farch_filter_table_probe(struct ef4_nic *efx);
0406 void ef4_farch_filter_table_restore(struct ef4_nic *efx);
0407 void ef4_farch_filter_table_remove(struct ef4_nic *efx);
0408 void ef4_farch_filter_update_rx_scatter(struct ef4_nic *efx);
0409 s32 ef4_farch_filter_insert(struct ef4_nic *efx, struct ef4_filter_spec *spec,
0410                 bool replace);
0411 int ef4_farch_filter_remove_safe(struct ef4_nic *efx,
0412                  enum ef4_filter_priority priority,
0413                  u32 filter_id);
0414 int ef4_farch_filter_get_safe(struct ef4_nic *efx,
0415                   enum ef4_filter_priority priority, u32 filter_id,
0416                   struct ef4_filter_spec *);
0417 int ef4_farch_filter_clear_rx(struct ef4_nic *efx,
0418                   enum ef4_filter_priority priority);
0419 u32 ef4_farch_filter_count_rx_used(struct ef4_nic *efx,
0420                    enum ef4_filter_priority priority);
0421 u32 ef4_farch_filter_get_rx_id_limit(struct ef4_nic *efx);
0422 s32 ef4_farch_filter_get_rx_ids(struct ef4_nic *efx,
0423                 enum ef4_filter_priority priority, u32 *buf,
0424                 u32 size);
0425 #ifdef CONFIG_RFS_ACCEL
0426 s32 ef4_farch_filter_rfs_insert(struct ef4_nic *efx,
0427                 struct ef4_filter_spec *spec);
0428 bool ef4_farch_filter_rfs_expire_one(struct ef4_nic *efx, u32 flow_id,
0429                      unsigned int index);
0430 #endif
0431 void ef4_farch_filter_sync_rx_mode(struct ef4_nic *efx);
0432 
0433 bool ef4_nic_event_present(struct ef4_channel *channel);
0434 
0435 /* Some statistics are computed as A - B where A and B each increase
0436  * linearly with some hardware counter(s) and the counters are read
0437  * asynchronously.  If the counters contributing to B are always read
0438  * after those contributing to A, the computed value may be lower than
0439  * the true value by some variable amount, and may decrease between
0440  * subsequent computations.
0441  *
0442  * We should never allow statistics to decrease or to exceed the true
0443  * value.  Since the computed value will never be greater than the
0444  * true value, we can achieve this by only storing the computed value
0445  * when it increases.
0446  */
0447 static inline void ef4_update_diff_stat(u64 *stat, u64 diff)
0448 {
0449     if ((s64)(diff - *stat) > 0)
0450         *stat = diff;
0451 }
0452 
0453 /* Interrupts */
0454 int ef4_nic_init_interrupt(struct ef4_nic *efx);
0455 int ef4_nic_irq_test_start(struct ef4_nic *efx);
0456 void ef4_nic_fini_interrupt(struct ef4_nic *efx);
0457 void ef4_farch_irq_enable_master(struct ef4_nic *efx);
0458 int ef4_farch_irq_test_generate(struct ef4_nic *efx);
0459 void ef4_farch_irq_disable_master(struct ef4_nic *efx);
0460 irqreturn_t ef4_farch_msi_interrupt(int irq, void *dev_id);
0461 irqreturn_t ef4_farch_legacy_interrupt(int irq, void *dev_id);
0462 irqreturn_t ef4_farch_fatal_interrupt(struct ef4_nic *efx);
0463 
0464 static inline int ef4_nic_event_test_irq_cpu(struct ef4_channel *channel)
0465 {
0466     return READ_ONCE(channel->event_test_cpu);
0467 }
0468 static inline int ef4_nic_irq_test_irq_cpu(struct ef4_nic *efx)
0469 {
0470     return READ_ONCE(efx->last_irq_cpu);
0471 }
0472 
0473 /* Global Resources */
0474 int ef4_nic_flush_queues(struct ef4_nic *efx);
0475 int ef4_farch_fini_dmaq(struct ef4_nic *efx);
0476 void ef4_farch_finish_flr(struct ef4_nic *efx);
0477 void falcon_start_nic_stats(struct ef4_nic *efx);
0478 void falcon_stop_nic_stats(struct ef4_nic *efx);
0479 int falcon_reset_xaui(struct ef4_nic *efx);
0480 void ef4_farch_dimension_resources(struct ef4_nic *efx, unsigned sram_lim_qw);
0481 void ef4_farch_init_common(struct ef4_nic *efx);
0482 void ef4_farch_rx_push_indir_table(struct ef4_nic *efx);
0483 
0484 int ef4_nic_alloc_buffer(struct ef4_nic *efx, struct ef4_buffer *buffer,
0485              unsigned int len, gfp_t gfp_flags);
0486 void ef4_nic_free_buffer(struct ef4_nic *efx, struct ef4_buffer *buffer);
0487 
0488 /* Tests */
0489 struct ef4_farch_register_test {
0490     unsigned address;
0491     ef4_oword_t mask;
0492 };
0493 int ef4_farch_test_registers(struct ef4_nic *efx,
0494                  const struct ef4_farch_register_test *regs,
0495                  size_t n_regs);
0496 
0497 size_t ef4_nic_get_regs_len(struct ef4_nic *efx);
0498 void ef4_nic_get_regs(struct ef4_nic *efx, void *buf);
0499 
0500 size_t ef4_nic_describe_stats(const struct ef4_hw_stat_desc *desc, size_t count,
0501                   const unsigned long *mask, u8 *names);
0502 void ef4_nic_update_stats(const struct ef4_hw_stat_desc *desc, size_t count,
0503               const unsigned long *mask, u64 *stats,
0504               const void *dma_buf, bool accumulate);
0505 void ef4_nic_fix_nodesc_drop_stat(struct ef4_nic *efx, u64 *stat);
0506 
0507 #define EF4_MAX_FLUSH_TIME 5000
0508 
0509 void ef4_farch_generate_event(struct ef4_nic *efx, unsigned int evq,
0510                   ef4_qword_t *event);
0511 
0512 #endif /* EF4_NIC_H */
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