sfc/falcon/io.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /****************************************************************************
0003  * Driver for Solarflare network controllers and boards
0004  * Copyright 2005-2006 Fen Systems Ltd.
0005  * Copyright 2006-2013 Solarflare Communications Inc.
0006  */
0007
0008 #ifndef EF4_IO_H
0009 #define EF4_IO_H
0010
0011 #include <linux/io.h>
0012 #include <linux/spinlock.h>
0013
0014 /**************************************************************************
0015  *
0016  * NIC register I/O
0017  *
0018  **************************************************************************
0019  *
0020  * Notes on locking strategy for the Falcon architecture:
0021  *
0022  * Many CSRs are very wide and cannot be read or written atomically.
0023  * Writes from the host are buffered by the Bus Interface Unit (BIU)
0024  * up to 128 bits.  Whenever the host writes part of such a register,
0025  * the BIU collects the written value and does not write to the
0026  * underlying register until all 4 dwords have been written.  A
0027  * similar buffering scheme applies to host access to the NIC's 64-bit
0028  * SRAM.
0029  *
0030  * Writes to different CSRs and 64-bit SRAM words must be serialised,
0031  * since interleaved access can result in lost writes.  We use
0032  * ef4_nic::biu_lock for this.
0033  *
0034  * We also serialise reads from 128-bit CSRs and SRAM with the same
0035  * spinlock.  This may not be necessary, but it doesn't really matter
0036  * as there are no such reads on the fast path.
0037  *
0038  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
0039  * 128-bit but are special-cased in the BIU to avoid the need for
0040  * locking in the host:
0041  *
0042  * - They are write-only.
0043  * - The semantics of writing to these registers are such that
0044  *   replacing the low 96 bits with zero does not affect functionality.
0045  * - If the host writes to the last dword address of such a register
0046  *   (i.e. the high 32 bits) the underlying register will always be
0047  *   written.  If the collector and the current write together do not
0048  *   provide values for all 128 bits of the register, the low 96 bits
0049  *   will be written as zero.
0050  * - If the host writes to the address of any other part of such a
0051  *   register while the collector already holds values for some other
0052  *   register, the write is discarded and the collector maintains its
0053  *   current state.
0054  *
0055  * The EF10 architecture exposes very few registers to the host and
0056  * most of them are only 32 bits wide.  The only exceptions are the MC
0057  * doorbell register pair, which has its own latching, and
0058  * TX_DESC_UPD, which works in a similar way to the Falcon
0059  * architecture.
0060  */
0061
0062 #if BITS_PER_LONG == 64
0063 #define EF4_USE_QWORD_IO 1
0064 #endif
0065
0066 #ifdef EF4_USE_QWORD_IO
0067 static inline void _ef4_writeq(struct ef4_nic *efx, __le64 value,
0068                   unsigned int reg)
0069 {
0070     __raw_writeq((__force u64)value, efx->membase + reg);
0071 }
0072 static inline __le64 _ef4_readq(struct ef4_nic *efx, unsigned int reg)
0073 {
0074     return (__force __le64)__raw_readq(efx->membase + reg);
0075 }
0076 #endif
0077
0078 static inline void _ef4_writed(struct ef4_nic *efx, __le32 value,
0079                   unsigned int reg)
0080 {
0081     __raw_writel((__force u32)value, efx->membase + reg);
0082 }
0083 static inline __le32 _ef4_readd(struct ef4_nic *efx, unsigned int reg)
0084 {
0085     return (__force __le32)__raw_readl(efx->membase + reg);
0086 }
0087
0088 /* Write a normal 128-bit CSR, locking as appropriate. */
0089 static inline void ef4_writeo(struct ef4_nic *efx, const ef4_oword_t *value,
0090                   unsigned int reg)
0091 {
0092     unsigned long flags __attribute__ ((unused));
0093
0094     netif_vdbg(efx, hw, efx->net_dev,
0095            "writing register %x with " EF4_OWORD_FMT "\n", reg,
0096            EF4_OWORD_VAL(*value));
0097
0098     spin_lock_irqsave(&efx->biu_lock, flags);
0099 #ifdef EF4_USE_QWORD_IO
0100     _ef4_writeq(efx, value->u64[0], reg + 0);
0101     _ef4_writeq(efx, value->u64[1], reg + 8);
0102 #else
0103     _ef4_writed(efx, value->u32[0], reg + 0);
0104     _ef4_writed(efx, value->u32[1], reg + 4);
0105     _ef4_writed(efx, value->u32[2], reg + 8);
0106     _ef4_writed(efx, value->u32[3], reg + 12);
0107 #endif
0108     spin_unlock_irqrestore(&efx->biu_lock, flags);
0109 }
0110
0111 /* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
0112 static inline void ef4_sram_writeq(struct ef4_nic *efx, void __iomem *membase,
0113                    const ef4_qword_t *value, unsigned int index)
0114 {
0115     unsigned int addr = index * sizeof(*value);
0116     unsigned long flags __attribute__ ((unused));
0117
0118     netif_vdbg(efx, hw, efx->net_dev,
0119            "writing SRAM address %x with " EF4_QWORD_FMT "\n",
0120            addr, EF4_QWORD_VAL(*value));
0121
0122     spin_lock_irqsave(&efx->biu_lock, flags);
0123 #ifdef EF4_USE_QWORD_IO
0124     __raw_writeq((__force u64)value->u64[0], membase + addr);
0125 #else
0126     __raw_writel((__force u32)value->u32[0], membase + addr);
0127     __raw_writel((__force u32)value->u32[1], membase + addr + 4);
0128 #endif
0129     spin_unlock_irqrestore(&efx->biu_lock, flags);
0130 }
0131
0132 /* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
0133 static inline void ef4_writed(struct ef4_nic *efx, const ef4_dword_t *value,
0134                   unsigned int reg)
0135 {
0136     netif_vdbg(efx, hw, efx->net_dev,
0137            "writing register %x with "EF4_DWORD_FMT"\n",
0138            reg, EF4_DWORD_VAL(*value));
0139
0140     /* No lock required */
0141     _ef4_writed(efx, value->u32[0], reg);
0142 }
0143
0144 /* Read a 128-bit CSR, locking as appropriate. */
0145 static inline void ef4_reado(struct ef4_nic *efx, ef4_oword_t *value,
0146                  unsigned int reg)
0147 {
0148     unsigned long flags __attribute__ ((unused));
0149
0150     spin_lock_irqsave(&efx->biu_lock, flags);
0151     value->u32[0] = _ef4_readd(efx, reg + 0);
0152     value->u32[1] = _ef4_readd(efx, reg + 4);
0153     value->u32[2] = _ef4_readd(efx, reg + 8);
0154     value->u32[3] = _ef4_readd(efx, reg + 12);
0155     spin_unlock_irqrestore(&efx->biu_lock, flags);
0156
0157     netif_vdbg(efx, hw, efx->net_dev,
0158            "read from register %x, got " EF4_OWORD_FMT "\n", reg,
0159            EF4_OWORD_VAL(*value));
0160 }
0161
0162 /* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
0163 static inline void ef4_sram_readq(struct ef4_nic *efx, void __iomem *membase,
0164                   ef4_qword_t *value, unsigned int index)
0165 {
0166     unsigned int addr = index * sizeof(*value);
0167     unsigned long flags __attribute__ ((unused));
0168
0169     spin_lock_irqsave(&efx->biu_lock, flags);
0170 #ifdef EF4_USE_QWORD_IO
0171     value->u64[0] = (__force __le64)__raw_readq(membase + addr);
0172 #else
0173     value->u32[0] = (__force __le32)__raw_readl(membase + addr);
0174     value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
0175 #endif
0176     spin_unlock_irqrestore(&efx->biu_lock, flags);
0177
0178     netif_vdbg(efx, hw, efx->net_dev,
0179            "read from SRAM address %x, got "EF4_QWORD_FMT"\n",
0180            addr, EF4_QWORD_VAL(*value));
0181 }
0182
0183 /* Read a 32-bit CSR or SRAM */
0184 static inline void ef4_readd(struct ef4_nic *efx, ef4_dword_t *value,
0185                 unsigned int reg)
0186 {
0187     value->u32[0] = _ef4_readd(efx, reg);
0188     netif_vdbg(efx, hw, efx->net_dev,
0189            "read from register %x, got "EF4_DWORD_FMT"\n",
0190            reg, EF4_DWORD_VAL(*value));
0191 }
0192
0193 /* Write a 128-bit CSR forming part of a table */
0194 static inline void
0195 ef4_writeo_table(struct ef4_nic *efx, const ef4_oword_t *value,
0196          unsigned int reg, unsigned int index)
0197 {
0198     ef4_writeo(efx, value, reg + index * sizeof(ef4_oword_t));
0199 }
0200
0201 /* Read a 128-bit CSR forming part of a table */
0202 static inline void ef4_reado_table(struct ef4_nic *efx, ef4_oword_t *value,
0203                      unsigned int reg, unsigned int index)
0204 {
0205     ef4_reado(efx, value, reg + index * sizeof(ef4_oword_t));
0206 }
0207
0208 /* Page size used as step between per-VI registers */
0209 #define EF4_VI_PAGE_SIZE 0x2000
0210
0211 /* Calculate offset to page-mapped register */
0212 #define EF4_PAGED_REG(page, reg) \
0213     ((page) * EF4_VI_PAGE_SIZE + (reg))
0214
0215 /* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
0216 static inline void _ef4_writeo_page(struct ef4_nic *efx, ef4_oword_t *value,
0217                     unsigned int reg, unsigned int page)
0218 {
0219     reg = EF4_PAGED_REG(page, reg);
0220
0221     netif_vdbg(efx, hw, efx->net_dev,
0222            "writing register %x with " EF4_OWORD_FMT "\n", reg,
0223            EF4_OWORD_VAL(*value));
0224
0225 #ifdef EF4_USE_QWORD_IO
0226     _ef4_writeq(efx, value->u64[0], reg + 0);
0227     _ef4_writeq(efx, value->u64[1], reg + 8);
0228 #else
0229     _ef4_writed(efx, value->u32[0], reg + 0);
0230     _ef4_writed(efx, value->u32[1], reg + 4);
0231     _ef4_writed(efx, value->u32[2], reg + 8);
0232     _ef4_writed(efx, value->u32[3], reg + 12);
0233 #endif
0234 }
0235 #define ef4_writeo_page(efx, value, reg, page)              \
0236     _ef4_writeo_page(efx, value,                    \
0237              reg +                      \
0238              BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
0239              page)
0240
0241 /* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the
0242  * high bits of RX_DESC_UPD or TX_DESC_UPD)
0243  */
0244 static inline void
0245 _ef4_writed_page(struct ef4_nic *efx, const ef4_dword_t *value,
0246          unsigned int reg, unsigned int page)
0247 {
0248     ef4_writed(efx, value, EF4_PAGED_REG(page, reg));
0249 }
0250 #define ef4_writed_page(efx, value, reg, page)              \
0251     _ef4_writed_page(efx, value,                    \
0252              reg +                      \
0253              BUILD_BUG_ON_ZERO((reg) != 0x400 &&        \
0254                        (reg) != 0x420 &&        \
0255                        (reg) != 0x830 &&        \
0256                        (reg) != 0x83c &&        \
0257                        (reg) != 0xa18 &&        \
0258                        (reg) != 0xa1c),     \
0259              page)
0260
0261 /* Write TIMER_COMMAND.  This is a page-mapped 32-bit CSR, but a bug
0262  * in the BIU means that writes to TIMER_COMMAND[0] invalidate the
0263  * collector register.
0264  */
0265 static inline void _ef4_writed_page_locked(struct ef4_nic *efx,
0266                        const ef4_dword_t *value,
0267                        unsigned int reg,
0268                        unsigned int page)
0269 {
0270     unsigned long flags __attribute__ ((unused));
0271
0272     if (page == 0) {
0273         spin_lock_irqsave(&efx->biu_lock, flags);
0274         ef4_writed(efx, value, EF4_PAGED_REG(page, reg));
0275         spin_unlock_irqrestore(&efx->biu_lock, flags);
0276     } else {
0277         ef4_writed(efx, value, EF4_PAGED_REG(page, reg));
0278     }
0279 }
0280 #define ef4_writed_page_locked(efx, value, reg, page)           \
0281     _ef4_writed_page_locked(efx, value,             \
0282                 reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
0283                 page)
0284
0285 #endif /* EF4_IO_H */