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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /****************************************************************************
0003  * Driver for Solarflare network controllers and boards
0004  * Copyright 2018 Solarflare Communications Inc.
0005  * Copyright 2019-2022 Xilinx Inc.
0006  *
0007  * This program is free software; you can redistribute it and/or modify it
0008  * under the terms of the GNU General Public License version 2 as published
0009  * by the Free Software Foundation, incorporated herein by reference.
0010  */
0011 
0012 #include "ef100_nic.h"
0013 #include "efx_common.h"
0014 #include "efx_channels.h"
0015 #include "io.h"
0016 #include "selftest.h"
0017 #include "ef100_regs.h"
0018 #include "mcdi.h"
0019 #include "mcdi_pcol.h"
0020 #include "mcdi_port_common.h"
0021 #include "mcdi_functions.h"
0022 #include "mcdi_filters.h"
0023 #include "ef100_rx.h"
0024 #include "ef100_tx.h"
0025 #include "ef100_sriov.h"
0026 #include "ef100_netdev.h"
0027 #include "tc.h"
0028 #include "mae.h"
0029 #include "rx_common.h"
0030 
0031 #define EF100_MAX_VIS 4096
0032 #define EF100_NUM_MCDI_BUFFERS  1
0033 #define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX)
0034 
0035 #define EF100_RESET_PORT ((ETH_RESET_MAC | ETH_RESET_PHY) << ETH_RESET_SHARED_SHIFT)
0036 
0037 /*  MCDI
0038  */
0039 static u8 *ef100_mcdi_buf(struct efx_nic *efx, u8 bufid, dma_addr_t *dma_addr)
0040 {
0041     struct ef100_nic_data *nic_data = efx->nic_data;
0042 
0043     if (dma_addr)
0044         *dma_addr = nic_data->mcdi_buf.dma_addr +
0045                 bufid * ALIGN(MCDI_BUF_LEN, 256);
0046     return nic_data->mcdi_buf.addr + bufid * ALIGN(MCDI_BUF_LEN, 256);
0047 }
0048 
0049 static int ef100_get_warm_boot_count(struct efx_nic *efx)
0050 {
0051     efx_dword_t reg;
0052 
0053     efx_readd(efx, &reg, efx_reg(efx, ER_GZ_MC_SFT_STATUS));
0054 
0055     if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) == 0xffffffff) {
0056         netif_err(efx, hw, efx->net_dev, "Hardware unavailable\n");
0057         efx->state = STATE_DISABLED;
0058         return -ENETDOWN;
0059     } else {
0060         return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
0061             EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
0062     }
0063 }
0064 
0065 static void ef100_mcdi_request(struct efx_nic *efx,
0066                    const efx_dword_t *hdr, size_t hdr_len,
0067                    const efx_dword_t *sdu, size_t sdu_len)
0068 {
0069     dma_addr_t dma_addr;
0070     u8 *pdu = ef100_mcdi_buf(efx, 0, &dma_addr);
0071 
0072     memcpy(pdu, hdr, hdr_len);
0073     memcpy(pdu + hdr_len, sdu, sdu_len);
0074     wmb();
0075 
0076     /* The hardware provides 'low' and 'high' (doorbell) registers
0077      * for passing the 64-bit address of an MCDI request to
0078      * firmware.  However the dwords are swapped by firmware.  The
0079      * least significant bits of the doorbell are then 0 for all
0080      * MCDI requests due to alignment.
0081      */
0082     _efx_writed(efx, cpu_to_le32((u64)dma_addr >> 32),  efx_reg(efx, ER_GZ_MC_DB_LWRD));
0083     _efx_writed(efx, cpu_to_le32((u32)dma_addr),  efx_reg(efx, ER_GZ_MC_DB_HWRD));
0084 }
0085 
0086 static bool ef100_mcdi_poll_response(struct efx_nic *efx)
0087 {
0088     const efx_dword_t hdr =
0089         *(const efx_dword_t *)(ef100_mcdi_buf(efx, 0, NULL));
0090 
0091     rmb();
0092     return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
0093 }
0094 
0095 static void ef100_mcdi_read_response(struct efx_nic *efx,
0096                      efx_dword_t *outbuf, size_t offset,
0097                      size_t outlen)
0098 {
0099     const u8 *pdu = ef100_mcdi_buf(efx, 0, NULL);
0100 
0101     memcpy(outbuf, pdu + offset, outlen);
0102 }
0103 
0104 static int ef100_mcdi_poll_reboot(struct efx_nic *efx)
0105 {
0106     struct ef100_nic_data *nic_data = efx->nic_data;
0107     int rc;
0108 
0109     rc = ef100_get_warm_boot_count(efx);
0110     if (rc < 0) {
0111         /* The firmware is presumably in the process of
0112          * rebooting.  However, we are supposed to report each
0113          * reboot just once, so we must only do that once we
0114          * can read and store the updated warm boot count.
0115          */
0116         return 0;
0117     }
0118 
0119     if (rc == nic_data->warm_boot_count)
0120         return 0;
0121 
0122     nic_data->warm_boot_count = rc;
0123 
0124     return -EIO;
0125 }
0126 
0127 static void ef100_mcdi_reboot_detected(struct efx_nic *efx)
0128 {
0129 }
0130 
0131 /*  MCDI calls
0132  */
0133 static int ef100_get_mac_address(struct efx_nic *efx, u8 *mac_address)
0134 {
0135     MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
0136     size_t outlen;
0137     int rc;
0138 
0139     BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
0140 
0141     rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
0142               outbuf, sizeof(outbuf), &outlen);
0143     if (rc)
0144         return rc;
0145     if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
0146         return -EIO;
0147 
0148     ether_addr_copy(mac_address,
0149             MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
0150     return 0;
0151 }
0152 
0153 int efx_ef100_init_datapath_caps(struct efx_nic *efx)
0154 {
0155     MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V7_OUT_LEN);
0156     struct ef100_nic_data *nic_data = efx->nic_data;
0157     u8 vi_window_mode;
0158     size_t outlen;
0159     int rc;
0160 
0161     BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
0162 
0163     rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
0164               outbuf, sizeof(outbuf), &outlen);
0165     if (rc)
0166         return rc;
0167     if (outlen < MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
0168         netif_err(efx, drv, efx->net_dev,
0169               "unable to read datapath firmware capabilities\n");
0170         return -EIO;
0171     }
0172 
0173     nic_data->datapath_caps = MCDI_DWORD(outbuf,
0174                          GET_CAPABILITIES_OUT_FLAGS1);
0175     nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
0176                           GET_CAPABILITIES_V2_OUT_FLAGS2);
0177     if (outlen < MC_CMD_GET_CAPABILITIES_V7_OUT_LEN)
0178         nic_data->datapath_caps3 = 0;
0179     else
0180         nic_data->datapath_caps3 = MCDI_DWORD(outbuf,
0181                               GET_CAPABILITIES_V7_OUT_FLAGS3);
0182 
0183     vi_window_mode = MCDI_BYTE(outbuf,
0184                    GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
0185     rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode);
0186     if (rc)
0187         return rc;
0188 
0189     if (efx_ef100_has_cap(nic_data->datapath_caps2, TX_TSO_V3)) {
0190         struct net_device *net_dev = efx->net_dev;
0191         netdev_features_t tso = NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_PARTIAL |
0192                     NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM |
0193                     NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM;
0194 
0195         net_dev->features |= tso;
0196         net_dev->hw_features |= tso;
0197         net_dev->hw_enc_features |= tso;
0198         /* EF100 HW can only offload outer checksums if they are UDP,
0199          * so for GRE_CSUM we have to use GSO_PARTIAL.
0200          */
0201         net_dev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
0202     }
0203     efx->num_mac_stats = MCDI_WORD(outbuf,
0204                        GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
0205     netif_dbg(efx, probe, efx->net_dev,
0206           "firmware reports num_mac_stats = %u\n",
0207           efx->num_mac_stats);
0208     return 0;
0209 }
0210 
0211 /*  Event handling
0212  */
0213 static int ef100_ev_probe(struct efx_channel *channel)
0214 {
0215     /* Allocate an extra descriptor for the QMDA status completion entry */
0216     return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
0217                     (channel->eventq_mask + 2) *
0218                     sizeof(efx_qword_t),
0219                     GFP_KERNEL);
0220 }
0221 
0222 static int ef100_ev_init(struct efx_channel *channel)
0223 {
0224     struct ef100_nic_data *nic_data = channel->efx->nic_data;
0225 
0226     /* initial phase is 0 */
0227     clear_bit(channel->channel, nic_data->evq_phases);
0228 
0229     return efx_mcdi_ev_init(channel, false, false);
0230 }
0231 
0232 static void ef100_ev_read_ack(struct efx_channel *channel)
0233 {
0234     efx_dword_t evq_prime;
0235 
0236     EFX_POPULATE_DWORD_2(evq_prime,
0237                  ERF_GZ_EVQ_ID, channel->channel,
0238                  ERF_GZ_IDX, channel->eventq_read_ptr &
0239                      channel->eventq_mask);
0240 
0241     efx_writed(channel->efx, &evq_prime,
0242            efx_reg(channel->efx, ER_GZ_EVQ_INT_PRIME));
0243 }
0244 
0245 static int ef100_ev_process(struct efx_channel *channel, int quota)
0246 {
0247     struct efx_nic *efx = channel->efx;
0248     struct ef100_nic_data *nic_data;
0249     bool evq_phase, old_evq_phase;
0250     unsigned int read_ptr;
0251     efx_qword_t *p_event;
0252     int spent = 0;
0253     bool ev_phase;
0254     int ev_type;
0255 
0256     if (unlikely(!channel->enabled))
0257         return 0;
0258 
0259     nic_data = efx->nic_data;
0260     evq_phase = test_bit(channel->channel, nic_data->evq_phases);
0261     old_evq_phase = evq_phase;
0262     read_ptr = channel->eventq_read_ptr;
0263     BUILD_BUG_ON(ESF_GZ_EV_RXPKTS_PHASE_LBN != ESF_GZ_EV_TXCMPL_PHASE_LBN);
0264 
0265     while (spent < quota) {
0266         p_event = efx_event(channel, read_ptr);
0267 
0268         ev_phase = !!EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_PHASE);
0269         if (ev_phase != evq_phase)
0270             break;
0271 
0272         netif_vdbg(efx, drv, efx->net_dev,
0273                "processing event on %d " EFX_QWORD_FMT "\n",
0274                channel->channel, EFX_QWORD_VAL(*p_event));
0275 
0276         ev_type = EFX_QWORD_FIELD(*p_event, ESF_GZ_E_TYPE);
0277 
0278         switch (ev_type) {
0279         case ESE_GZ_EF100_EV_RX_PKTS:
0280             efx_ef100_ev_rx(channel, p_event);
0281             ++spent;
0282             break;
0283         case ESE_GZ_EF100_EV_MCDI:
0284             efx_mcdi_process_event(channel, p_event);
0285             break;
0286         case ESE_GZ_EF100_EV_TX_COMPLETION:
0287             ef100_ev_tx(channel, p_event);
0288             break;
0289         case ESE_GZ_EF100_EV_DRIVER:
0290             netif_info(efx, drv, efx->net_dev,
0291                    "Driver initiated event " EFX_QWORD_FMT "\n",
0292                    EFX_QWORD_VAL(*p_event));
0293             break;
0294         default:
0295             netif_info(efx, drv, efx->net_dev,
0296                    "Unhandled event " EFX_QWORD_FMT "\n",
0297                    EFX_QWORD_VAL(*p_event));
0298         }
0299 
0300         ++read_ptr;
0301         if ((read_ptr & channel->eventq_mask) == 0)
0302             evq_phase = !evq_phase;
0303     }
0304 
0305     channel->eventq_read_ptr = read_ptr;
0306     if (evq_phase != old_evq_phase)
0307         change_bit(channel->channel, nic_data->evq_phases);
0308 
0309     return spent;
0310 }
0311 
0312 static irqreturn_t ef100_msi_interrupt(int irq, void *dev_id)
0313 {
0314     struct efx_msi_context *context = dev_id;
0315     struct efx_nic *efx = context->efx;
0316 
0317     netif_vdbg(efx, intr, efx->net_dev,
0318            "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
0319 
0320     if (likely(READ_ONCE(efx->irq_soft_enabled))) {
0321         /* Note test interrupts */
0322         if (context->index == efx->irq_level)
0323             efx->last_irq_cpu = raw_smp_processor_id();
0324 
0325         /* Schedule processing of the channel */
0326         efx_schedule_channel_irq(efx->channel[context->index]);
0327     }
0328 
0329     return IRQ_HANDLED;
0330 }
0331 
0332 int ef100_phy_probe(struct efx_nic *efx)
0333 {
0334     struct efx_mcdi_phy_data *phy_data;
0335     int rc;
0336 
0337     /* Probe for the PHY */
0338     efx->phy_data = kzalloc(sizeof(struct efx_mcdi_phy_data), GFP_KERNEL);
0339     if (!efx->phy_data)
0340         return -ENOMEM;
0341 
0342     rc = efx_mcdi_get_phy_cfg(efx, efx->phy_data);
0343     if (rc)
0344         return rc;
0345 
0346     /* Populate driver and ethtool settings */
0347     phy_data = efx->phy_data;
0348     mcdi_to_ethtool_linkset(phy_data->media, phy_data->supported_cap,
0349                 efx->link_advertising);
0350     efx->fec_config = mcdi_fec_caps_to_ethtool(phy_data->supported_cap,
0351                            false);
0352 
0353     /* Default to Autonegotiated flow control if the PHY supports it */
0354     efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
0355     if (phy_data->supported_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
0356         efx->wanted_fc |= EFX_FC_AUTO;
0357     efx_link_set_wanted_fc(efx, efx->wanted_fc);
0358 
0359     /* Push settings to the PHY. Failure is not fatal, the user can try to
0360      * fix it using ethtool.
0361      */
0362     rc = efx_mcdi_port_reconfigure(efx);
0363     if (rc && rc != -EPERM)
0364         netif_warn(efx, drv, efx->net_dev,
0365                "could not initialise PHY settings\n");
0366 
0367     return 0;
0368 }
0369 
0370 int ef100_filter_table_probe(struct efx_nic *efx)
0371 {
0372     return efx_mcdi_filter_table_probe(efx, true);
0373 }
0374 
0375 static int ef100_filter_table_up(struct efx_nic *efx)
0376 {
0377     int rc;
0378 
0379     down_write(&efx->filter_sem);
0380     rc = efx_mcdi_filter_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
0381     if (rc)
0382         goto fail_unspec;
0383 
0384     rc = efx_mcdi_filter_add_vlan(efx, 0);
0385     if (rc)
0386         goto fail_vlan0;
0387     /* Drop the lock: we've finished altering table existence, and
0388      * filter insertion will need to take the lock for read.
0389      */
0390     up_write(&efx->filter_sem);
0391 #ifdef CONFIG_SFC_SRIOV
0392     rc = efx_tc_insert_rep_filters(efx);
0393     /* Rep filter failure is nonfatal */
0394     if (rc)
0395         netif_warn(efx, drv, efx->net_dev,
0396                "Failed to insert representor filters, rc %d\n",
0397                rc);
0398 #endif
0399     return 0;
0400 
0401 fail_vlan0:
0402     efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
0403 fail_unspec:
0404     efx_mcdi_filter_table_down(efx);
0405     up_write(&efx->filter_sem);
0406     return rc;
0407 }
0408 
0409 static void ef100_filter_table_down(struct efx_nic *efx)
0410 {
0411 #ifdef CONFIG_SFC_SRIOV
0412     efx_tc_remove_rep_filters(efx);
0413 #endif
0414     down_write(&efx->filter_sem);
0415     efx_mcdi_filter_del_vlan(efx, 0);
0416     efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
0417     efx_mcdi_filter_table_down(efx);
0418     up_write(&efx->filter_sem);
0419 }
0420 
0421 /*  Other
0422  */
0423 static int ef100_reconfigure_mac(struct efx_nic *efx, bool mtu_only)
0424 {
0425     WARN_ON(!mutex_is_locked(&efx->mac_lock));
0426 
0427     efx_mcdi_filter_sync_rx_mode(efx);
0428 
0429     if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED))
0430         return efx_mcdi_set_mtu(efx);
0431     return efx_mcdi_set_mac(efx);
0432 }
0433 
0434 static enum reset_type ef100_map_reset_reason(enum reset_type reason)
0435 {
0436     if (reason == RESET_TYPE_TX_WATCHDOG)
0437         return reason;
0438     return RESET_TYPE_DISABLE;
0439 }
0440 
0441 static int ef100_map_reset_flags(u32 *flags)
0442 {
0443     /* Only perform a RESET_TYPE_ALL because we don't support MC_REBOOTs */
0444     if ((*flags & EF100_RESET_PORT)) {
0445         *flags &= ~EF100_RESET_PORT;
0446         return RESET_TYPE_ALL;
0447     }
0448     if (*flags & ETH_RESET_MGMT) {
0449         *flags &= ~ETH_RESET_MGMT;
0450         return RESET_TYPE_DISABLE;
0451     }
0452 
0453     return -EINVAL;
0454 }
0455 
0456 static int ef100_reset(struct efx_nic *efx, enum reset_type reset_type)
0457 {
0458     int rc;
0459 
0460     dev_close(efx->net_dev);
0461 
0462     if (reset_type == RESET_TYPE_TX_WATCHDOG) {
0463         netif_device_attach(efx->net_dev);
0464         __clear_bit(reset_type, &efx->reset_pending);
0465         rc = dev_open(efx->net_dev, NULL);
0466     } else if (reset_type == RESET_TYPE_ALL) {
0467         rc = efx_mcdi_reset(efx, reset_type);
0468         if (rc)
0469             return rc;
0470 
0471         netif_device_attach(efx->net_dev);
0472 
0473         rc = dev_open(efx->net_dev, NULL);
0474     } else {
0475         rc = 1; /* Leave the device closed */
0476     }
0477     return rc;
0478 }
0479 
0480 static void ef100_common_stat_mask(unsigned long *mask)
0481 {
0482     __set_bit(EF100_STAT_port_rx_packets, mask);
0483     __set_bit(EF100_STAT_port_tx_packets, mask);
0484     __set_bit(EF100_STAT_port_rx_bytes, mask);
0485     __set_bit(EF100_STAT_port_tx_bytes, mask);
0486     __set_bit(EF100_STAT_port_rx_multicast, mask);
0487     __set_bit(EF100_STAT_port_rx_bad, mask);
0488     __set_bit(EF100_STAT_port_rx_align_error, mask);
0489     __set_bit(EF100_STAT_port_rx_overflow, mask);
0490 }
0491 
0492 static void ef100_ethtool_stat_mask(unsigned long *mask)
0493 {
0494     __set_bit(EF100_STAT_port_tx_pause, mask);
0495     __set_bit(EF100_STAT_port_tx_unicast, mask);
0496     __set_bit(EF100_STAT_port_tx_multicast, mask);
0497     __set_bit(EF100_STAT_port_tx_broadcast, mask);
0498     __set_bit(EF100_STAT_port_tx_lt64, mask);
0499     __set_bit(EF100_STAT_port_tx_64, mask);
0500     __set_bit(EF100_STAT_port_tx_65_to_127, mask);
0501     __set_bit(EF100_STAT_port_tx_128_to_255, mask);
0502     __set_bit(EF100_STAT_port_tx_256_to_511, mask);
0503     __set_bit(EF100_STAT_port_tx_512_to_1023, mask);
0504     __set_bit(EF100_STAT_port_tx_1024_to_15xx, mask);
0505     __set_bit(EF100_STAT_port_tx_15xx_to_jumbo, mask);
0506     __set_bit(EF100_STAT_port_rx_good, mask);
0507     __set_bit(EF100_STAT_port_rx_pause, mask);
0508     __set_bit(EF100_STAT_port_rx_unicast, mask);
0509     __set_bit(EF100_STAT_port_rx_broadcast, mask);
0510     __set_bit(EF100_STAT_port_rx_lt64, mask);
0511     __set_bit(EF100_STAT_port_rx_64, mask);
0512     __set_bit(EF100_STAT_port_rx_65_to_127, mask);
0513     __set_bit(EF100_STAT_port_rx_128_to_255, mask);
0514     __set_bit(EF100_STAT_port_rx_256_to_511, mask);
0515     __set_bit(EF100_STAT_port_rx_512_to_1023, mask);
0516     __set_bit(EF100_STAT_port_rx_1024_to_15xx, mask);
0517     __set_bit(EF100_STAT_port_rx_15xx_to_jumbo, mask);
0518     __set_bit(EF100_STAT_port_rx_gtjumbo, mask);
0519     __set_bit(EF100_STAT_port_rx_bad_gtjumbo, mask);
0520     __set_bit(EF100_STAT_port_rx_length_error, mask);
0521     __set_bit(EF100_STAT_port_rx_nodesc_drops, mask);
0522     __set_bit(GENERIC_STAT_rx_nodesc_trunc, mask);
0523     __set_bit(GENERIC_STAT_rx_noskb_drops, mask);
0524 }
0525 
0526 #define EF100_DMA_STAT(ext_name, mcdi_name)         \
0527     [EF100_STAT_ ## ext_name] =             \
0528     { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
0529 
0530 static const struct efx_hw_stat_desc ef100_stat_desc[EF100_STAT_COUNT] = {
0531     EF100_DMA_STAT(port_tx_bytes, TX_BYTES),
0532     EF100_DMA_STAT(port_tx_packets, TX_PKTS),
0533     EF100_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
0534     EF100_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
0535     EF100_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
0536     EF100_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
0537     EF100_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
0538     EF100_DMA_STAT(port_tx_64, TX_64_PKTS),
0539     EF100_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
0540     EF100_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
0541     EF100_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
0542     EF100_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
0543     EF100_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
0544     EF100_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
0545     EF100_DMA_STAT(port_rx_bytes, RX_BYTES),
0546     EF100_DMA_STAT(port_rx_packets, RX_PKTS),
0547     EF100_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
0548     EF100_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
0549     EF100_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
0550     EF100_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
0551     EF100_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
0552     EF100_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
0553     EF100_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
0554     EF100_DMA_STAT(port_rx_64, RX_64_PKTS),
0555     EF100_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
0556     EF100_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
0557     EF100_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
0558     EF100_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
0559     EF100_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
0560     EF100_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
0561     EF100_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
0562     EF100_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
0563     EF100_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
0564     EF100_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
0565     EF100_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
0566     EF100_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
0567     EFX_GENERIC_SW_STAT(rx_nodesc_trunc),
0568     EFX_GENERIC_SW_STAT(rx_noskb_drops),
0569 };
0570 
0571 static size_t ef100_describe_stats(struct efx_nic *efx, u8 *names)
0572 {
0573     DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
0574 
0575     ef100_ethtool_stat_mask(mask);
0576     return efx_nic_describe_stats(ef100_stat_desc, EF100_STAT_COUNT,
0577                       mask, names);
0578 }
0579 
0580 static size_t ef100_update_stats_common(struct efx_nic *efx, u64 *full_stats,
0581                     struct rtnl_link_stats64 *core_stats)
0582 {
0583     struct ef100_nic_data *nic_data = efx->nic_data;
0584     DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
0585     size_t stats_count = 0, index;
0586     u64 *stats = nic_data->stats;
0587 
0588     ef100_ethtool_stat_mask(mask);
0589 
0590     if (full_stats) {
0591         for_each_set_bit(index, mask, EF100_STAT_COUNT) {
0592             if (ef100_stat_desc[index].name) {
0593                 *full_stats++ = stats[index];
0594                 ++stats_count;
0595             }
0596         }
0597     }
0598 
0599     if (!core_stats)
0600         return stats_count;
0601 
0602     core_stats->rx_packets = stats[EF100_STAT_port_rx_packets];
0603     core_stats->tx_packets = stats[EF100_STAT_port_tx_packets];
0604     core_stats->rx_bytes = stats[EF100_STAT_port_rx_bytes];
0605     core_stats->tx_bytes = stats[EF100_STAT_port_tx_bytes];
0606     core_stats->rx_dropped = stats[EF100_STAT_port_rx_nodesc_drops] +
0607                  stats[GENERIC_STAT_rx_nodesc_trunc] +
0608                  stats[GENERIC_STAT_rx_noskb_drops];
0609     core_stats->multicast = stats[EF100_STAT_port_rx_multicast];
0610     core_stats->rx_length_errors =
0611             stats[EF100_STAT_port_rx_gtjumbo] +
0612             stats[EF100_STAT_port_rx_length_error];
0613     core_stats->rx_crc_errors = stats[EF100_STAT_port_rx_bad];
0614     core_stats->rx_frame_errors =
0615             stats[EF100_STAT_port_rx_align_error];
0616     core_stats->rx_fifo_errors = stats[EF100_STAT_port_rx_overflow];
0617     core_stats->rx_errors = (core_stats->rx_length_errors +
0618                  core_stats->rx_crc_errors +
0619                  core_stats->rx_frame_errors);
0620 
0621     return stats_count;
0622 }
0623 
0624 static size_t ef100_update_stats(struct efx_nic *efx,
0625                  u64 *full_stats,
0626                  struct rtnl_link_stats64 *core_stats)
0627 {
0628     __le64 *mc_stats = kmalloc(array_size(efx->num_mac_stats, sizeof(__le64)), GFP_ATOMIC);
0629     struct ef100_nic_data *nic_data = efx->nic_data;
0630     DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
0631     u64 *stats = nic_data->stats;
0632 
0633     ef100_common_stat_mask(mask);
0634     ef100_ethtool_stat_mask(mask);
0635 
0636     if (!mc_stats)
0637         return 0;
0638 
0639     efx_nic_copy_stats(efx, mc_stats);
0640     efx_nic_update_stats(ef100_stat_desc, EF100_STAT_COUNT, mask,
0641                  stats, mc_stats, false);
0642 
0643     kfree(mc_stats);
0644 
0645     return ef100_update_stats_common(efx, full_stats, core_stats);
0646 }
0647 
0648 static int efx_ef100_get_phys_port_id(struct efx_nic *efx,
0649                       struct netdev_phys_item_id *ppid)
0650 {
0651     struct ef100_nic_data *nic_data = efx->nic_data;
0652 
0653     if (!is_valid_ether_addr(nic_data->port_id))
0654         return -EOPNOTSUPP;
0655 
0656     ppid->id_len = ETH_ALEN;
0657     memcpy(ppid->id, nic_data->port_id, ppid->id_len);
0658 
0659     return 0;
0660 }
0661 
0662 static int efx_ef100_irq_test_generate(struct efx_nic *efx)
0663 {
0664     MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
0665 
0666     BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
0667 
0668     MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
0669     return efx_mcdi_rpc_quiet(efx, MC_CMD_TRIGGER_INTERRUPT,
0670                   inbuf, sizeof(inbuf), NULL, 0, NULL);
0671 }
0672 
0673 #define EFX_EF100_TEST 1
0674 
0675 static void efx_ef100_ev_test_generate(struct efx_channel *channel)
0676 {
0677     MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
0678     struct efx_nic *efx = channel->efx;
0679     efx_qword_t event;
0680     int rc;
0681 
0682     EFX_POPULATE_QWORD_2(event,
0683                  ESF_GZ_E_TYPE, ESE_GZ_EF100_EV_DRIVER,
0684                  ESF_GZ_DRIVER_DATA, EFX_EF100_TEST);
0685 
0686     MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
0687 
0688     /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
0689      * already swapped the data to little-endian order.
0690      */
0691     memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
0692            sizeof(efx_qword_t));
0693 
0694     rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
0695               NULL, 0, NULL);
0696     if (rc && (rc != -ENETDOWN))
0697         goto fail;
0698 
0699     return;
0700 
0701 fail:
0702     WARN_ON(true);
0703     netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
0704 }
0705 
0706 static unsigned int ef100_check_caps(const struct efx_nic *efx,
0707                      u8 flag, u32 offset)
0708 {
0709     const struct ef100_nic_data *nic_data = efx->nic_data;
0710 
0711     switch (offset) {
0712     case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST:
0713         return nic_data->datapath_caps & BIT_ULL(flag);
0714     case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST:
0715         return nic_data->datapath_caps2 & BIT_ULL(flag);
0716     case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST:
0717         return nic_data->datapath_caps3 & BIT_ULL(flag);
0718     default:
0719         return 0;
0720     }
0721 }
0722 
0723 static unsigned int efx_ef100_recycle_ring_size(const struct efx_nic *efx)
0724 {
0725     /* Maximum link speed for Riverhead is 100G */
0726     return 10 * EFX_RECYCLE_RING_SIZE_10G;
0727 }
0728 
0729 #ifdef CONFIG_SFC_SRIOV
0730 static int efx_ef100_get_base_mport(struct efx_nic *efx)
0731 {
0732     struct ef100_nic_data *nic_data = efx->nic_data;
0733     u32 selector, id;
0734     int rc;
0735 
0736     /* Construct mport selector for "physical network port" */
0737     efx_mae_mport_wire(efx, &selector);
0738     /* Look up actual mport ID */
0739     rc = efx_mae_lookup_mport(efx, selector, &id);
0740     if (rc)
0741         return rc;
0742     /* The ID should always fit in 16 bits, because that's how wide the
0743      * corresponding fields in the RX prefix & TX override descriptor are
0744      */
0745     if (id >> 16)
0746         netif_warn(efx, probe, efx->net_dev, "Bad base m-port id %#x\n",
0747                id);
0748     nic_data->base_mport = id;
0749     nic_data->have_mport = true;
0750     return 0;
0751 }
0752 #endif
0753 
0754 static int compare_versions(const char *a, const char *b)
0755 {
0756     int a_major, a_minor, a_point, a_patch;
0757     int b_major, b_minor, b_point, b_patch;
0758     int a_matched, b_matched;
0759 
0760     a_matched = sscanf(a, "%d.%d.%d.%d", &a_major, &a_minor, &a_point, &a_patch);
0761     b_matched = sscanf(b, "%d.%d.%d.%d", &b_major, &b_minor, &b_point, &b_patch);
0762 
0763     if (a_matched == 4 && b_matched != 4)
0764         return +1;
0765 
0766     if (a_matched != 4 && b_matched == 4)
0767         return -1;
0768 
0769     if (a_matched != 4 && b_matched != 4)
0770         return 0;
0771 
0772     if (a_major != b_major)
0773         return a_major - b_major;
0774 
0775     if (a_minor != b_minor)
0776         return a_minor - b_minor;
0777 
0778     if (a_point != b_point)
0779         return a_point - b_point;
0780 
0781     return a_patch - b_patch;
0782 }
0783 
0784 enum ef100_tlv_state_machine {
0785     EF100_TLV_TYPE,
0786     EF100_TLV_TYPE_CONT,
0787     EF100_TLV_LENGTH,
0788     EF100_TLV_VALUE
0789 };
0790 
0791 struct ef100_tlv_state {
0792     enum ef100_tlv_state_machine state;
0793     u64 value;
0794     u32 value_offset;
0795     u16 type;
0796     u8 len;
0797 };
0798 
0799 static int ef100_tlv_feed(struct ef100_tlv_state *state, u8 byte)
0800 {
0801     switch (state->state) {
0802     case EF100_TLV_TYPE:
0803         state->type = byte & 0x7f;
0804         state->state = (byte & 0x80) ? EF100_TLV_TYPE_CONT
0805                          : EF100_TLV_LENGTH;
0806         /* Clear ready to read in a new entry */
0807         state->value = 0;
0808         state->value_offset = 0;
0809         return 0;
0810     case EF100_TLV_TYPE_CONT:
0811         state->type |= byte << 7;
0812         state->state = EF100_TLV_LENGTH;
0813         return 0;
0814     case EF100_TLV_LENGTH:
0815         state->len = byte;
0816         /* We only handle TLVs that fit in a u64 */
0817         if (state->len > sizeof(state->value))
0818             return -EOPNOTSUPP;
0819         /* len may be zero, implying a value of zero */
0820         state->state = state->len ? EF100_TLV_VALUE : EF100_TLV_TYPE;
0821         return 0;
0822     case EF100_TLV_VALUE:
0823         state->value |= ((u64)byte) << (state->value_offset * 8);
0824         state->value_offset++;
0825         if (state->value_offset >= state->len)
0826             state->state = EF100_TLV_TYPE;
0827         return 0;
0828     default: /* state machine error, can't happen */
0829         WARN_ON_ONCE(1);
0830         return -EIO;
0831     }
0832 }
0833 
0834 static int ef100_process_design_param(struct efx_nic *efx,
0835                       const struct ef100_tlv_state *reader)
0836 {
0837     struct ef100_nic_data *nic_data = efx->nic_data;
0838 
0839     switch (reader->type) {
0840     case ESE_EF100_DP_GZ_PAD: /* padding, skip it */
0841         return 0;
0842     case ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS:
0843         /* Driver doesn't support timestamping yet, so we don't care */
0844         return 0;
0845     case ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS:
0846         /* Driver doesn't support unsolicited-event credits yet, so
0847          * we don't care
0848          */
0849         return 0;
0850     case ESE_EF100_DP_GZ_NMMU_GROUP_SIZE:
0851         /* Driver doesn't manage the NMMU (so we don't care) */
0852         return 0;
0853     case ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS:
0854         /* Driver uses CHECKSUM_COMPLETE, so we don't care about
0855          * protocol checksum validation
0856          */
0857         return 0;
0858     case ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN:
0859         nic_data->tso_max_hdr_len = min_t(u64, reader->value, 0xffff);
0860         return 0;
0861     case ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS:
0862         /* We always put HDR_NUM_SEGS=1 in our TSO descriptors */
0863         if (!reader->value) {
0864             netif_err(efx, probe, efx->net_dev,
0865                   "TSO_MAX_HDR_NUM_SEGS < 1\n");
0866             return -EOPNOTSUPP;
0867         }
0868         return 0;
0869     case ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY:
0870     case ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY:
0871         /* Our TXQ and RXQ sizes are always power-of-two and thus divisible by
0872          * EFX_MIN_DMAQ_SIZE, so we just need to check that
0873          * EFX_MIN_DMAQ_SIZE is divisible by GRANULARITY.
0874          * This is very unlikely to fail.
0875          */
0876         if (!reader->value || reader->value > EFX_MIN_DMAQ_SIZE ||
0877             EFX_MIN_DMAQ_SIZE % (u32)reader->value) {
0878             netif_err(efx, probe, efx->net_dev,
0879                   "%s size granularity is %llu, can't guarantee safety\n",
0880                   reader->type == ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY ? "RXQ" : "TXQ",
0881                   reader->value);
0882             return -EOPNOTSUPP;
0883         }
0884         return 0;
0885     case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN:
0886         nic_data->tso_max_payload_len = min_t(u64, reader->value,
0887                               GSO_LEGACY_MAX_SIZE);
0888         netif_set_tso_max_size(efx->net_dev,
0889                        nic_data->tso_max_payload_len);
0890         return 0;
0891     case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS:
0892         nic_data->tso_max_payload_num_segs = min_t(u64, reader->value, 0xffff);
0893         netif_set_tso_max_segs(efx->net_dev,
0894                        nic_data->tso_max_payload_num_segs);
0895         return 0;
0896     case ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES:
0897         nic_data->tso_max_frames = min_t(u64, reader->value, 0xffff);
0898         return 0;
0899     case ESE_EF100_DP_GZ_COMPAT:
0900         if (reader->value) {
0901             netif_err(efx, probe, efx->net_dev,
0902                   "DP_COMPAT has unknown bits %#llx, driver not compatible with this hw\n",
0903                   reader->value);
0904             return -EOPNOTSUPP;
0905         }
0906         return 0;
0907     case ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN:
0908         /* Driver doesn't use mem2mem transfers */
0909         return 0;
0910     case ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS:
0911         /* Driver doesn't currently use EVQ_TIMER */
0912         return 0;
0913     case ESE_EF100_DP_GZ_NMMU_PAGE_SIZES:
0914         /* Driver doesn't manage the NMMU (so we don't care) */
0915         return 0;
0916     case ESE_EF100_DP_GZ_VI_STRIDES:
0917         /* We never try to set the VI stride, and we don't rely on
0918          * being able to find VIs past VI 0 until after we've learned
0919          * the current stride from MC_CMD_GET_CAPABILITIES.
0920          * So the value of this shouldn't matter.
0921          */
0922         if (reader->value != ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT)
0923             netif_dbg(efx, probe, efx->net_dev,
0924                   "NIC has other than default VI_STRIDES (mask "
0925                   "%#llx), early probing might use wrong one\n",
0926                   reader->value);
0927         return 0;
0928     case ESE_EF100_DP_GZ_RX_MAX_RUNT:
0929         /* Driver doesn't look at L2_STATUS:LEN_ERR bit, so we don't
0930          * care whether it indicates runt or overlength for any given
0931          * packet, so we don't care about this parameter.
0932          */
0933         return 0;
0934     default:
0935         /* Host interface says "Drivers should ignore design parameters
0936          * that they do not recognise."
0937          */
0938         netif_dbg(efx, probe, efx->net_dev,
0939               "Ignoring unrecognised design parameter %u\n",
0940               reader->type);
0941         return 0;
0942     }
0943 }
0944 
0945 static int ef100_check_design_params(struct efx_nic *efx)
0946 {
0947     struct ef100_tlv_state reader = {};
0948     u32 total_len, offset = 0;
0949     efx_dword_t reg;
0950     int rc = 0, i;
0951     u32 data;
0952 
0953     efx_readd(efx, &reg, ER_GZ_PARAMS_TLV_LEN);
0954     total_len = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
0955     pci_dbg(efx->pci_dev, "%u bytes of design parameters\n", total_len);
0956     while (offset < total_len) {
0957         efx_readd(efx, &reg, ER_GZ_PARAMS_TLV + offset);
0958         data = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
0959         for (i = 0; i < sizeof(data); i++) {
0960             rc = ef100_tlv_feed(&reader, data);
0961             /* Got a complete value? */
0962             if (!rc && reader.state == EF100_TLV_TYPE)
0963                 rc = ef100_process_design_param(efx, &reader);
0964             if (rc)
0965                 goto out;
0966             data >>= 8;
0967             offset++;
0968         }
0969     }
0970     /* Check we didn't end halfway through a TLV entry, which could either
0971      * mean that the TLV stream is truncated or just that it's corrupted
0972      * and our state machine is out of sync.
0973      */
0974     if (reader.state != EF100_TLV_TYPE) {
0975         if (reader.state == EF100_TLV_TYPE_CONT)
0976             netif_err(efx, probe, efx->net_dev,
0977                   "truncated design parameter (incomplete type %u)\n",
0978                   reader.type);
0979         else
0980             netif_err(efx, probe, efx->net_dev,
0981                   "truncated design parameter %u\n",
0982                   reader.type);
0983         rc = -EIO;
0984     }
0985 out:
0986     return rc;
0987 }
0988 
0989 /*  NIC probe and remove
0990  */
0991 static int ef100_probe_main(struct efx_nic *efx)
0992 {
0993     unsigned int bar_size = resource_size(&efx->pci_dev->resource[efx->mem_bar]);
0994     struct ef100_nic_data *nic_data;
0995     char fw_version[32];
0996     u32 priv_mask = 0;
0997     int i, rc;
0998 
0999     if (WARN_ON(bar_size == 0))
1000         return -EIO;
1001 
1002     nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1003     if (!nic_data)
1004         return -ENOMEM;
1005     efx->nic_data = nic_data;
1006     nic_data->efx = efx;
1007     efx->max_vis = EF100_MAX_VIS;
1008 
1009     /* Populate design-parameter defaults */
1010     nic_data->tso_max_hdr_len = ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT;
1011     nic_data->tso_max_frames = ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT;
1012     nic_data->tso_max_payload_num_segs = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT;
1013     nic_data->tso_max_payload_len = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT;
1014 
1015     /* Read design parameters */
1016     rc = ef100_check_design_params(efx);
1017     if (rc) {
1018         pci_err(efx->pci_dev, "Unsupported design parameters\n");
1019         goto fail;
1020     }
1021 
1022     /* we assume later that we can copy from this buffer in dwords */
1023     BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
1024 
1025     /* MCDI buffers must be 256 byte aligned. */
1026     rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, MCDI_BUF_LEN,
1027                   GFP_KERNEL);
1028     if (rc)
1029         goto fail;
1030 
1031     /* Get the MC's warm boot count.  In case it's rebooting right
1032      * now, be prepared to retry.
1033      */
1034     i = 0;
1035     for (;;) {
1036         rc = ef100_get_warm_boot_count(efx);
1037         if (rc >= 0)
1038             break;
1039         if (++i == 5)
1040             goto fail;
1041         ssleep(1);
1042     }
1043     nic_data->warm_boot_count = rc;
1044 
1045     /* In case we're recovering from a crash (kexec), we want to
1046      * cancel any outstanding request by the previous user of this
1047      * function.  We send a special message using the least
1048      * significant bits of the 'high' (doorbell) register.
1049      */
1050     _efx_writed(efx, cpu_to_le32(1), efx_reg(efx, ER_GZ_MC_DB_HWRD));
1051 
1052     /* Post-IO section. */
1053 
1054     rc = efx_mcdi_init(efx);
1055     if (rc)
1056         goto fail;
1057     /* Reset (most) configuration for this function */
1058     rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
1059     if (rc)
1060         goto fail;
1061     /* Enable event logging */
1062     rc = efx_mcdi_log_ctrl(efx, true, false, 0);
1063     if (rc)
1064         goto fail;
1065 
1066     rc = efx_get_pf_index(efx, &nic_data->pf_index);
1067     if (rc)
1068         goto fail;
1069 
1070     rc = efx_mcdi_port_get_number(efx);
1071     if (rc < 0)
1072         goto fail;
1073     efx->port_num = rc;
1074 
1075     efx_mcdi_print_fwver(efx, fw_version, sizeof(fw_version));
1076     pci_dbg(efx->pci_dev, "Firmware version %s\n", fw_version);
1077 
1078     rc = efx_mcdi_get_privilege_mask(efx, &priv_mask);
1079     if (rc) /* non-fatal, and priv_mask will still be 0 */
1080         pci_info(efx->pci_dev,
1081              "Failed to get privilege mask from FW, rc %d\n", rc);
1082     nic_data->grp_mae = !!(priv_mask & MC_CMD_PRIVILEGE_MASK_IN_GRP_MAE);
1083 
1084     if (compare_versions(fw_version, "1.1.0.1000") < 0) {
1085         pci_info(efx->pci_dev, "Firmware uses old event descriptors\n");
1086         rc = -EINVAL;
1087         goto fail;
1088     }
1089 
1090     if (efx_has_cap(efx, UNSOL_EV_CREDIT_SUPPORTED)) {
1091         pci_info(efx->pci_dev, "Firmware uses unsolicited-event credits\n");
1092         rc = -EINVAL;
1093         goto fail;
1094     }
1095 
1096     return 0;
1097 fail:
1098     return rc;
1099 }
1100 
1101 int ef100_probe_netdev_pf(struct efx_nic *efx)
1102 {
1103     struct ef100_nic_data *nic_data = efx->nic_data;
1104     struct net_device *net_dev = efx->net_dev;
1105     int rc;
1106 
1107     rc = ef100_get_mac_address(efx, net_dev->perm_addr);
1108     if (rc)
1109         goto fail;
1110     /* Assign MAC address */
1111     eth_hw_addr_set(net_dev, net_dev->perm_addr);
1112     memcpy(nic_data->port_id, net_dev->perm_addr, ETH_ALEN);
1113 
1114     if (!nic_data->grp_mae)
1115         return 0;
1116 
1117 #ifdef CONFIG_SFC_SRIOV
1118     rc = efx_init_struct_tc(efx);
1119     if (rc)
1120         return rc;
1121 
1122     rc = efx_ef100_get_base_mport(efx);
1123     if (rc) {
1124         netif_warn(efx, probe, net_dev,
1125                "Failed to probe base mport rc %d; representors will not function\n",
1126                rc);
1127     }
1128 
1129     rc = efx_init_tc(efx);
1130     if (rc) {
1131         /* Either we don't have an MAE at all (i.e. legacy v-switching),
1132          * or we do but we failed to probe it.  In the latter case, we
1133          * may not have set up default rules, in which case we won't be
1134          * able to pass any traffic.  However, we don't fail the probe,
1135          * because the user might need to use the netdevice to apply
1136          * configuration changes to fix whatever's wrong with the MAE.
1137          */
1138         netif_warn(efx, probe, net_dev, "Failed to probe MAE rc %d\n",
1139                rc);
1140     }
1141 #endif
1142     return 0;
1143 
1144 fail:
1145     return rc;
1146 }
1147 
1148 int ef100_probe_vf(struct efx_nic *efx)
1149 {
1150     return ef100_probe_main(efx);
1151 }
1152 
1153 void ef100_remove(struct efx_nic *efx)
1154 {
1155     struct ef100_nic_data *nic_data = efx->nic_data;
1156 
1157     efx_mcdi_detach(efx);
1158     efx_mcdi_fini(efx);
1159     if (nic_data)
1160         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1161     kfree(nic_data);
1162     efx->nic_data = NULL;
1163 }
1164 
1165 /*  NIC level access functions
1166  */
1167 #define EF100_OFFLOAD_FEATURES  (NETIF_F_HW_CSUM | NETIF_F_RXCSUM | \
1168     NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_NTUPLE | \
1169     NETIF_F_RXHASH | NETIF_F_RXFCS | NETIF_F_TSO_ECN | NETIF_F_RXALL | \
1170     NETIF_F_HW_VLAN_CTAG_TX)
1171 
1172 const struct efx_nic_type ef100_pf_nic_type = {
1173     .revision = EFX_REV_EF100,
1174     .is_vf = false,
1175     .probe = ef100_probe_main,
1176     .offload_features = EF100_OFFLOAD_FEATURES,
1177     .mcdi_max_ver = 2,
1178     .mcdi_request = ef100_mcdi_request,
1179     .mcdi_poll_response = ef100_mcdi_poll_response,
1180     .mcdi_read_response = ef100_mcdi_read_response,
1181     .mcdi_poll_reboot = ef100_mcdi_poll_reboot,
1182     .mcdi_reboot_detected = ef100_mcdi_reboot_detected,
1183     .irq_enable_master = efx_port_dummy_op_void,
1184     .irq_test_generate = efx_ef100_irq_test_generate,
1185     .irq_disable_non_ev = efx_port_dummy_op_void,
1186     .push_irq_moderation = efx_channel_dummy_op_void,
1187     .min_interrupt_mode = EFX_INT_MODE_MSIX,
1188     .map_reset_reason = ef100_map_reset_reason,
1189     .map_reset_flags = ef100_map_reset_flags,
1190     .reset = ef100_reset,
1191 
1192     .check_caps = ef100_check_caps,
1193 
1194     .ev_probe = ef100_ev_probe,
1195     .ev_init = ef100_ev_init,
1196     .ev_fini = efx_mcdi_ev_fini,
1197     .ev_remove = efx_mcdi_ev_remove,
1198     .irq_handle_msi = ef100_msi_interrupt,
1199     .ev_process = ef100_ev_process,
1200     .ev_read_ack = ef100_ev_read_ack,
1201     .ev_test_generate = efx_ef100_ev_test_generate,
1202     .tx_probe = ef100_tx_probe,
1203     .tx_init = ef100_tx_init,
1204     .tx_write = ef100_tx_write,
1205     .tx_enqueue = ef100_enqueue_skb,
1206     .rx_probe = efx_mcdi_rx_probe,
1207     .rx_init = efx_mcdi_rx_init,
1208     .rx_remove = efx_mcdi_rx_remove,
1209     .rx_write = ef100_rx_write,
1210     .rx_packet = __ef100_rx_packet,
1211     .rx_buf_hash_valid = ef100_rx_buf_hash_valid,
1212     .fini_dmaq = efx_fini_dmaq,
1213     .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
1214     .filter_table_probe = ef100_filter_table_up,
1215     .filter_table_restore = efx_mcdi_filter_table_restore,
1216     .filter_table_remove = ef100_filter_table_down,
1217     .filter_insert = efx_mcdi_filter_insert,
1218     .filter_remove_safe = efx_mcdi_filter_remove_safe,
1219     .filter_get_safe = efx_mcdi_filter_get_safe,
1220     .filter_clear_rx = efx_mcdi_filter_clear_rx,
1221     .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
1222     .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
1223     .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
1224 #ifdef CONFIG_RFS_ACCEL
1225     .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
1226 #endif
1227 
1228     .get_phys_port_id = efx_ef100_get_phys_port_id,
1229 
1230     .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
1231     .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
1232     .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
1233     .rx_hash_key_size = 40,
1234     .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
1235     .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
1236     .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config,
1237     .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config,
1238     .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
1239     .rx_recycle_ring_size = efx_ef100_recycle_ring_size,
1240 
1241     .reconfigure_mac = ef100_reconfigure_mac,
1242     .reconfigure_port = efx_mcdi_port_reconfigure,
1243     .test_nvram = efx_new_mcdi_nvram_test_all,
1244     .describe_stats = ef100_describe_stats,
1245     .start_stats = efx_mcdi_mac_start_stats,
1246     .update_stats = ef100_update_stats,
1247     .pull_stats = efx_mcdi_mac_pull_stats,
1248     .stop_stats = efx_mcdi_mac_stop_stats,
1249 #ifdef CONFIG_SFC_SRIOV
1250     .sriov_configure = efx_ef100_sriov_configure,
1251 #endif
1252 
1253     /* Per-type bar/size configuration not used on ef100. Location of
1254      * registers is defined by extended capabilities.
1255      */
1256     .mem_bar = NULL,
1257     .mem_map_size = NULL,
1258 
1259 };
1260 
1261 const struct efx_nic_type ef100_vf_nic_type = {
1262     .revision = EFX_REV_EF100,
1263     .is_vf = true,
1264     .probe = ef100_probe_vf,
1265     .offload_features = EF100_OFFLOAD_FEATURES,
1266     .mcdi_max_ver = 2,
1267     .mcdi_request = ef100_mcdi_request,
1268     .mcdi_poll_response = ef100_mcdi_poll_response,
1269     .mcdi_read_response = ef100_mcdi_read_response,
1270     .mcdi_poll_reboot = ef100_mcdi_poll_reboot,
1271     .mcdi_reboot_detected = ef100_mcdi_reboot_detected,
1272     .irq_enable_master = efx_port_dummy_op_void,
1273     .irq_test_generate = efx_ef100_irq_test_generate,
1274     .irq_disable_non_ev = efx_port_dummy_op_void,
1275     .push_irq_moderation = efx_channel_dummy_op_void,
1276     .min_interrupt_mode = EFX_INT_MODE_MSIX,
1277     .map_reset_reason = ef100_map_reset_reason,
1278     .map_reset_flags = ef100_map_reset_flags,
1279     .reset = ef100_reset,
1280     .check_caps = ef100_check_caps,
1281     .ev_probe = ef100_ev_probe,
1282     .ev_init = ef100_ev_init,
1283     .ev_fini = efx_mcdi_ev_fini,
1284     .ev_remove = efx_mcdi_ev_remove,
1285     .irq_handle_msi = ef100_msi_interrupt,
1286     .ev_process = ef100_ev_process,
1287     .ev_read_ack = ef100_ev_read_ack,
1288     .ev_test_generate = efx_ef100_ev_test_generate,
1289     .tx_probe = ef100_tx_probe,
1290     .tx_init = ef100_tx_init,
1291     .tx_write = ef100_tx_write,
1292     .tx_enqueue = ef100_enqueue_skb,
1293     .rx_probe = efx_mcdi_rx_probe,
1294     .rx_init = efx_mcdi_rx_init,
1295     .rx_remove = efx_mcdi_rx_remove,
1296     .rx_write = ef100_rx_write,
1297     .rx_packet = __ef100_rx_packet,
1298     .rx_buf_hash_valid = ef100_rx_buf_hash_valid,
1299     .fini_dmaq = efx_fini_dmaq,
1300     .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
1301     .filter_table_probe = ef100_filter_table_up,
1302     .filter_table_restore = efx_mcdi_filter_table_restore,
1303     .filter_table_remove = ef100_filter_table_down,
1304     .filter_insert = efx_mcdi_filter_insert,
1305     .filter_remove_safe = efx_mcdi_filter_remove_safe,
1306     .filter_get_safe = efx_mcdi_filter_get_safe,
1307     .filter_clear_rx = efx_mcdi_filter_clear_rx,
1308     .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
1309     .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
1310     .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
1311 #ifdef CONFIG_RFS_ACCEL
1312     .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
1313 #endif
1314 
1315     .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
1316     .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
1317     .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
1318     .rx_hash_key_size = 40,
1319     .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
1320     .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
1321     .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
1322     .rx_recycle_ring_size = efx_ef100_recycle_ring_size,
1323 
1324     .reconfigure_mac = ef100_reconfigure_mac,
1325     .test_nvram = efx_new_mcdi_nvram_test_all,
1326     .describe_stats = ef100_describe_stats,
1327     .start_stats = efx_mcdi_mac_start_stats,
1328     .update_stats = ef100_update_stats,
1329     .pull_stats = efx_mcdi_mac_pull_stats,
1330     .stop_stats = efx_mcdi_mac_stop_stats,
1331 
1332     .mem_bar = NULL,
1333     .mem_map_size = NULL,
1334 
1335 };
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