ethernet/sfc/ef100.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /****************************************************************************
0003  * Driver for Solarflare network controllers and boards
0004  * Copyright 2005-2018 Solarflare Communications Inc.
0005  * Copyright 2019-2022 Xilinx Inc.
0006  *
0007  * This program is free software; you can redistribute it and/or modify it
0008  * under the terms of the GNU General Public License version 2 as published
0009  * by the Free Software Foundation, incorporated herein by reference.
0010  */
0011
0012 #include "net_driver.h"
0013 #include <linux/module.h>
0014 #include <linux/aer.h>
0015 #include "efx_common.h"
0016 #include "efx_channels.h"
0017 #include "io.h"
0018 #include "ef100_nic.h"
0019 #include "ef100_netdev.h"
0020 #include "ef100_sriov.h"
0021 #include "ef100_regs.h"
0022 #include "ef100.h"
0023
0024 #define EFX_EF100_PCI_DEFAULT_BAR   2
0025
0026 /* Number of bytes at start of vendor specified extended capability that indicate
0027  * that the capability is vendor specified. i.e. offset from value returned by
0028  * pci_find_next_ext_capability() to beginning of vendor specified capability
0029  * header.
0030  */
0031 #define PCI_EXT_CAP_HDR_LENGTH  4
0032
0033 /* Expected size of a Xilinx continuation address table entry. */
0034 #define ESE_GZ_CFGBAR_CONT_CAP_MIN_LENGTH      16
0035
0036 struct ef100_func_ctl_window {
0037     bool valid;
0038     unsigned int bar;
0039     u64 offset;
0040 };
0041
0042 static int ef100_pci_walk_xilinx_table(struct efx_nic *efx, u64 offset,
0043                        struct ef100_func_ctl_window *result);
0044
0045 /* Number of bytes to offset when reading bit position x with dword accessors. */
0046 #define ROUND_DOWN_TO_DWORD(x) (((x) & (~31)) >> 3)
0047
0048 #define EXTRACT_BITS(x, lbn, width) \
0049     (((x) >> ((lbn) & 31)) & ((1ull << (width)) - 1))
0050
0051 static u32 _ef100_pci_get_bar_bits_with_width(struct efx_nic *efx,
0052                           int structure_start,
0053                           int lbn, int width)
0054 {
0055     efx_dword_t dword;
0056
0057     efx_readd(efx, &dword, structure_start + ROUND_DOWN_TO_DWORD(lbn));
0058
0059     return EXTRACT_BITS(le32_to_cpu(dword.u32[0]), lbn, width);
0060 }
0061
0062 #define ef100_pci_get_bar_bits(efx, entry_location, bitdef) \
0063     _ef100_pci_get_bar_bits_with_width(efx, entry_location, \
0064         ESF_GZ_CFGBAR_ ## bitdef ## _LBN,       \
0065         ESF_GZ_CFGBAR_ ## bitdef ## _WIDTH)
0066
0067 static int ef100_pci_parse_ef100_entry(struct efx_nic *efx, int entry_location,
0068                        struct ef100_func_ctl_window *result)
0069 {
0070     u64 offset = ef100_pci_get_bar_bits(efx, entry_location, EF100_FUNC_CTL_WIN_OFF) <<
0071                     ESE_GZ_EF100_FUNC_CTL_WIN_OFF_SHIFT;
0072     u32 bar = ef100_pci_get_bar_bits(efx, entry_location, EF100_BAR);
0073
0074     netif_dbg(efx, probe, efx->net_dev,
0075           "Found EF100 function control window bar=%d offset=0x%llx\n",
0076           bar, offset);
0077
0078     if (result->valid) {
0079         netif_err(efx, probe, efx->net_dev,
0080               "Duplicated EF100 table entry.\n");
0081         return -EINVAL;
0082     }
0083
0084     if (bar == ESE_GZ_CFGBAR_EF100_BAR_NUM_EXPANSION_ROM ||
0085         bar == ESE_GZ_CFGBAR_EF100_BAR_NUM_INVALID) {
0086         netif_err(efx, probe, efx->net_dev,
0087               "Bad BAR value of %d in Xilinx capabilities EF100 entry.\n",
0088               bar);
0089         return -EINVAL;
0090     }
0091
0092     result->bar = bar;
0093     result->offset = offset;
0094     result->valid = true;
0095     return 0;
0096 }
0097
0098 static bool ef100_pci_does_bar_overflow(struct efx_nic *efx, int bar,
0099                     u64 next_entry)
0100 {
0101     return next_entry + ESE_GZ_CFGBAR_ENTRY_HEADER_SIZE >
0102                     pci_resource_len(efx->pci_dev, bar);
0103 }
0104
0105 /* Parse a Xilinx capabilities table entry describing a continuation to a new
0106  * sub-table.
0107  */
0108 static int ef100_pci_parse_continue_entry(struct efx_nic *efx, int entry_location,
0109                       struct ef100_func_ctl_window *result)
0110 {
0111     unsigned int previous_bar;
0112     efx_oword_t entry;
0113     u64 offset;
0114     int rc = 0;
0115     u32 bar;
0116
0117     efx_reado(efx, &entry, entry_location);
0118
0119     bar = EFX_OWORD_FIELD32(entry, ESF_GZ_CFGBAR_CONT_CAP_BAR);
0120
0121     offset = EFX_OWORD_FIELD64(entry, ESF_GZ_CFGBAR_CONT_CAP_OFFSET) <<
0122         ESE_GZ_CONT_CAP_OFFSET_BYTES_SHIFT;
0123
0124     previous_bar = efx->mem_bar;
0125
0126     if (bar == ESE_GZ_VSEC_BAR_NUM_EXPANSION_ROM ||
0127         bar == ESE_GZ_VSEC_BAR_NUM_INVALID) {
0128         netif_err(efx, probe, efx->net_dev,
0129               "Bad BAR value of %d in Xilinx capabilities sub-table.\n",
0130               bar);
0131         return -EINVAL;
0132     }
0133
0134     if (bar != previous_bar) {
0135         efx_fini_io(efx);
0136
0137         if (ef100_pci_does_bar_overflow(efx, bar, offset)) {
0138             netif_err(efx, probe, efx->net_dev,
0139                   "Xilinx table will overrun BAR[%d] offset=0x%llx\n",
0140                   bar, offset);
0141             return -EINVAL;
0142         }
0143
0144         /* Temporarily map new BAR. */
0145         rc = efx_init_io(efx, bar,
0146                  (dma_addr_t)DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH),
0147                  pci_resource_len(efx->pci_dev, bar));
0148         if (rc) {
0149             netif_err(efx, probe, efx->net_dev,
0150                   "Mapping new BAR for Xilinx table failed, rc=%d\n", rc);
0151             return rc;
0152         }
0153     }
0154
0155     rc = ef100_pci_walk_xilinx_table(efx, offset, result);
0156     if (rc)
0157         return rc;
0158
0159     if (bar != previous_bar) {
0160         efx_fini_io(efx);
0161
0162         /* Put old BAR back. */
0163         rc = efx_init_io(efx, previous_bar,
0164                  (dma_addr_t)DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH),
0165                  pci_resource_len(efx->pci_dev, previous_bar));
0166         if (rc) {
0167             netif_err(efx, probe, efx->net_dev,
0168                   "Putting old BAR back failed, rc=%d\n", rc);
0169             return rc;
0170         }
0171     }
0172
0173     return 0;
0174 }
0175
0176 /* Iterate over the Xilinx capabilities table in the currently mapped BAR and
0177  * call ef100_pci_parse_ef100_entry() on any EF100 entries and
0178  * ef100_pci_parse_continue_entry() on any table continuations.
0179  */
0180 static int ef100_pci_walk_xilinx_table(struct efx_nic *efx, u64 offset,
0181                        struct ef100_func_ctl_window *result)
0182 {
0183     u64 current_entry = offset;
0184     int rc = 0;
0185
0186     while (true) {
0187         u32 id = ef100_pci_get_bar_bits(efx, current_entry, ENTRY_FORMAT);
0188         u32 last = ef100_pci_get_bar_bits(efx, current_entry, ENTRY_LAST);
0189         u32 rev = ef100_pci_get_bar_bits(efx, current_entry, ENTRY_REV);
0190         u32 entry_size;
0191
0192         if (id == ESE_GZ_CFGBAR_ENTRY_LAST)
0193             return 0;
0194
0195         entry_size = ef100_pci_get_bar_bits(efx, current_entry, ENTRY_SIZE);
0196
0197         netif_dbg(efx, probe, efx->net_dev,
0198               "Seen Xilinx table entry 0x%x size 0x%x at 0x%llx in BAR[%d]\n",
0199               id, entry_size, current_entry, efx->mem_bar);
0200
0201         if (entry_size < sizeof(u32) * 2) {
0202             netif_err(efx, probe, efx->net_dev,
0203                   "Xilinx table entry too short len=0x%x\n", entry_size);
0204             return -EINVAL;
0205         }
0206
0207         switch (id) {
0208         case ESE_GZ_CFGBAR_ENTRY_EF100:
0209             if (rev != ESE_GZ_CFGBAR_ENTRY_REV_EF100 ||
0210                 entry_size < ESE_GZ_CFGBAR_ENTRY_SIZE_EF100) {
0211                 netif_err(efx, probe, efx->net_dev,
0212                       "Bad length or rev for EF100 entry in Xilinx capabilities table. entry_size=%d rev=%d.\n",
0213                       entry_size, rev);
0214                 return -EINVAL;
0215             }
0216
0217             rc = ef100_pci_parse_ef100_entry(efx, current_entry,
0218                              result);
0219             if (rc)
0220                 return rc;
0221             break;
0222         case ESE_GZ_CFGBAR_ENTRY_CONT_CAP_ADDR:
0223             if (rev != 0 || entry_size < ESE_GZ_CFGBAR_CONT_CAP_MIN_LENGTH) {
0224                 netif_err(efx, probe, efx->net_dev,
0225                       "Bad length or rev for continue entry in Xilinx capabilities table. entry_size=%d rev=%d.\n",
0226                       entry_size, rev);
0227                 return -EINVAL;
0228             }
0229
0230             rc = ef100_pci_parse_continue_entry(efx, current_entry, result);
0231             if (rc)
0232                 return rc;
0233             break;
0234         default:
0235             /* Ignore unknown table entries. */
0236             break;
0237         }
0238
0239         if (last)
0240             return 0;
0241
0242         current_entry += entry_size;
0243
0244         if (ef100_pci_does_bar_overflow(efx, efx->mem_bar, current_entry)) {
0245             netif_err(efx, probe, efx->net_dev,
0246                   "Xilinx table overrun at position=0x%llx.\n",
0247                   current_entry);
0248             return -EINVAL;
0249         }
0250     }
0251 }
0252
0253 static int _ef100_pci_get_config_bits_with_width(struct efx_nic *efx,
0254                          int structure_start, int lbn,
0255                          int width, u32 *result)
0256 {
0257     int rc, pos = structure_start + ROUND_DOWN_TO_DWORD(lbn);
0258     u32 temp;
0259
0260     rc = pci_read_config_dword(efx->pci_dev, pos, &temp);
0261     if (rc) {
0262         netif_err(efx, probe, efx->net_dev,
0263               "Failed to read PCI config dword at %d\n",
0264               pos);
0265         return rc;
0266     }
0267
0268     *result = EXTRACT_BITS(temp, lbn, width);
0269
0270     return 0;
0271 }
0272
0273 #define ef100_pci_get_config_bits(efx, entry_location, bitdef, result)  \
0274     _ef100_pci_get_config_bits_with_width(efx, entry_location,  \
0275          ESF_GZ_VSEC_ ## bitdef ## _LBN,            \
0276          ESF_GZ_VSEC_ ## bitdef ## _WIDTH, result)
0277
0278 /* Call ef100_pci_walk_xilinx_table() for the Xilinx capabilities table pointed
0279  * to by this PCI_EXT_CAP_ID_VNDR.
0280  */
0281 static int ef100_pci_parse_xilinx_cap(struct efx_nic *efx, int vndr_cap,
0282                       bool has_offset_hi,
0283                       struct ef100_func_ctl_window *result)
0284 {
0285     u32 offset_high = 0;
0286     u32 offset_lo = 0;
0287     u64 offset = 0;
0288     u32 bar = 0;
0289     int rc = 0;
0290
0291     rc = ef100_pci_get_config_bits(efx, vndr_cap, TBL_BAR, &bar);
0292     if (rc) {
0293         netif_err(efx, probe, efx->net_dev,
0294               "Failed to read ESF_GZ_VSEC_TBL_BAR, rc=%d\n",
0295               rc);
0296         return rc;
0297     }
0298
0299     if (bar == ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_EXPANSION_ROM ||
0300         bar == ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_INVALID) {
0301         netif_err(efx, probe, efx->net_dev,
0302               "Bad BAR value of %d in Xilinx capabilities sub-table.\n",
0303               bar);
0304         return -EINVAL;
0305     }
0306
0307     rc = ef100_pci_get_config_bits(efx, vndr_cap, TBL_OFF_LO, &offset_lo);
0308     if (rc) {
0309         netif_err(efx, probe, efx->net_dev,
0310               "Failed to read ESF_GZ_VSEC_TBL_OFF_LO, rc=%d\n",
0311               rc);
0312         return rc;
0313     }
0314
0315     /* Get optional extension to 64bit offset. */
0316     if (has_offset_hi) {
0317         rc = ef100_pci_get_config_bits(efx, vndr_cap, TBL_OFF_HI, &offset_high);
0318         if (rc) {
0319             netif_err(efx, probe, efx->net_dev,
0320                   "Failed to read ESF_GZ_VSEC_TBL_OFF_HI, rc=%d\n",
0321                   rc);
0322             return rc;
0323         }
0324     }
0325
0326     offset = (((u64)offset_lo) << ESE_GZ_VSEC_TBL_OFF_LO_BYTES_SHIFT) |
0327          (((u64)offset_high) << ESE_GZ_VSEC_TBL_OFF_HI_BYTES_SHIFT);
0328
0329     if (offset > pci_resource_len(efx->pci_dev, bar) - sizeof(u32) * 2) {
0330         netif_err(efx, probe, efx->net_dev,
0331               "Xilinx table will overrun BAR[%d] offset=0x%llx\n",
0332               bar, offset);
0333         return -EINVAL;
0334     }
0335
0336     /* Temporarily map BAR. */
0337     rc = efx_init_io(efx, bar,
0338              (dma_addr_t)DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH),
0339              pci_resource_len(efx->pci_dev, bar));
0340     if (rc) {
0341         netif_err(efx, probe, efx->net_dev,
0342               "efx_init_io failed, rc=%d\n", rc);
0343         return rc;
0344     }
0345
0346     rc = ef100_pci_walk_xilinx_table(efx, offset, result);
0347
0348     /* Unmap temporarily mapped BAR. */
0349     efx_fini_io(efx);
0350     return rc;
0351 }
0352
0353 /* Call ef100_pci_parse_ef100_entry() for each Xilinx PCI_EXT_CAP_ID_VNDR
0354  * capability.
0355  */
0356 static int ef100_pci_find_func_ctrl_window(struct efx_nic *efx,
0357                        struct ef100_func_ctl_window *result)
0358 {
0359     int num_xilinx_caps = 0;
0360     int cap = 0;
0361
0362     result->valid = false;
0363
0364     while ((cap = pci_find_next_ext_capability(efx->pci_dev, cap, PCI_EXT_CAP_ID_VNDR)) != 0) {
0365         int vndr_cap = cap + PCI_EXT_CAP_HDR_LENGTH;
0366         u32 vsec_ver = 0;
0367         u32 vsec_len = 0;
0368         u32 vsec_id = 0;
0369         int rc = 0;
0370
0371         num_xilinx_caps++;
0372
0373         rc = ef100_pci_get_config_bits(efx, vndr_cap, ID, &vsec_id);
0374         if (rc) {
0375             netif_err(efx, probe, efx->net_dev,
0376                   "Failed to read ESF_GZ_VSEC_ID, rc=%d\n",
0377                   rc);
0378             return rc;
0379         }
0380
0381         rc = ef100_pci_get_config_bits(efx, vndr_cap, VER, &vsec_ver);
0382         if (rc) {
0383             netif_err(efx, probe, efx->net_dev,
0384                   "Failed to read ESF_GZ_VSEC_VER, rc=%d\n",
0385                   rc);
0386             return rc;
0387         }
0388
0389         /* Get length of whole capability - i.e. starting at cap */
0390         rc = ef100_pci_get_config_bits(efx, vndr_cap, LEN, &vsec_len);
0391         if (rc) {
0392             netif_err(efx, probe, efx->net_dev,
0393                   "Failed to read ESF_GZ_VSEC_LEN, rc=%d\n",
0394                   rc);
0395             return rc;
0396         }
0397
0398         if (vsec_id == ESE_GZ_XILINX_VSEC_ID &&
0399             vsec_ver == ESE_GZ_VSEC_VER_XIL_CFGBAR &&
0400             vsec_len >= ESE_GZ_VSEC_LEN_MIN) {
0401             bool has_offset_hi = (vsec_len >= ESE_GZ_VSEC_LEN_HIGH_OFFT);
0402
0403             rc = ef100_pci_parse_xilinx_cap(efx, vndr_cap,
0404                             has_offset_hi, result);
0405             if (rc)
0406                 return rc;
0407         }
0408     }
0409
0410     if (num_xilinx_caps && !result->valid) {
0411         netif_err(efx, probe, efx->net_dev,
0412               "Seen %d Xilinx tables, but no EF100 entry.\n",
0413               num_xilinx_caps);
0414         return -EINVAL;
0415     }
0416
0417     return 0;
0418 }
0419
0420 /* Final NIC shutdown
0421  * This is called only at module unload (or hotplug removal).  A PF can call
0422  * this on its VFs to ensure they are unbound first.
0423  */
0424 static void ef100_pci_remove(struct pci_dev *pci_dev)
0425 {
0426     struct efx_nic *efx = pci_get_drvdata(pci_dev);
0427     struct efx_probe_data *probe_data;
0428
0429     if (!efx)
0430         return;
0431
0432     probe_data = container_of(efx, struct efx_probe_data, efx);
0433     ef100_remove_netdev(probe_data);
0434 #ifdef CONFIG_SFC_SRIOV
0435     efx_fini_struct_tc(efx);
0436 #endif
0437
0438     ef100_remove(efx);
0439     efx_fini_io(efx);
0440
0441     pci_dbg(pci_dev, "shutdown successful\n");
0442
0443     pci_disable_pcie_error_reporting(pci_dev);
0444
0445     pci_set_drvdata(pci_dev, NULL);
0446     efx_fini_struct(efx);
0447     kfree(probe_data);
0448 };
0449
0450 static int ef100_pci_probe(struct pci_dev *pci_dev,
0451                const struct pci_device_id *entry)
0452 {
0453     struct ef100_func_ctl_window fcw = { 0 };
0454     struct efx_probe_data *probe_data;
0455     struct efx_nic *efx;
0456     int rc;
0457
0458     /* Allocate probe data and struct efx_nic */
0459     probe_data = kzalloc(sizeof(*probe_data), GFP_KERNEL);
0460     if (!probe_data)
0461         return -ENOMEM;
0462     probe_data->pci_dev = pci_dev;
0463     efx = &probe_data->efx;
0464
0465     efx->type = (const struct efx_nic_type *)entry->driver_data;
0466
0467     efx->pci_dev = pci_dev;
0468     pci_set_drvdata(pci_dev, efx);
0469     rc = efx_init_struct(efx, pci_dev);
0470     if (rc)
0471         goto fail;
0472
0473     efx->vi_stride = EF100_DEFAULT_VI_STRIDE;
0474     pci_info(pci_dev, "Solarflare EF100 NIC detected\n");
0475
0476     rc = ef100_pci_find_func_ctrl_window(efx, &fcw);
0477     if (rc) {
0478         pci_err(pci_dev,
0479             "Error looking for ef100 function control window, rc=%d\n",
0480             rc);
0481         goto fail;
0482     }
0483
0484     if (!fcw.valid) {
0485         /* Extended capability not found - use defaults. */
0486         fcw.bar = EFX_EF100_PCI_DEFAULT_BAR;
0487         fcw.offset = 0;
0488         fcw.valid = true;
0489     }
0490
0491     if (fcw.offset > pci_resource_len(efx->pci_dev, fcw.bar) - ESE_GZ_FCW_LEN) {
0492         pci_err(pci_dev, "Func control window overruns BAR\n");
0493         rc = -EIO;
0494         goto fail;
0495     }
0496
0497     /* Set up basic I/O (BAR mappings etc) */
0498     rc = efx_init_io(efx, fcw.bar,
0499              (dma_addr_t)DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH),
0500              pci_resource_len(efx->pci_dev, fcw.bar));
0501     if (rc)
0502         goto fail;
0503
0504     efx->reg_base = fcw.offset;
0505
0506     rc = efx->type->probe(efx);
0507     if (rc)
0508         goto fail;
0509
0510     efx->state = STATE_PROBED;
0511     rc = ef100_probe_netdev(probe_data);
0512     if (rc)
0513         goto fail;
0514
0515     pci_dbg(pci_dev, "initialisation successful\n");
0516
0517     return 0;
0518
0519 fail:
0520     ef100_pci_remove(pci_dev);
0521     return rc;
0522 }
0523
0524 #ifdef CONFIG_SFC_SRIOV
0525 static int ef100_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
0526 {
0527     struct efx_nic *efx = pci_get_drvdata(dev);
0528     int rc;
0529
0530     if (efx->type->sriov_configure) {
0531         rc = efx->type->sriov_configure(efx, num_vfs);
0532         if (rc)
0533             return rc;
0534         else
0535             return num_vfs;
0536     }
0537     return -ENOENT;
0538 }
0539 #endif
0540
0541 /* PCI device ID table */
0542 static const struct pci_device_id ef100_pci_table[] = {
0543     {PCI_DEVICE(PCI_VENDOR_ID_XILINX, 0x0100),  /* Riverhead PF */
0544         .driver_data = (unsigned long) &ef100_pf_nic_type },
0545     {PCI_DEVICE(PCI_VENDOR_ID_XILINX, 0x1100),  /* Riverhead VF */
0546         .driver_data = (unsigned long) &ef100_vf_nic_type },
0547     {0}                     /* end of list */
0548 };
0549
0550 struct pci_driver ef100_pci_driver = {
0551     .name           = "sfc_ef100",
0552     .id_table       = ef100_pci_table,
0553     .probe          = ef100_pci_probe,
0554     .remove         = ef100_pci_remove,
0555 #ifdef CONFIG_SFC_SRIOV
0556     .sriov_configure = ef100_pci_sriov_configure,
0557 #endif
0558     .err_handler    = &efx_err_handlers,
0559 };
0560
0561 MODULE_DEVICE_TABLE(pci, ef100_pci_table);