ethernet/seeq/sgiseeq.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * sgiseeq.h: Defines for the Seeq8003 ethernet controller.
0004  *
0005  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
0006  */
0007 #ifndef _SGISEEQ_H
0008 #define _SGISEEQ_H
0009
0010 struct sgiseeq_wregs {
0011     volatile unsigned int multicase_high[2];
0012     volatile unsigned int frame_gap;
0013     volatile unsigned int control;
0014 };
0015
0016 struct sgiseeq_rregs {
0017     volatile unsigned int collision_tx[2];
0018     volatile unsigned int collision_all[2];
0019     volatile unsigned int _unused0;
0020     volatile unsigned int rflags;
0021 };
0022
0023 struct sgiseeq_regs {
0024     union {
0025         volatile unsigned int eth_addr[6];
0026         volatile unsigned int multicast_low[6];
0027         struct sgiseeq_wregs wregs;
0028         struct sgiseeq_rregs rregs;
0029     } rw;
0030     volatile unsigned int rstat;
0031     volatile unsigned int tstat;
0032 };
0033
0034 /* Seeq8003 receive status register */
0035 #define SEEQ_RSTAT_OVERF   0x001 /* Overflow */
0036 #define SEEQ_RSTAT_CERROR  0x002 /* CRC error */
0037 #define SEEQ_RSTAT_DERROR  0x004 /* Dribble error */
0038 #define SEEQ_RSTAT_SFRAME  0x008 /* Short frame */
0039 #define SEEQ_RSTAT_REOF    0x010 /* Received end of frame */
0040 #define SEEQ_RSTAT_FIG     0x020 /* Frame is good */
0041 #define SEEQ_RSTAT_TIMEO   0x040 /* Timeout, or late receive */
0042 #define SEEQ_RSTAT_WHICH   0x080 /* Which status, 1=old 0=new */
0043 #define SEEQ_RSTAT_LITTLE  0x100 /* DMA is done in little endian format */
0044 #define SEEQ_RSTAT_SDMA    0x200 /* DMA has started */
0045 #define SEEQ_RSTAT_ADMA    0x400 /* DMA is active */
0046 #define SEEQ_RSTAT_ROVERF  0x800 /* Receive buffer overflow */
0047
0048 /* Seeq8003 receive command register */
0049 #define SEEQ_RCMD_RDISAB   0x000 /* Disable receiver on the Seeq8003 */
0050 #define SEEQ_RCMD_IOVERF   0x001 /* IRQ on buffer overflows */
0051 #define SEEQ_RCMD_ICRC     0x002 /* IRQ on CRC errors */
0052 #define SEEQ_RCMD_IDRIB    0x004 /* IRQ on dribble errors */
0053 #define SEEQ_RCMD_ISHORT   0x008 /* IRQ on short frames */
0054 #define SEEQ_RCMD_IEOF     0x010 /* IRQ on end of frame */
0055 #define SEEQ_RCMD_IGOOD    0x020 /* IRQ on good frames */
0056 #define SEEQ_RCMD_RANY     0x040 /* Receive any frame */
0057 #define SEEQ_RCMD_RBCAST   0x080 /* Receive broadcasts */
0058 #define SEEQ_RCMD_RBMCAST  0x0c0 /* Receive broadcasts/multicasts */
0059
0060 /* Seeq8003 transmit status register */
0061 #define SEEQ_TSTAT_UFLOW   0x001 /* Transmit buffer underflow */
0062 #define SEEQ_TSTAT_CLS     0x002 /* Collision detected */
0063 #define SEEQ_TSTAT_R16     0x004 /* Did 16 retries to tx a frame */
0064 #define SEEQ_TSTAT_PTRANS  0x008 /* Packet was transmitted ok */
0065 #define SEEQ_TSTAT_LCLS    0x010 /* Late collision occurred */
0066 #define SEEQ_TSTAT_WHICH   0x080 /* Which status, 1=old 0=new */
0067 #define SEEQ_TSTAT_TLE     0x100 /* DMA is done in little endian format */
0068 #define SEEQ_TSTAT_SDMA    0x200 /* DMA has started */
0069 #define SEEQ_TSTAT_ADMA    0x400 /* DMA is active */
0070
0071 /* Seeq8003 transmit command register */
0072 #define SEEQ_TCMD_RB0      0x00 /* Register bank zero w/station addr */
0073 #define SEEQ_TCMD_IUF      0x01 /* IRQ on tx underflow */
0074 #define SEEQ_TCMD_IC       0x02 /* IRQ on collisions */
0075 #define SEEQ_TCMD_I16      0x04 /* IRQ after 16 failed attempts to tx frame */
0076 #define SEEQ_TCMD_IPT      0x08 /* IRQ when packet successfully transmitted */
0077 #define SEEQ_TCMD_RB1      0x20 /* Register bank one w/multi-cast low byte */
0078 #define SEEQ_TCMD_RB2      0x40 /* Register bank two w/multi-cast high byte */
0079
0080 /* Seeq8003 control register */
0081 #define SEEQ_CTRL_XCNT     0x01
0082 #define SEEQ_CTRL_ACCNT    0x02
0083 #define SEEQ_CTRL_SFLAG    0x04
0084 #define SEEQ_CTRL_EMULTI   0x08
0085 #define SEEQ_CTRL_ESHORT   0x10
0086 #define SEEQ_CTRL_ENCARR   0x20
0087
0088 /* Seeq8003 control registers on the SGI Hollywood HPC. */
0089 #define SEEQ_HPIO_P1BITS  0x00000001 /* cycles to stay in P1 phase for PIO */
0090 #define SEEQ_HPIO_P2BITS  0x00000060 /* cycles to stay in P2 phase for PIO */
0091 #define SEEQ_HPIO_P3BITS  0x00000100 /* cycles to stay in P3 phase for PIO */
0092 #define SEEQ_HDMA_D1BITS  0x00000006 /* cycles to stay in D1 phase for DMA */
0093 #define SEEQ_HDMA_D2BITS  0x00000020 /* cycles to stay in D2 phase for DMA */
0094 #define SEEQ_HDMA_D3BITS  0x00000000 /* cycles to stay in D3 phase for DMA */
0095 #define SEEQ_HDMA_TIMEO   0x00030000 /* cycles for DMA timeout */
0096 #define SEEQ_HCTL_NORM    0x00000000 /* Normal operation mode */
0097 #define SEEQ_HCTL_RESET   0x00000001 /* Reset Seeq8003 and HPC interface */
0098 #define SEEQ_HCTL_IPEND   0x00000002 /* IRQ is pending for the chip */
0099 #define SEEQ_HCTL_IPG     0x00001000 /* Inter-packet gap */
0100 #define SEEQ_HCTL_RFIX    0x00002000 /* At rxdc, clear end-of-packet */
0101 #define SEEQ_HCTL_EFIX    0x00004000 /* fixes intr status bit settings */
0102 #define SEEQ_HCTL_IFIX    0x00008000 /* enable startup timeouts */
0103
0104 #endif /* !(_SGISEEQ_H) */