ethernet/seeq/ether3.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  linux/drivers/acorn/net/ether3.h
0004  *
0005  *  Copyright (C) 1995-2000 Russell King
0006  *
0007  *  network driver for Acorn/ANT Ether3 cards
0008  */
0009
0010 #ifndef _LINUX_ether3_H
0011 #define _LINUX_ether3_H
0012
0013 /* use 0 for production, 1 for verification, >2 for debug. debug flags: */
0014 #define DEBUG_TX     2
0015 #define DEBUG_RX     4
0016 #define DEBUG_INT    8
0017 #define DEBUG_IC    16
0018 #ifndef NET_DEBUG
0019 #define NET_DEBUG   0
0020 #endif
0021
0022 #define priv(dev)   ((struct dev_priv *)netdev_priv(dev))
0023
0024 /* Command register definitions & bits */
0025 #define REG_COMMAND     (priv(dev)->seeq + 0x0000)
0026 #define CMD_ENINTDMA        0x0001
0027 #define CMD_ENINTRX     0x0002
0028 #define CMD_ENINTTX     0x0004
0029 #define CMD_ENINTBUFWIN     0x0008
0030 #define CMD_ACKINTDMA       0x0010
0031 #define CMD_ACKINTRX        0x0020
0032 #define CMD_ACKINTTX        0x0040
0033 #define CMD_ACKINTBUFWIN    0x0080
0034 #define CMD_DMAON       0x0100
0035 #define CMD_RXON        0x0200
0036 #define CMD_TXON        0x0400
0037 #define CMD_DMAOFF      0x0800
0038 #define CMD_RXOFF       0x1000
0039 #define CMD_TXOFF       0x2000
0040 #define CMD_FIFOREAD        0x4000
0041 #define CMD_FIFOWRITE       0x8000
0042
0043 /* status register */
0044 #define REG_STATUS      (priv(dev)->seeq + 0x0000)
0045 #define STAT_ENINTSTAT      0x0001
0046 #define STAT_ENINTRX        0x0002
0047 #define STAT_ENINTTX        0x0004
0048 #define STAT_ENINTBUFWIN    0x0008
0049 #define STAT_INTDMA     0x0010
0050 #define STAT_INTRX      0x0020
0051 #define STAT_INTTX      0x0040
0052 #define STAT_INTBUFWIN      0x0080
0053 #define STAT_DMAON      0x0100
0054 #define STAT_RXON       0x0200
0055 #define STAT_TXON       0x0400
0056 #define STAT_FIFOFULL       0x2000
0057 #define STAT_FIFOEMPTY      0x4000
0058 #define STAT_FIFODIR        0x8000
0059
0060 /* configuration register 1 */
0061 #define REG_CONFIG1     (priv(dev)->seeq + 0x0040)
0062 #define CFG1_BUFSELSTAT0    0x0000
0063 #define CFG1_BUFSELSTAT1    0x0001
0064 #define CFG1_BUFSELSTAT2    0x0002
0065 #define CFG1_BUFSELSTAT3    0x0003
0066 #define CFG1_BUFSELSTAT4    0x0004
0067 #define CFG1_BUFSELSTAT5    0x0005
0068 #define CFG1_ADDRPROM       0x0006
0069 #define CFG1_TRANSEND       0x0007
0070 #define CFG1_LOCBUFMEM      0x0008
0071 #define CFG1_INTVECTOR      0x0009
0072 #define CFG1_RECVSPECONLY   0x0000
0073 #define CFG1_RECVSPECBROAD  0x4000
0074 #define CFG1_RECVSPECBRMULTI    0x8000
0075 #define CFG1_RECVPROMISC    0xC000
0076
0077 /* The following aren't in 8004 */
0078 #define CFG1_DMABURSTCONT   0x0000
0079 #define CFG1_DMABURST800NS  0x0010
0080 #define CFG1_DMABURST1600NS 0x0020
0081 #define CFG1_DMABURST3200NS 0x0030
0082 #define CFG1_DMABURST1      0x0000
0083 #define CFG1_DMABURST4      0x0040
0084 #define CFG1_DMABURST8      0x0080
0085 #define CFG1_DMABURST16     0x00C0
0086 #define CFG1_RECVCOMPSTAT0  0x0100
0087 #define CFG1_RECVCOMPSTAT1  0x0200
0088 #define CFG1_RECVCOMPSTAT2  0x0400
0089 #define CFG1_RECVCOMPSTAT3  0x0800
0090 #define CFG1_RECVCOMPSTAT4  0x1000
0091 #define CFG1_RECVCOMPSTAT5  0x2000
0092
0093 /* configuration register 2 */
0094 #define REG_CONFIG2     (priv(dev)->seeq + 0x0080)
0095 #define CFG2_BYTESWAP       0x0001
0096 #define CFG2_ERRENCRC       0x0008
0097 #define CFG2_ERRENDRIBBLE   0x0010
0098 #define CFG2_ERRSHORTFRAME  0x0020
0099 #define CFG2_SLOTSELECT     0x0040
0100 #define CFG2_PREAMSELECT    0x0080
0101 #define CFG2_ADDRLENGTH     0x0100
0102 #define CFG2_RECVCRC        0x0200
0103 #define CFG2_XMITNOCRC      0x0400
0104 #define CFG2_LOOPBACK       0x0800
0105 #define CFG2_CTRLO      0x1000
0106 #define CFG2_RESET      0x8000
0107
0108 #define REG_RECVEND     (priv(dev)->seeq + 0x00c0)
0109
0110 #define REG_BUFWIN      (priv(dev)->seeq + 0x0100)
0111
0112 #define REG_RECVPTR     (priv(dev)->seeq + 0x0140)
0113
0114 #define REG_TRANSMITPTR     (priv(dev)->seeq + 0x0180)
0115
0116 #define REG_DMAADDR     (priv(dev)->seeq + 0x01c0)
0117
0118 /*
0119  * Cards transmit/receive headers
0120  */
0121 #define TX_NEXT         (0xffff)
0122 #define TXHDR_ENBABBLEINT   (1 << 16)
0123 #define TXHDR_ENCOLLISIONINT    (1 << 17)
0124 #define TXHDR_EN16COLLISION (1 << 18)
0125 #define TXHDR_ENSUCCESS     (1 << 19)
0126 #define TXHDR_DATAFOLLOWS   (1 << 21)
0127 #define TXHDR_CHAINCONTINUE (1 << 22)
0128 #define TXHDR_TRANSMIT      (1 << 23)
0129 #define TXSTAT_BABBLED      (1 << 24)
0130 #define TXSTAT_COLLISION    (1 << 25)
0131 #define TXSTAT_16COLLISIONS (1 << 26)
0132 #define TXSTAT_DONE     (1 << 31)
0133
0134 #define RX_NEXT         (0xffff)
0135 #define RXHDR_CHAINCONTINUE (1 << 6)
0136 #define RXHDR_RECEIVE       (1 << 7)
0137 #define RXSTAT_OVERSIZE     (1 << 8)
0138 #define RXSTAT_CRCERROR     (1 << 9)
0139 #define RXSTAT_DRIBBLEERROR (1 << 10)
0140 #define RXSTAT_SHORTPACKET  (1 << 11)
0141 #define RXSTAT_DONE     (1 << 15)
0142
0143
0144 #define TX_START    0x0000
0145 #define TX_END      0x6000
0146 #define RX_START    0x6000
0147 #define RX_LEN      0xA000
0148 #define RX_END      0x10000
0149 /* must be a power of 2 and greater than MAX_TX_BUFFERED */
0150 #define MAX_TXED    16
0151 #define MAX_TX_BUFFERED 10
0152
0153 struct dev_priv {
0154     void __iomem *base;
0155     void __iomem *seeq;
0156     struct {
0157     unsigned int command;
0158     unsigned int config1;
0159     unsigned int config2;
0160     } regs;
0161     unsigned char tx_head;      /* buffer nr to insert next packet   */
0162     unsigned char tx_tail;      /* buffer nr of transmitting packet  */
0163     unsigned int rx_head;       /* address to fetch next packet from     */
0164     struct timer_list timer;
0165     struct net_device *dev;
0166     int broken;             /* 0 = ok, 1 = something went wrong  */
0167 };
0168
0169 struct ether3_data {
0170     const char name[8];
0171     unsigned long base_offset;
0172 };
0173
0174 #endif