ethernet/renesas/sh_eth.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*  SuperH Ethernet device driver
0003  *
0004  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
0005  *  Copyright (C) 2008-2012 Renesas Solutions Corp.
0006  */
0007
0008 #ifndef __SH_ETH_H__
0009 #define __SH_ETH_H__
0010
0011 #define CARDNAME    "sh-eth"
0012 #define TX_TIMEOUT  (5*HZ)
0013 #define TX_RING_SIZE    64  /* Tx ring size */
0014 #define RX_RING_SIZE    64  /* Rx ring size */
0015 #define TX_RING_MIN 64
0016 #define RX_RING_MIN 64
0017 #define TX_RING_MAX 1024
0018 #define RX_RING_MAX 1024
0019 #define PKT_BUF_SZ  1538
0020 #define SH_ETH_TSU_TIMEOUT_MS   500
0021 #define SH_ETH_TSU_CAM_ENTRIES  32
0022
0023 enum {
0024     /* IMPORTANT: To keep ethtool register dump working, add new
0025      * register names immediately before SH_ETH_MAX_REGISTER_OFFSET.
0026      */
0027
0028     /* E-DMAC registers */
0029     EDSR = 0,
0030     EDMR,
0031     EDTRR,
0032     EDRRR,
0033     EESR,
0034     EESIPR,
0035     TDLAR,
0036     TDFAR,
0037     TDFXR,
0038     TDFFR,
0039     RDLAR,
0040     RDFAR,
0041     RDFXR,
0042     RDFFR,
0043     TRSCER,
0044     RMFCR,
0045     TFTR,
0046     FDR,
0047     RMCR,
0048     EDOCR,
0049     TFUCR,
0050     RFOCR,
0051     RMIIMODE,
0052     FCFTR,
0053     RPADIR,
0054     TRIMD,
0055     RBWAR,
0056     TBRAR,
0057
0058     /* Ether registers */
0059     ECMR,
0060     ECSR,
0061     ECSIPR,
0062     PIR,
0063     PSR,
0064     RDMLR,
0065     PIPR,
0066     RFLR,
0067     IPGR,
0068     APR,
0069     MPR,
0070     PFTCR,
0071     PFRCR,
0072     RFCR,
0073     RFCF,
0074     TPAUSER,
0075     TPAUSECR,
0076     BCFR,
0077     BCFRR,
0078     GECMR,
0079     BCULR,
0080     MAHR,
0081     MALR,
0082     TROCR,
0083     CDCR,
0084     LCCR,
0085     CNDCR,
0086     CEFCR,
0087     FRECR,
0088     TSFRCR,
0089     TLFRCR,
0090     CERCR,
0091     CEECR,
0092     MAFCR,
0093     RTRATE,
0094     CSMR,
0095     RMII_MII,
0096
0097     /* TSU Absolute address */
0098     ARSTR,
0099     TSU_CTRST,
0100     TSU_FWEN0,
0101     TSU_FWEN1,
0102     TSU_FCM,
0103     TSU_BSYSL0,
0104     TSU_BSYSL1,
0105     TSU_PRISL0,
0106     TSU_PRISL1,
0107     TSU_FWSL0,
0108     TSU_FWSL1,
0109     TSU_FWSLC,
0110     TSU_QTAG0,          /* Same as TSU_QTAGM0 */
0111     TSU_QTAG1,          /* Same as TSU_QTAGM1 */
0112     TSU_QTAGM0,
0113     TSU_QTAGM1,
0114     TSU_FWSR,
0115     TSU_FWINMK,
0116     TSU_ADQT0,
0117     TSU_ADQT1,
0118     TSU_VTAG0,
0119     TSU_VTAG1,
0120     TSU_ADSBSY,
0121     TSU_TEN,
0122     TSU_POST1,
0123     TSU_POST2,
0124     TSU_POST3,
0125     TSU_POST4,
0126     TSU_ADRH0,
0127     /* TSU_ADR{H,L}{0..31} are assumed to be contiguous */
0128
0129     TXNLCR0,
0130     TXALCR0,
0131     RXNLCR0,
0132     RXALCR0,
0133     FWNLCR0,
0134     FWALCR0,
0135     TXNLCR1,
0136     TXALCR1,
0137     RXNLCR1,
0138     RXALCR1,
0139     FWNLCR1,
0140     FWALCR1,
0141
0142     /* This value must be written at last. */
0143     SH_ETH_MAX_REGISTER_OFFSET,
0144 };
0145
0146 enum {
0147     SH_ETH_REG_GIGABIT,
0148     SH_ETH_REG_FAST_RCAR,
0149     SH_ETH_REG_FAST_SH4,
0150     SH_ETH_REG_FAST_SH3_SH2
0151 };
0152
0153 /* Driver's parameters */
0154 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RENESAS)
0155 #define SH_ETH_RX_ALIGN     32
0156 #else
0157 #define SH_ETH_RX_ALIGN     2
0158 #endif
0159
0160 /* Register's bits
0161  */
0162 /* EDSR : sh7734, sh7757, sh7763, r8a7740, and r7s72100 only */
0163 enum EDSR_BIT {
0164     EDSR_ENT = 0x01, EDSR_ENR = 0x02,
0165 };
0166 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
0167
0168 /* GECMR : sh7734, sh7763 and r8a7740 only */
0169 enum GECMR_BIT {
0170     GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
0171 };
0172
0173 /* EDMR */
0174 enum EDMR_BIT {
0175     EDMR_NBST = 0x80,
0176     EDMR_EL = 0x40, /* Litte endian */
0177     EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
0178     EDMR_SRST_GETHER = 0x03,
0179     EDMR_SRST_ETHER = 0x01,
0180 };
0181
0182 /* EDTRR */
0183 enum EDTRR_BIT {
0184     EDTRR_TRNS_GETHER = 0x03,
0185     EDTRR_TRNS_ETHER = 0x01,
0186 };
0187
0188 /* EDRRR */
0189 enum EDRRR_BIT {
0190     EDRRR_R = 0x01,
0191 };
0192
0193 /* TPAUSER */
0194 enum TPAUSER_BIT {
0195     TPAUSER_TPAUSE = 0x0000ffff,
0196     TPAUSER_UNLIMITED = 0,
0197 };
0198
0199 /* BCFR */
0200 enum BCFR_BIT {
0201     BCFR_RPAUSE = 0x0000ffff,
0202     BCFR_UNLIMITED = 0,
0203 };
0204
0205 /* PIR */
0206 enum PIR_BIT {
0207     PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
0208 };
0209
0210 /* PSR */
0211 enum PSR_BIT { PSR_LMON = 0x01, };
0212
0213 /* EESR */
0214 enum EESR_BIT {
0215     EESR_TWB1   = 0x80000000,
0216     EESR_TWB    = 0x40000000,   /* same as TWB0 */
0217     EESR_TC1    = 0x20000000,
0218     EESR_TUC    = 0x10000000,
0219     EESR_ROC    = 0x08000000,
0220     EESR_TABT   = 0x04000000,
0221     EESR_RABT   = 0x02000000,
0222     EESR_RFRMER = 0x01000000,   /* same as RFCOF */
0223     EESR_ADE    = 0x00800000,
0224     EESR_ECI    = 0x00400000,
0225     EESR_FTC    = 0x00200000,   /* same as TC or TC0 */
0226     EESR_TDE    = 0x00100000,
0227     EESR_TFE    = 0x00080000,   /* same as TFUF */
0228     EESR_FRC    = 0x00040000,   /* same as FR */
0229     EESR_RDE    = 0x00020000,
0230     EESR_RFE    = 0x00010000,
0231     EESR_CND    = 0x00000800,
0232     EESR_DLC    = 0x00000400,
0233     EESR_CD     = 0x00000200,
0234     EESR_TRO    = 0x00000100,
0235     EESR_RMAF   = 0x00000080,
0236     EESR_CEEF   = 0x00000040,
0237     EESR_CELF   = 0x00000020,
0238     EESR_RRF    = 0x00000010,
0239     EESR_RTLF   = 0x00000008,
0240     EESR_RTSF   = 0x00000004,
0241     EESR_PRE    = 0x00000002,
0242     EESR_CERF   = 0x00000001,
0243 };
0244
0245 #define EESR_RX_CHECK       (EESR_FRC  | /* Frame recv */       \
0246                  EESR_RMAF | /* Multicast address recv */ \
0247                  EESR_RRF  | /* Bit frame recv */   \
0248                  EESR_RTLF | /* Long frame recv */  \
0249                  EESR_RTSF | /* Short frame recv */ \
0250                  EESR_PRE  | /* PHY-LSI recv error */   \
0251                  EESR_CERF)  /* Recv frame CRC error */
0252
0253 #define DEFAULT_TX_CHECK    (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
0254                  EESR_TRO)
0255 #define DEFAULT_EESR_ERR_CHECK  (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \
0256                  EESR_RDE | EESR_RFRMER | EESR_ADE | \
0257                  EESR_TFE | EESR_TDE)
0258
0259 /* EESIPR */
0260 enum EESIPR_BIT {
0261     EESIPR_TWB1IP   = 0x80000000,
0262     EESIPR_TWBIP    = 0x40000000,   /* same as TWB0IP */
0263     EESIPR_TC1IP    = 0x20000000,
0264     EESIPR_TUCIP    = 0x10000000,
0265     EESIPR_ROCIP    = 0x08000000,
0266     EESIPR_TABTIP   = 0x04000000,
0267     EESIPR_RABTIP   = 0x02000000,
0268     EESIPR_RFCOFIP  = 0x01000000,
0269     EESIPR_ADEIP    = 0x00800000,
0270     EESIPR_ECIIP    = 0x00400000,
0271     EESIPR_FTCIP    = 0x00200000,   /* same as TC0IP */
0272     EESIPR_TDEIP    = 0x00100000,
0273     EESIPR_TFUFIP   = 0x00080000,
0274     EESIPR_FRIP = 0x00040000,
0275     EESIPR_RDEIP    = 0x00020000,
0276     EESIPR_RFOFIP   = 0x00010000,
0277     EESIPR_CNDIP    = 0x00000800,
0278     EESIPR_DLCIP    = 0x00000400,
0279     EESIPR_CDIP = 0x00000200,
0280     EESIPR_TROIP    = 0x00000100,
0281     EESIPR_RMAFIP   = 0x00000080,
0282     EESIPR_CEEFIP   = 0x00000040,
0283     EESIPR_CELFIP   = 0x00000020,
0284     EESIPR_RRFIP    = 0x00000010,
0285     EESIPR_RTLFIP   = 0x00000008,
0286     EESIPR_RTSFIP   = 0x00000004,
0287     EESIPR_PREIP    = 0x00000002,
0288     EESIPR_CERFIP   = 0x00000001,
0289 };
0290
0291 /* FCFTR */
0292 enum FCFTR_BIT {
0293     FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
0294     FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
0295     FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
0296 };
0297 #define DEFAULT_FIFO_F_D_RFF    (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
0298 #define DEFAULT_FIFO_F_D_RFD    (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
0299
0300 /* RMCR */
0301 enum RMCR_BIT {
0302     RMCR_RNC = 0x00000001,
0303 };
0304
0305 /* ECMR */
0306 enum ECMR_BIT {
0307     ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
0308     ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
0309     ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
0310     ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
0311     ECMR_MPDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
0312     ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
0313     ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
0314 };
0315
0316 /* ECSR */
0317 enum ECSR_BIT {
0318     ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
0319     ECSR_LCHNG = 0x04,
0320     ECSR_MPD = 0x02, ECSR_ICD = 0x01,
0321 };
0322
0323 #define DEFAULT_ECSR_INIT   (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
0324                  ECSR_ICD | ECSIPR_MPDIP)
0325
0326 /* ECSIPR */
0327 enum ECSIPR_BIT {
0328     ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
0329     ECSIPR_LCHNGIP = 0x04,
0330     ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
0331 };
0332
0333 #define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
0334                  ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
0335
0336 /* APR */
0337 enum APR_BIT {
0338     APR_AP = 0x0000ffff,
0339 };
0340
0341 /* MPR */
0342 enum MPR_BIT {
0343     MPR_MP = 0x0000ffff,
0344 };
0345
0346 /* TRSCER */
0347 enum TRSCER_BIT {
0348     TRSCER_CNDCE    = 0x00000800,
0349     TRSCER_DLCCE    = 0x00000400,
0350     TRSCER_CDCE = 0x00000200,
0351     TRSCER_TROCE    = 0x00000100,
0352     TRSCER_RMAFCE   = 0x00000080,
0353     TRSCER_RRFCE    = 0x00000010,
0354     TRSCER_RTLFCE   = 0x00000008,
0355     TRSCER_RTSFCE   = 0x00000004,
0356     TRSCER_PRECE    = 0x00000002,
0357     TRSCER_CERFCE   = 0x00000001,
0358 };
0359
0360 #define DEFAULT_TRSCER_ERR_MASK (TRSCER_RMAFCE | TRSCER_RRFCE | TRSCER_CDCE)
0361
0362 /* RPADIR */
0363 enum RPADIR_BIT {
0364     RPADIR_PADS = 0x1f0000, RPADIR_PADR = 0xffff,
0365 };
0366
0367 /* FDR */
0368 #define DEFAULT_FDR_INIT    0x00000707
0369
0370 /* ARSTR */
0371 enum ARSTR_BIT { ARSTR_ARST = 0x00000001, };
0372
0373 /* TSU_FWEN0 */
0374 enum TSU_FWEN0_BIT {
0375     TSU_FWEN0_0 = 0x00000001,
0376 };
0377
0378 /* TSU_ADSBSY */
0379 enum TSU_ADSBSY_BIT {
0380     TSU_ADSBSY_0 = 0x00000001,
0381 };
0382
0383 /* TSU_TEN */
0384 enum TSU_TEN_BIT {
0385     TSU_TEN_0 = 0x80000000,
0386 };
0387
0388 /* TSU_FWSL0 */
0389 enum TSU_FWSL0_BIT {
0390     TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
0391     TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
0392     TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
0393 };
0394
0395 /* TSU_FWSLC */
0396 enum TSU_FWSLC_BIT {
0397     TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
0398     TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
0399     TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
0400     TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
0401     TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
0402 };
0403
0404 /* TSU_VTAGn */
0405 #define TSU_VTAG_ENABLE     0x80000000
0406 #define TSU_VTAG_VID_MASK   0x00000fff
0407
0408 /* The sh ether Tx buffer descriptors.
0409  * This structure should be 20 bytes.
0410  */
0411 struct sh_eth_txdesc {
0412     u32 status;     /* TD0 */
0413     u32 len;        /* TD1 */
0414     u32 addr;       /* TD2 */
0415     u32 pad0;       /* padding data */
0416 } __aligned(2) __packed;
0417
0418 /* Transmit descriptor 0 bits */
0419 enum TD_STS_BIT {
0420     TD_TACT = 0x80000000,
0421     TD_TDLE = 0x40000000,
0422     TD_TFP1 = 0x20000000,
0423     TD_TFP0 = 0x10000000,
0424     TD_TFE  = 0x08000000,
0425     TD_TWBI = 0x04000000,
0426 };
0427 #define TDF1ST  TD_TFP1
0428 #define TDFEND  TD_TFP0
0429 #define TD_TFP  (TD_TFP1 | TD_TFP0)
0430
0431 /* Transmit descriptor 1 bits */
0432 enum TD_LEN_BIT {
0433     TD_TBL  = 0xffff0000,   /* transmit buffer length */
0434 };
0435
0436 /* The sh ether Rx buffer descriptors.
0437  * This structure should be 20 bytes.
0438  */
0439 struct sh_eth_rxdesc {
0440     u32 status;     /* RD0 */
0441     u32 len;        /* RD1 */
0442     u32 addr;       /* RD2 */
0443     u32 pad0;       /* padding data */
0444 } __aligned(2) __packed;
0445
0446 /* Receive descriptor 0 bits */
0447 enum RD_STS_BIT {
0448     RD_RACT = 0x80000000,
0449     RD_RDLE = 0x40000000,
0450     RD_RFP1 = 0x20000000,
0451     RD_RFP0 = 0x10000000,
0452     RD_RFE  = 0x08000000,
0453     RD_RFS10 = 0x00000200,
0454     RD_RFS9 = 0x00000100,
0455     RD_RFS8 = 0x00000080,
0456     RD_RFS7 = 0x00000040,
0457     RD_RFS6 = 0x00000020,
0458     RD_RFS5 = 0x00000010,
0459     RD_RFS4 = 0x00000008,
0460     RD_RFS3 = 0x00000004,
0461     RD_RFS2 = 0x00000002,
0462     RD_RFS1 = 0x00000001,
0463 };
0464 #define RDF1ST  RD_RFP1
0465 #define RDFEND  RD_RFP0
0466 #define RD_RFP  (RD_RFP1 | RD_RFP0)
0467
0468 /* Receive descriptor 1 bits */
0469 enum RD_LEN_BIT {
0470     RD_RFL  = 0x0000ffff,   /* receive frame  length */
0471     RD_RBL  = 0xffff0000,   /* receive buffer length */
0472 };
0473
0474 /* This structure is used by each CPU dependency handling. */
0475 struct sh_eth_cpu_data {
0476     /* mandatory functions */
0477     int (*soft_reset)(struct net_device *ndev);
0478
0479     /* optional functions */
0480     void (*chip_reset)(struct net_device *ndev);
0481     void (*set_duplex)(struct net_device *ndev);
0482     void (*set_rate)(struct net_device *ndev);
0483
0484     /* mandatory initialize value */
0485     int register_type;
0486     u32 edtrr_trns;
0487     u32 eesipr_value;
0488
0489     /* optional initialize value */
0490     u32 ecsr_value;
0491     u32 ecsipr_value;
0492     u32 fdr_value;
0493     u32 fcftr_value;
0494
0495     /* interrupt checking mask */
0496     u32 tx_check;
0497     u32 eesr_err_check;
0498
0499     /* Error mask */
0500     u32 trscer_err_mask;
0501
0502     /* hardware features */
0503     unsigned long irq_flags; /* IRQ configuration flags */
0504     unsigned no_psr:1;  /* EtherC DOES NOT have PSR */
0505     unsigned apr:1;     /* EtherC has APR */
0506     unsigned mpr:1;     /* EtherC has MPR */
0507     unsigned tpauser:1; /* EtherC has TPAUSER */
0508     unsigned gecmr:1;   /* EtherC has GECMR */
0509     unsigned bculr:1;   /* EtherC has BCULR */
0510     unsigned tsu:1;     /* EtherC has TSU */
0511     unsigned hw_swap:1; /* E-DMAC has DE bit in EDMR */
0512     unsigned nbst:1;    /* E-DMAC has NBST bit in EDMR */
0513     unsigned rpadir:1;  /* E-DMAC has RPADIR */
0514     unsigned no_trimd:1;    /* E-DMAC DOES NOT have TRIMD */
0515     unsigned no_ade:1;  /* E-DMAC DOES NOT have ADE bit in EESR */
0516     unsigned no_xdfar:1;    /* E-DMAC DOES NOT have RDFAR/TDFAR */
0517     unsigned xdfar_rw:1;    /* E-DMAC has writeable RDFAR/TDFAR */
0518     unsigned csmr:1;    /* E-DMAC has CSMR */
0519     unsigned rx_csum:1; /* EtherC has ECMR.RCSC */
0520     unsigned select_mii:1;  /* EtherC has RMII_MII (MII select register) */
0521     unsigned rmiimode:1;    /* EtherC has RMIIMODE register */
0522     unsigned rtrate:1;  /* EtherC has RTRATE register */
0523     unsigned magic:1;   /* EtherC has ECMR.MPDE and ECSR.MPD */
0524     unsigned no_tx_cntrs:1; /* EtherC DOES NOT have TX error counters */
0525     unsigned cexcr:1;   /* EtherC has CERCR/CEECR */
0526     unsigned dual_port:1;   /* Dual EtherC/E-DMAC */
0527 };
0528
0529 struct sh_eth_private {
0530     struct platform_device *pdev;
0531     struct sh_eth_cpu_data *cd;
0532     const u16 *reg_offset;
0533     void __iomem *addr;
0534     void __iomem *tsu_addr;
0535     struct clk *clk;
0536     u32 num_rx_ring;
0537     u32 num_tx_ring;
0538     dma_addr_t rx_desc_dma;
0539     dma_addr_t tx_desc_dma;
0540     struct sh_eth_rxdesc *rx_ring;
0541     struct sh_eth_txdesc *tx_ring;
0542     struct sk_buff **rx_skbuff;
0543     struct sk_buff **tx_skbuff;
0544     spinlock_t lock;        /* Register access lock */
0545     u32 cur_rx, dirty_rx;       /* Producer/consumer ring indices */
0546     u32 cur_tx, dirty_tx;
0547     u32 rx_buf_sz;          /* Based on MTU+slack. */
0548     struct napi_struct napi;
0549     bool irq_enabled;
0550     /* MII transceiver section. */
0551     u32 phy_id;         /* PHY ID */
0552     struct mii_bus *mii_bus;    /* MDIO bus control */
0553     int link;
0554     phy_interface_t phy_interface;
0555     int msg_enable;
0556     int speed;
0557     int duplex;
0558     int port;           /* for TSU */
0559     int vlan_num_ids;       /* for VLAN tag filter */
0560
0561     unsigned no_ether_link:1;
0562     unsigned ether_link_active_low:1;
0563     unsigned is_opened:1;
0564     unsigned wol_enabled:1;
0565 };
0566
0567 #endif  /* #ifndef __SH_ETH_H__ */