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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Renesas Ethernet AVB device driver
0003  *
0004  * Copyright (C) 2014-2015 Renesas Electronics Corporation
0005  * Copyright (C) 2015 Renesas Solutions Corp.
0006  * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
0007  *
0008  * Based on the SuperH Ethernet driver
0009  */
0010 
0011 #ifndef __RAVB_H__
0012 #define __RAVB_H__
0013 
0014 #include <linux/interrupt.h>
0015 #include <linux/io.h>
0016 #include <linux/kernel.h>
0017 #include <linux/mdio-bitbang.h>
0018 #include <linux/netdevice.h>
0019 #include <linux/phy.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/ptp_clock_kernel.h>
0022 
0023 #define BE_TX_RING_SIZE 64  /* TX ring size for Best Effort */
0024 #define BE_RX_RING_SIZE 1024    /* RX ring size for Best Effort */
0025 #define NC_TX_RING_SIZE 64  /* TX ring size for Network Control */
0026 #define NC_RX_RING_SIZE 64  /* RX ring size for Network Control */
0027 #define BE_TX_RING_MIN  64
0028 #define BE_RX_RING_MIN  64
0029 #define BE_TX_RING_MAX  1024
0030 #define BE_RX_RING_MAX  2048
0031 
0032 #define PKT_BUF_SZ  1538
0033 
0034 /* Driver's parameters */
0035 #define RAVB_ALIGN  128
0036 
0037 /* Hardware time stamp */
0038 #define RAVB_TXTSTAMP_VALID 0x00000001  /* TX timestamp valid */
0039 #define RAVB_TXTSTAMP_ENABLED   0x00000010  /* Enable TX timestamping */
0040 
0041 #define RAVB_RXTSTAMP_VALID 0x00000001  /* RX timestamp valid */
0042 #define RAVB_RXTSTAMP_TYPE  0x00000006  /* RX type mask */
0043 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
0044 #define RAVB_RXTSTAMP_TYPE_ALL  0x00000006
0045 #define RAVB_RXTSTAMP_ENABLED   0x00000010  /* Enable RX timestamping */
0046 
0047 enum ravb_reg {
0048     /* AVB-DMAC registers */
0049     CCC = 0x0000,
0050     DBAT    = 0x0004,
0051     DLR = 0x0008,
0052     CSR = 0x000C,
0053     CDAR0   = 0x0010,
0054     CDAR1   = 0x0014,
0055     CDAR2   = 0x0018,
0056     CDAR3   = 0x001C,
0057     CDAR4   = 0x0020,
0058     CDAR5   = 0x0024,
0059     CDAR6   = 0x0028,
0060     CDAR7   = 0x002C,
0061     CDAR8   = 0x0030,
0062     CDAR9   = 0x0034,
0063     CDAR10  = 0x0038,
0064     CDAR11  = 0x003C,
0065     CDAR12  = 0x0040,
0066     CDAR13  = 0x0044,
0067     CDAR14  = 0x0048,
0068     CDAR15  = 0x004C,
0069     CDAR16  = 0x0050,
0070     CDAR17  = 0x0054,
0071     CDAR18  = 0x0058,
0072     CDAR19  = 0x005C,
0073     CDAR20  = 0x0060,
0074     CDAR21  = 0x0064,
0075     ESR = 0x0088,
0076     APSR    = 0x008C,   /* R-Car Gen3 only */
0077     RCR = 0x0090,
0078     RQC0    = 0x0094,
0079     RQC1    = 0x0098,
0080     RQC2    = 0x009C,
0081     RQC3    = 0x00A0,
0082     RQC4    = 0x00A4,
0083     RPC = 0x00B0,
0084     RTC = 0x00B4,   /* R-Car Gen3 and RZ/G2L only */
0085     UFCW    = 0x00BC,
0086     UFCS    = 0x00C0,
0087     UFCV0   = 0x00C4,
0088     UFCV1   = 0x00C8,
0089     UFCV2   = 0x00CC,
0090     UFCV3   = 0x00D0,
0091     UFCV4   = 0x00D4,
0092     UFCD0   = 0x00E0,
0093     UFCD1   = 0x00E4,
0094     UFCD2   = 0x00E8,
0095     UFCD3   = 0x00EC,
0096     UFCD4   = 0x00F0,
0097     SFO = 0x00FC,
0098     SFP0    = 0x0100,
0099     SFP1    = 0x0104,
0100     SFP2    = 0x0108,
0101     SFP3    = 0x010C,
0102     SFP4    = 0x0110,
0103     SFP5    = 0x0114,
0104     SFP6    = 0x0118,
0105     SFP7    = 0x011C,
0106     SFP8    = 0x0120,
0107     SFP9    = 0x0124,
0108     SFP10   = 0x0128,
0109     SFP11   = 0x012C,
0110     SFP12   = 0x0130,
0111     SFP13   = 0x0134,
0112     SFP14   = 0x0138,
0113     SFP15   = 0x013C,
0114     SFP16   = 0x0140,
0115     SFP17   = 0x0144,
0116     SFP18   = 0x0148,
0117     SFP19   = 0x014C,
0118     SFP20   = 0x0150,
0119     SFP21   = 0x0154,
0120     SFP22   = 0x0158,
0121     SFP23   = 0x015C,
0122     SFP24   = 0x0160,
0123     SFP25   = 0x0164,
0124     SFP26   = 0x0168,
0125     SFP27   = 0x016C,
0126     SFP28   = 0x0170,
0127     SFP29   = 0x0174,
0128     SFP30   = 0x0178,
0129     SFP31   = 0x017C,
0130     SFM0    = 0x01C0,
0131     SFM1    = 0x01C4,
0132     TGC = 0x0300,
0133     TCCR    = 0x0304,
0134     TSR = 0x0308,
0135     TFA0    = 0x0310,
0136     TFA1    = 0x0314,
0137     TFA2    = 0x0318,
0138     CIVR0   = 0x0320,
0139     CIVR1   = 0x0324,
0140     CDVR0   = 0x0328,
0141     CDVR1   = 0x032C,
0142     CUL0    = 0x0330,
0143     CUL1    = 0x0334,
0144     CLL0    = 0x0338,
0145     CLL1    = 0x033C,
0146     DIC = 0x0350,
0147     DIS = 0x0354,
0148     EIC = 0x0358,
0149     EIS = 0x035C,
0150     RIC0    = 0x0360,
0151     RIS0    = 0x0364,
0152     RIC1    = 0x0368,
0153     RIS1    = 0x036C,
0154     RIC2    = 0x0370,
0155     RIS2    = 0x0374,
0156     TIC = 0x0378,
0157     TIS = 0x037C,
0158     ISS = 0x0380,
0159     CIE = 0x0384,   /* R-Car Gen3 only */
0160     GCCR    = 0x0390,
0161     GMTT    = 0x0394,
0162     GPTC    = 0x0398,
0163     GTI = 0x039C,
0164     GTO0    = 0x03A0,
0165     GTO1    = 0x03A4,
0166     GTO2    = 0x03A8,
0167     GIC = 0x03AC,
0168     GIS = 0x03B0,
0169     GCPT    = 0x03B4,   /* Documented for R-Car Gen3 only */
0170     GCT0    = 0x03B8,
0171     GCT1    = 0x03BC,
0172     GCT2    = 0x03C0,
0173     GIE = 0x03CC,   /* R-Car Gen3 only */
0174     GID = 0x03D0,   /* R-Car Gen3 only */
0175     DIL = 0x0440,   /* R-Car Gen3 only */
0176     RIE0    = 0x0460,   /* R-Car Gen3 only */
0177     RID0    = 0x0464,   /* R-Car Gen3 only */
0178     RIE2    = 0x0470,   /* R-Car Gen3 only */
0179     RID2    = 0x0474,   /* R-Car Gen3 only */
0180     TIE = 0x0478,   /* R-Car Gen3 only */
0181     TID = 0x047c,   /* R-Car Gen3 only */
0182 
0183     /* E-MAC registers */
0184     ECMR    = 0x0500,
0185     RFLR    = 0x0508,
0186     ECSR    = 0x0510,
0187     ECSIPR  = 0x0518,
0188     PIR = 0x0520,
0189     PSR = 0x0528,
0190     PIPR    = 0x052c,
0191     CXR31   = 0x0530,   /* RZ/G2L only */
0192     MPR = 0x0558,
0193     PFTCR   = 0x055c,
0194     PFRCR   = 0x0560,
0195     GECMR   = 0x05b0,
0196     MAHR    = 0x05c0,
0197     MALR    = 0x05c8,
0198     TROCR   = 0x0700,   /* R-Car Gen3 and RZ/G2L only */
0199     CXR41   = 0x0708,   /* RZ/G2L only */
0200     CXR42   = 0x0710,   /* RZ/G2L only */
0201     CEFCR   = 0x0740,
0202     FRECR   = 0x0748,
0203     TSFRCR  = 0x0750,
0204     TLFRCR  = 0x0758,
0205     RFCR    = 0x0760,
0206     MAFCR   = 0x0778,
0207     CSR0    = 0x0800,   /* RZ/G2L only */
0208 };
0209 
0210 
0211 /* Register bits of the Ethernet AVB */
0212 /* CCC */
0213 enum CCC_BIT {
0214     CCC_OPC     = 0x00000003,
0215     CCC_OPC_RESET   = 0x00000000,
0216     CCC_OPC_CONFIG  = 0x00000001,
0217     CCC_OPC_OPERATION = 0x00000002,
0218     CCC_GAC     = 0x00000080,
0219     CCC_DTSR    = 0x00000100,
0220     CCC_CSEL    = 0x00030000,
0221     CCC_CSEL_HPB    = 0x00010000,
0222     CCC_CSEL_ETH_TX = 0x00020000,
0223     CCC_CSEL_GMII_REF = 0x00030000,
0224     CCC_LBME    = 0x01000000,
0225 };
0226 
0227 /* CSR */
0228 enum CSR_BIT {
0229     CSR_OPS     = 0x0000000F,
0230     CSR_OPS_RESET   = 0x00000001,
0231     CSR_OPS_CONFIG  = 0x00000002,
0232     CSR_OPS_OPERATION = 0x00000004,
0233     CSR_OPS_STANDBY = 0x00000008,   /* Documented for R-Car Gen3 only */
0234     CSR_DTS     = 0x00000100,
0235     CSR_TPO0    = 0x00010000,
0236     CSR_TPO1    = 0x00020000,
0237     CSR_TPO2    = 0x00040000,
0238     CSR_TPO3    = 0x00080000,
0239     CSR_RPO     = 0x00100000,
0240 };
0241 
0242 /* ESR */
0243 enum ESR_BIT {
0244     ESR_EQN     = 0x0000001F,
0245     ESR_ET      = 0x00000F00,
0246     ESR_EIL     = 0x00001000,
0247 };
0248 
0249 /* APSR (R-Car Gen3 only) */
0250 enum APSR_BIT {
0251     APSR_MEMS   = 0x00000002,   /* Undocumented */
0252     APSR_CMSW   = 0x00000010,
0253     APSR_RDM    = 0x00002000,
0254     APSR_TDM    = 0x00004000,
0255 };
0256 
0257 /* RCR */
0258 enum RCR_BIT {
0259     RCR_EFFS    = 0x00000001,
0260     RCR_ENCF    = 0x00000002,
0261     RCR_ESF     = 0x0000000C,
0262     RCR_ETS0    = 0x00000010,
0263     RCR_ETS2    = 0x00000020,
0264     RCR_RFCL    = 0x1FFF0000,
0265 };
0266 
0267 /* RQC0/1/2/3/4 */
0268 enum RQC_BIT {
0269     RQC_RSM0    = 0x00000003,
0270     RQC_UFCC0   = 0x00000030,
0271     RQC_RSM1    = 0x00000300,
0272     RQC_UFCC1   = 0x00003000,
0273     RQC_RSM2    = 0x00030000,
0274     RQC_UFCC2   = 0x00300000,
0275     RQC_RSM3    = 0x03000000,
0276     RQC_UFCC3   = 0x30000000,
0277 };
0278 
0279 /* RPC */
0280 enum RPC_BIT {
0281     RPC_PCNT    = 0x00000700,
0282     RPC_DCNT    = 0x00FF0000,
0283 };
0284 
0285 /* UFCW */
0286 enum UFCW_BIT {
0287     UFCW_WL0    = 0x0000003F,
0288     UFCW_WL1    = 0x00003F00,
0289     UFCW_WL2    = 0x003F0000,
0290     UFCW_WL3    = 0x3F000000,
0291 };
0292 
0293 /* UFCS */
0294 enum UFCS_BIT {
0295     UFCS_SL0    = 0x0000003F,
0296     UFCS_SL1    = 0x00003F00,
0297     UFCS_SL2    = 0x003F0000,
0298     UFCS_SL3    = 0x3F000000,
0299 };
0300 
0301 /* UFCV0/1/2/3/4 */
0302 enum UFCV_BIT {
0303     UFCV_CV0    = 0x0000003F,
0304     UFCV_CV1    = 0x00003F00,
0305     UFCV_CV2    = 0x003F0000,
0306     UFCV_CV3    = 0x3F000000,
0307 };
0308 
0309 /* UFCD0/1/2/3/4 */
0310 enum UFCD_BIT {
0311     UFCD_DV0    = 0x0000003F,
0312     UFCD_DV1    = 0x00003F00,
0313     UFCD_DV2    = 0x003F0000,
0314     UFCD_DV3    = 0x3F000000,
0315 };
0316 
0317 /* SFO */
0318 enum SFO_BIT {
0319     SFO_FBP     = 0x0000003F,
0320 };
0321 
0322 /* RTC */
0323 enum RTC_BIT {
0324     RTC_MFL0    = 0x00000FFF,
0325     RTC_MFL1    = 0x0FFF0000,
0326 };
0327 
0328 /* TGC */
0329 enum TGC_BIT {
0330     TGC_TSM0    = 0x00000001,
0331     TGC_TSM1    = 0x00000002,
0332     TGC_TSM2    = 0x00000004,
0333     TGC_TSM3    = 0x00000008,
0334     TGC_TQP     = 0x00000030,
0335     TGC_TQP_NONAVB  = 0x00000000,
0336     TGC_TQP_AVBMODE1 = 0x00000010,
0337     TGC_TQP_AVBMODE2 = 0x00000030,
0338     TGC_TBD0    = 0x00000300,
0339     TGC_TBD1    = 0x00003000,
0340     TGC_TBD2    = 0x00030000,
0341     TGC_TBD3    = 0x00300000,
0342 };
0343 
0344 /* TCCR */
0345 enum TCCR_BIT {
0346     TCCR_TSRQ0  = 0x00000001,
0347     TCCR_TSRQ1  = 0x00000002,
0348     TCCR_TSRQ2  = 0x00000004,
0349     TCCR_TSRQ3  = 0x00000008,
0350     TCCR_TFEN   = 0x00000100,
0351     TCCR_TFR    = 0x00000200,
0352 };
0353 
0354 /* TSR */
0355 enum TSR_BIT {
0356     TSR_CCS0    = 0x00000003,
0357     TSR_CCS1    = 0x0000000C,
0358     TSR_TFFL    = 0x00000700,
0359 };
0360 
0361 /* TFA2 */
0362 enum TFA2_BIT {
0363     TFA2_TSV    = 0x0000FFFF,
0364     TFA2_TST    = 0x03FF0000,
0365 };
0366 
0367 /* DIC */
0368 enum DIC_BIT {
0369     DIC_DPE1    = 0x00000002,
0370     DIC_DPE2    = 0x00000004,
0371     DIC_DPE3    = 0x00000008,
0372     DIC_DPE4    = 0x00000010,
0373     DIC_DPE5    = 0x00000020,
0374     DIC_DPE6    = 0x00000040,
0375     DIC_DPE7    = 0x00000080,
0376     DIC_DPE8    = 0x00000100,
0377     DIC_DPE9    = 0x00000200,
0378     DIC_DPE10   = 0x00000400,
0379     DIC_DPE11   = 0x00000800,
0380     DIC_DPE12   = 0x00001000,
0381     DIC_DPE13   = 0x00002000,
0382     DIC_DPE14   = 0x00004000,
0383     DIC_DPE15   = 0x00008000,
0384 };
0385 
0386 /* DIS */
0387 enum DIS_BIT {
0388     DIS_DPF1    = 0x00000002,
0389     DIS_DPF2    = 0x00000004,
0390     DIS_DPF3    = 0x00000008,
0391     DIS_DPF4    = 0x00000010,
0392     DIS_DPF5    = 0x00000020,
0393     DIS_DPF6    = 0x00000040,
0394     DIS_DPF7    = 0x00000080,
0395     DIS_DPF8    = 0x00000100,
0396     DIS_DPF9    = 0x00000200,
0397     DIS_DPF10   = 0x00000400,
0398     DIS_DPF11   = 0x00000800,
0399     DIS_DPF12   = 0x00001000,
0400     DIS_DPF13   = 0x00002000,
0401     DIS_DPF14   = 0x00004000,
0402     DIS_DPF15   = 0x00008000,
0403 };
0404 
0405 /* EIC */
0406 enum EIC_BIT {
0407     EIC_MREE    = 0x00000001,
0408     EIC_MTEE    = 0x00000002,
0409     EIC_QEE     = 0x00000004,
0410     EIC_SEE     = 0x00000008,
0411     EIC_CLLE0   = 0x00000010,
0412     EIC_CLLE1   = 0x00000020,
0413     EIC_CULE0   = 0x00000040,
0414     EIC_CULE1   = 0x00000080,
0415     EIC_TFFE    = 0x00000100,
0416 };
0417 
0418 /* EIS */
0419 enum EIS_BIT {
0420     EIS_MREF    = 0x00000001,
0421     EIS_MTEF    = 0x00000002,
0422     EIS_QEF     = 0x00000004,
0423     EIS_SEF     = 0x00000008,
0424     EIS_CLLF0   = 0x00000010,
0425     EIS_CLLF1   = 0x00000020,
0426     EIS_CULF0   = 0x00000040,
0427     EIS_CULF1   = 0x00000080,
0428     EIS_TFFF    = 0x00000100,
0429     EIS_QFS     = 0x00010000,
0430     EIS_RESERVED    = (GENMASK(31, 17) | GENMASK(15, 11)),
0431 };
0432 
0433 /* RIC0 */
0434 enum RIC0_BIT {
0435     RIC0_FRE0   = 0x00000001,
0436     RIC0_FRE1   = 0x00000002,
0437     RIC0_FRE2   = 0x00000004,
0438     RIC0_FRE3   = 0x00000008,
0439     RIC0_FRE4   = 0x00000010,
0440     RIC0_FRE5   = 0x00000020,
0441     RIC0_FRE6   = 0x00000040,
0442     RIC0_FRE7   = 0x00000080,
0443     RIC0_FRE8   = 0x00000100,
0444     RIC0_FRE9   = 0x00000200,
0445     RIC0_FRE10  = 0x00000400,
0446     RIC0_FRE11  = 0x00000800,
0447     RIC0_FRE12  = 0x00001000,
0448     RIC0_FRE13  = 0x00002000,
0449     RIC0_FRE14  = 0x00004000,
0450     RIC0_FRE15  = 0x00008000,
0451     RIC0_FRE16  = 0x00010000,
0452     RIC0_FRE17  = 0x00020000,
0453 };
0454 
0455 /* RIC0 */
0456 enum RIS0_BIT {
0457     RIS0_FRF0   = 0x00000001,
0458     RIS0_FRF1   = 0x00000002,
0459     RIS0_FRF2   = 0x00000004,
0460     RIS0_FRF3   = 0x00000008,
0461     RIS0_FRF4   = 0x00000010,
0462     RIS0_FRF5   = 0x00000020,
0463     RIS0_FRF6   = 0x00000040,
0464     RIS0_FRF7   = 0x00000080,
0465     RIS0_FRF8   = 0x00000100,
0466     RIS0_FRF9   = 0x00000200,
0467     RIS0_FRF10  = 0x00000400,
0468     RIS0_FRF11  = 0x00000800,
0469     RIS0_FRF12  = 0x00001000,
0470     RIS0_FRF13  = 0x00002000,
0471     RIS0_FRF14  = 0x00004000,
0472     RIS0_FRF15  = 0x00008000,
0473     RIS0_FRF16  = 0x00010000,
0474     RIS0_FRF17  = 0x00020000,
0475     RIS0_RESERVED   = GENMASK(31, 18),
0476 };
0477 
0478 /* RIC1 */
0479 enum RIC1_BIT {
0480     RIC1_RFWE   = 0x80000000,
0481 };
0482 
0483 /* RIS1 */
0484 enum RIS1_BIT {
0485     RIS1_RFWF   = 0x80000000,
0486 };
0487 
0488 /* RIC2 */
0489 enum RIC2_BIT {
0490     RIC2_QFE0   = 0x00000001,
0491     RIC2_QFE1   = 0x00000002,
0492     RIC2_QFE2   = 0x00000004,
0493     RIC2_QFE3   = 0x00000008,
0494     RIC2_QFE4   = 0x00000010,
0495     RIC2_QFE5   = 0x00000020,
0496     RIC2_QFE6   = 0x00000040,
0497     RIC2_QFE7   = 0x00000080,
0498     RIC2_QFE8   = 0x00000100,
0499     RIC2_QFE9   = 0x00000200,
0500     RIC2_QFE10  = 0x00000400,
0501     RIC2_QFE11  = 0x00000800,
0502     RIC2_QFE12  = 0x00001000,
0503     RIC2_QFE13  = 0x00002000,
0504     RIC2_QFE14  = 0x00004000,
0505     RIC2_QFE15  = 0x00008000,
0506     RIC2_QFE16  = 0x00010000,
0507     RIC2_QFE17  = 0x00020000,
0508     RIC2_RFFE   = 0x80000000,
0509 };
0510 
0511 /* RIS2 */
0512 enum RIS2_BIT {
0513     RIS2_QFF0   = 0x00000001,
0514     RIS2_QFF1   = 0x00000002,
0515     RIS2_QFF2   = 0x00000004,
0516     RIS2_QFF3   = 0x00000008,
0517     RIS2_QFF4   = 0x00000010,
0518     RIS2_QFF5   = 0x00000020,
0519     RIS2_QFF6   = 0x00000040,
0520     RIS2_QFF7   = 0x00000080,
0521     RIS2_QFF8   = 0x00000100,
0522     RIS2_QFF9   = 0x00000200,
0523     RIS2_QFF10  = 0x00000400,
0524     RIS2_QFF11  = 0x00000800,
0525     RIS2_QFF12  = 0x00001000,
0526     RIS2_QFF13  = 0x00002000,
0527     RIS2_QFF14  = 0x00004000,
0528     RIS2_QFF15  = 0x00008000,
0529     RIS2_QFF16  = 0x00010000,
0530     RIS2_QFF17  = 0x00020000,
0531     RIS2_RFFF   = 0x80000000,
0532     RIS2_RESERVED   = GENMASK(30, 18),
0533 };
0534 
0535 /* TIC */
0536 enum TIC_BIT {
0537     TIC_FTE0    = 0x00000001,   /* Documented for R-Car Gen3 only */
0538     TIC_FTE1    = 0x00000002,   /* Documented for R-Car Gen3 only */
0539     TIC_TFUE    = 0x00000100,
0540     TIC_TFWE    = 0x00000200,
0541 };
0542 
0543 /* TIS */
0544 enum TIS_BIT {
0545     TIS_FTF0    = 0x00000001,   /* Documented for R-Car Gen3 only */
0546     TIS_FTF1    = 0x00000002,   /* Documented for R-Car Gen3 only */
0547     TIS_TFUF    = 0x00000100,
0548     TIS_TFWF    = 0x00000200,
0549     TIS_RESERVED    = (GENMASK(31, 20) | GENMASK(15, 12) | GENMASK(7, 4))
0550 };
0551 
0552 /* ISS */
0553 enum ISS_BIT {
0554     ISS_FRS     = 0x00000001,   /* Documented for R-Car Gen3 only */
0555     ISS_FTS     = 0x00000004,   /* Documented for R-Car Gen3 only */
0556     ISS_ES      = 0x00000040,
0557     ISS_MS      = 0x00000080,
0558     ISS_TFUS    = 0x00000100,
0559     ISS_TFWS    = 0x00000200,
0560     ISS_RFWS    = 0x00001000,
0561     ISS_CGIS    = 0x00002000,
0562     ISS_DPS1    = 0x00020000,
0563     ISS_DPS2    = 0x00040000,
0564     ISS_DPS3    = 0x00080000,
0565     ISS_DPS4    = 0x00100000,
0566     ISS_DPS5    = 0x00200000,
0567     ISS_DPS6    = 0x00400000,
0568     ISS_DPS7    = 0x00800000,
0569     ISS_DPS8    = 0x01000000,
0570     ISS_DPS9    = 0x02000000,
0571     ISS_DPS10   = 0x04000000,
0572     ISS_DPS11   = 0x08000000,
0573     ISS_DPS12   = 0x10000000,
0574     ISS_DPS13   = 0x20000000,
0575     ISS_DPS14   = 0x40000000,
0576     ISS_DPS15   = 0x80000000,
0577 };
0578 
0579 /* CIE (R-Car Gen3 only) */
0580 enum CIE_BIT {
0581     CIE_CRIE    = 0x00000001,
0582     CIE_CTIE    = 0x00000100,
0583     CIE_RQFM    = 0x00010000,
0584     CIE_CL0M    = 0x00020000,
0585     CIE_RFWL    = 0x00040000,
0586     CIE_RFFL    = 0x00080000,
0587 };
0588 
0589 /* GCCR */
0590 enum GCCR_BIT {
0591     GCCR_TCR    = 0x00000003,
0592     GCCR_TCR_NOREQ  = 0x00000000, /* No request */
0593     GCCR_TCR_RESET  = 0x00000001, /* gPTP/AVTP presentation timer reset */
0594     GCCR_TCR_CAPTURE = 0x00000003, /* Capture value set in GCCR.TCSS */
0595     GCCR_LTO    = 0x00000004,
0596     GCCR_LTI    = 0x00000008,
0597     GCCR_LPTC   = 0x00000010,
0598     GCCR_LMTT   = 0x00000020,
0599     GCCR_TCSS   = 0x00000300,
0600     GCCR_TCSS_GPTP  = 0x00000000,   /* gPTP timer value */
0601     GCCR_TCSS_ADJGPTP = 0x00000100, /* Adjusted gPTP timer value */
0602     GCCR_TCSS_AVTP  = 0x00000200,   /* AVTP presentation time value */
0603 };
0604 
0605 /* GTI */
0606 enum GTI_BIT {
0607     GTI_TIV     = 0x0FFFFFFF,
0608 };
0609 
0610 #define GTI_TIV_MAX GTI_TIV
0611 #define GTI_TIV_MIN 0x20
0612 
0613 /* GIC */
0614 enum GIC_BIT {
0615     GIC_PTCE    = 0x00000001,   /* Documented for R-Car Gen3 only */
0616     GIC_PTME    = 0x00000004,
0617 };
0618 
0619 /* GIS */
0620 enum GIS_BIT {
0621     GIS_PTCF    = 0x00000001,   /* Documented for R-Car Gen3 only */
0622     GIS_PTMF    = 0x00000004,
0623     GIS_RESERVED    = GENMASK(15, 10),
0624 };
0625 
0626 /* GIE (R-Car Gen3 only) */
0627 enum GIE_BIT {
0628     GIE_PTCS    = 0x00000001,
0629     GIE_PTOS    = 0x00000002,
0630     GIE_PTMS0   = 0x00000004,
0631     GIE_PTMS1   = 0x00000008,
0632     GIE_PTMS2   = 0x00000010,
0633     GIE_PTMS3   = 0x00000020,
0634     GIE_PTMS4   = 0x00000040,
0635     GIE_PTMS5   = 0x00000080,
0636     GIE_PTMS6   = 0x00000100,
0637     GIE_PTMS7   = 0x00000200,
0638     GIE_ATCS0   = 0x00010000,
0639     GIE_ATCS1   = 0x00020000,
0640     GIE_ATCS2   = 0x00040000,
0641     GIE_ATCS3   = 0x00080000,
0642     GIE_ATCS4   = 0x00100000,
0643     GIE_ATCS5   = 0x00200000,
0644     GIE_ATCS6   = 0x00400000,
0645     GIE_ATCS7   = 0x00800000,
0646     GIE_ATCS8   = 0x01000000,
0647     GIE_ATCS9   = 0x02000000,
0648     GIE_ATCS10  = 0x04000000,
0649     GIE_ATCS11  = 0x08000000,
0650     GIE_ATCS12  = 0x10000000,
0651     GIE_ATCS13  = 0x20000000,
0652     GIE_ATCS14  = 0x40000000,
0653     GIE_ATCS15  = 0x80000000,
0654 };
0655 
0656 /* GID (R-Car Gen3 only) */
0657 enum GID_BIT {
0658     GID_PTCD    = 0x00000001,
0659     GID_PTOD    = 0x00000002,
0660     GID_PTMD0   = 0x00000004,
0661     GID_PTMD1   = 0x00000008,
0662     GID_PTMD2   = 0x00000010,
0663     GID_PTMD3   = 0x00000020,
0664     GID_PTMD4   = 0x00000040,
0665     GID_PTMD5   = 0x00000080,
0666     GID_PTMD6   = 0x00000100,
0667     GID_PTMD7   = 0x00000200,
0668     GID_ATCD0   = 0x00010000,
0669     GID_ATCD1   = 0x00020000,
0670     GID_ATCD2   = 0x00040000,
0671     GID_ATCD3   = 0x00080000,
0672     GID_ATCD4   = 0x00100000,
0673     GID_ATCD5   = 0x00200000,
0674     GID_ATCD6   = 0x00400000,
0675     GID_ATCD7   = 0x00800000,
0676     GID_ATCD8   = 0x01000000,
0677     GID_ATCD9   = 0x02000000,
0678     GID_ATCD10  = 0x04000000,
0679     GID_ATCD11  = 0x08000000,
0680     GID_ATCD12  = 0x10000000,
0681     GID_ATCD13  = 0x20000000,
0682     GID_ATCD14  = 0x40000000,
0683     GID_ATCD15  = 0x80000000,
0684 };
0685 
0686 /* RIE0 (R-Car Gen3 only) */
0687 enum RIE0_BIT {
0688     RIE0_FRS0   = 0x00000001,
0689     RIE0_FRS1   = 0x00000002,
0690     RIE0_FRS2   = 0x00000004,
0691     RIE0_FRS3   = 0x00000008,
0692     RIE0_FRS4   = 0x00000010,
0693     RIE0_FRS5   = 0x00000020,
0694     RIE0_FRS6   = 0x00000040,
0695     RIE0_FRS7   = 0x00000080,
0696     RIE0_FRS8   = 0x00000100,
0697     RIE0_FRS9   = 0x00000200,
0698     RIE0_FRS10  = 0x00000400,
0699     RIE0_FRS11  = 0x00000800,
0700     RIE0_FRS12  = 0x00001000,
0701     RIE0_FRS13  = 0x00002000,
0702     RIE0_FRS14  = 0x00004000,
0703     RIE0_FRS15  = 0x00008000,
0704     RIE0_FRS16  = 0x00010000,
0705     RIE0_FRS17  = 0x00020000,
0706 };
0707 
0708 /* RID0 (R-Car Gen3 only) */
0709 enum RID0_BIT {
0710     RID0_FRD0   = 0x00000001,
0711     RID0_FRD1   = 0x00000002,
0712     RID0_FRD2   = 0x00000004,
0713     RID0_FRD3   = 0x00000008,
0714     RID0_FRD4   = 0x00000010,
0715     RID0_FRD5   = 0x00000020,
0716     RID0_FRD6   = 0x00000040,
0717     RID0_FRD7   = 0x00000080,
0718     RID0_FRD8   = 0x00000100,
0719     RID0_FRD9   = 0x00000200,
0720     RID0_FRD10  = 0x00000400,
0721     RID0_FRD11  = 0x00000800,
0722     RID0_FRD12  = 0x00001000,
0723     RID0_FRD13  = 0x00002000,
0724     RID0_FRD14  = 0x00004000,
0725     RID0_FRD15  = 0x00008000,
0726     RID0_FRD16  = 0x00010000,
0727     RID0_FRD17  = 0x00020000,
0728 };
0729 
0730 /* RIE2 (R-Car Gen3 only) */
0731 enum RIE2_BIT {
0732     RIE2_QFS0   = 0x00000001,
0733     RIE2_QFS1   = 0x00000002,
0734     RIE2_QFS2   = 0x00000004,
0735     RIE2_QFS3   = 0x00000008,
0736     RIE2_QFS4   = 0x00000010,
0737     RIE2_QFS5   = 0x00000020,
0738     RIE2_QFS6   = 0x00000040,
0739     RIE2_QFS7   = 0x00000080,
0740     RIE2_QFS8   = 0x00000100,
0741     RIE2_QFS9   = 0x00000200,
0742     RIE2_QFS10  = 0x00000400,
0743     RIE2_QFS11  = 0x00000800,
0744     RIE2_QFS12  = 0x00001000,
0745     RIE2_QFS13  = 0x00002000,
0746     RIE2_QFS14  = 0x00004000,
0747     RIE2_QFS15  = 0x00008000,
0748     RIE2_QFS16  = 0x00010000,
0749     RIE2_QFS17  = 0x00020000,
0750     RIE2_RFFS   = 0x80000000,
0751 };
0752 
0753 /* RID2 (R-Car Gen3 only) */
0754 enum RID2_BIT {
0755     RID2_QFD0   = 0x00000001,
0756     RID2_QFD1   = 0x00000002,
0757     RID2_QFD2   = 0x00000004,
0758     RID2_QFD3   = 0x00000008,
0759     RID2_QFD4   = 0x00000010,
0760     RID2_QFD5   = 0x00000020,
0761     RID2_QFD6   = 0x00000040,
0762     RID2_QFD7   = 0x00000080,
0763     RID2_QFD8   = 0x00000100,
0764     RID2_QFD9   = 0x00000200,
0765     RID2_QFD10  = 0x00000400,
0766     RID2_QFD11  = 0x00000800,
0767     RID2_QFD12  = 0x00001000,
0768     RID2_QFD13  = 0x00002000,
0769     RID2_QFD14  = 0x00004000,
0770     RID2_QFD15  = 0x00008000,
0771     RID2_QFD16  = 0x00010000,
0772     RID2_QFD17  = 0x00020000,
0773     RID2_RFFD   = 0x80000000,
0774 };
0775 
0776 /* TIE (R-Car Gen3 only) */
0777 enum TIE_BIT {
0778     TIE_FTS0    = 0x00000001,
0779     TIE_FTS1    = 0x00000002,
0780     TIE_FTS2    = 0x00000004,
0781     TIE_FTS3    = 0x00000008,
0782     TIE_TFUS    = 0x00000100,
0783     TIE_TFWS    = 0x00000200,
0784     TIE_MFUS    = 0x00000400,
0785     TIE_MFWS    = 0x00000800,
0786     TIE_TDPS0   = 0x00010000,
0787     TIE_TDPS1   = 0x00020000,
0788     TIE_TDPS2   = 0x00040000,
0789     TIE_TDPS3   = 0x00080000,
0790 };
0791 
0792 /* TID (R-Car Gen3 only) */
0793 enum TID_BIT {
0794     TID_FTD0    = 0x00000001,
0795     TID_FTD1    = 0x00000002,
0796     TID_FTD2    = 0x00000004,
0797     TID_FTD3    = 0x00000008,
0798     TID_TFUD    = 0x00000100,
0799     TID_TFWD    = 0x00000200,
0800     TID_MFUD    = 0x00000400,
0801     TID_MFWD    = 0x00000800,
0802     TID_TDPD0   = 0x00010000,
0803     TID_TDPD1   = 0x00020000,
0804     TID_TDPD2   = 0x00040000,
0805     TID_TDPD3   = 0x00080000,
0806 };
0807 
0808 /* ECMR */
0809 enum ECMR_BIT {
0810     ECMR_PRM    = 0x00000001,
0811     ECMR_DM     = 0x00000002,
0812     ECMR_TE     = 0x00000020,
0813     ECMR_RE     = 0x00000040,
0814     ECMR_MPDE   = 0x00000200,
0815     ECMR_TXF    = 0x00010000,   /* Documented for R-Car Gen3 only */
0816     ECMR_RXF    = 0x00020000,
0817     ECMR_PFR    = 0x00040000,
0818     ECMR_ZPF    = 0x00080000,   /* Documented for R-Car Gen3 and RZ/G2L */
0819     ECMR_RZPF   = 0x00100000,
0820     ECMR_DPAD   = 0x00200000,
0821     ECMR_RCSC   = 0x00800000,
0822     ECMR_RCPT   = 0x02000000,   /* Documented for RZ/G2L only */
0823     ECMR_TRCCM  = 0x04000000,
0824 };
0825 
0826 /* ECSR */
0827 enum ECSR_BIT {
0828     ECSR_ICD    = 0x00000001,
0829     ECSR_MPD    = 0x00000002,
0830     ECSR_LCHNG  = 0x00000004,
0831     ECSR_PHYI   = 0x00000008,
0832     ECSR_PFRI   = 0x00000010,   /* Documented for R-Car Gen3 and RZ/G2L */
0833 };
0834 
0835 /* ECSIPR */
0836 enum ECSIPR_BIT {
0837     ECSIPR_ICDIP    = 0x00000001,
0838     ECSIPR_MPDIP    = 0x00000002,
0839     ECSIPR_LCHNGIP  = 0x00000004,
0840 };
0841 
0842 /* PIR */
0843 enum PIR_BIT {
0844     PIR_MDC     = 0x00000001,
0845     PIR_MMD     = 0x00000002,
0846     PIR_MDO     = 0x00000004,
0847     PIR_MDI     = 0x00000008,
0848 };
0849 
0850 /* PSR */
0851 enum PSR_BIT {
0852     PSR_LMON    = 0x00000001,
0853 };
0854 
0855 /* PIPR */
0856 enum PIPR_BIT {
0857     PIPR_PHYIP  = 0x00000001,
0858 };
0859 
0860 /* MPR */
0861 enum MPR_BIT {
0862     MPR_MP      = 0x0000ffff,
0863 };
0864 
0865 /* GECMR */
0866 enum GECMR_BIT {
0867     GECMR_SPEED     = 0x00000001,
0868     GECMR_SPEED_100     = 0x00000000,
0869     GECMR_SPEED_1000    = 0x00000001,
0870     GBETH_GECMR_SPEED   = 0x00000030,
0871     GBETH_GECMR_SPEED_10    = 0x00000000,
0872     GBETH_GECMR_SPEED_100   = 0x00000010,
0873     GBETH_GECMR_SPEED_1000  = 0x00000020,
0874 };
0875 
0876 /* The Ethernet AVB descriptor definitions. */
0877 struct ravb_desc {
0878     __le16 ds;  /* Descriptor size */
0879     u8 cc;      /* Content control MSBs (reserved) */
0880     u8 die_dt;  /* Descriptor interrupt enable and type */
0881     __le32 dptr;    /* Descriptor pointer */
0882 };
0883 
0884 #define DPTR_ALIGN  4   /* Required descriptor pointer alignment */
0885 
0886 enum DIE_DT {
0887     /* Frame data */
0888     DT_FMID     = 0x40,
0889     DT_FSTART   = 0x50,
0890     DT_FEND     = 0x60,
0891     DT_FSINGLE  = 0x70,
0892     /* Chain control */
0893     DT_LINK     = 0x80,
0894     DT_LINKFIX  = 0x90,
0895     DT_EOS      = 0xa0,
0896     /* HW/SW arbitration */
0897     DT_FEMPTY   = 0xc0,
0898     DT_FEMPTY_IS    = 0xd0,
0899     DT_FEMPTY_IC    = 0xe0,
0900     DT_FEMPTY_ND    = 0xf0,
0901     DT_LEMPTY   = 0x20,
0902     DT_EEMPTY   = 0x30,
0903 };
0904 
0905 struct ravb_rx_desc {
0906     __le16 ds_cc;   /* Descriptor size and content control LSBs */
0907     u8 msc;     /* MAC status code */
0908     u8 die_dt;  /* Descriptor interrupt enable and type */
0909     __le32 dptr;    /* Descpriptor pointer */
0910 };
0911 
0912 struct ravb_ex_rx_desc {
0913     __le16 ds_cc;   /* Descriptor size and content control lower bits */
0914     u8 msc;     /* MAC status code */
0915     u8 die_dt;  /* Descriptor interrupt enable and type */
0916     __le32 dptr;    /* Descpriptor pointer */
0917     __le32 ts_n;    /* Timestampe nsec */
0918     __le32 ts_sl;   /* Timestamp low */
0919     __le16 ts_sh;   /* Timestamp high */
0920     __le16 res; /* Reserved bits */
0921 };
0922 
0923 enum RX_DS_CC_BIT {
0924     RX_DS       = 0x0fff, /* Data size */
0925     RX_TR       = 0x1000, /* Truncation indication */
0926     RX_EI       = 0x2000, /* Error indication */
0927     RX_PS       = 0xc000, /* Padding selection */
0928 };
0929 
0930 /* E-MAC status code */
0931 enum MSC_BIT {
0932     MSC_CRC     = 0x01, /* Frame CRC error */
0933     MSC_RFE     = 0x02, /* Frame reception error (flagged by PHY) */
0934     MSC_RTSF    = 0x04, /* Frame length error (frame too short) */
0935     MSC_RTLF    = 0x08, /* Frame length error (frame too long) */
0936     MSC_FRE     = 0x10, /* Fraction error (not a multiple of 8 bits) */
0937     MSC_CRL     = 0x20, /* Carrier lost */
0938     MSC_CEEF    = 0x40, /* Carrier extension error */
0939     MSC_MC      = 0x80, /* Multicast frame reception */
0940 };
0941 
0942 struct ravb_tx_desc {
0943     __le16 ds_tagl; /* Descriptor size and frame tag LSBs */
0944     u8 tagh_tsr;    /* Frame tag MSBs and timestamp storage request bit */
0945     u8 die_dt;  /* Descriptor interrupt enable and type */
0946     __le32 dptr;    /* Descpriptor pointer */
0947 };
0948 
0949 enum TX_DS_TAGL_BIT {
0950     TX_DS       = 0x0fff, /* Data size */
0951     TX_TAGL     = 0xf000, /* Frame tag LSBs */
0952 };
0953 
0954 enum TX_TAGH_TSR_BIT {
0955     TX_TAGH     = 0x3f, /* Frame tag MSBs */
0956     TX_TSR      = 0x40, /* Timestamp storage request */
0957 };
0958 enum RAVB_QUEUE {
0959     RAVB_BE = 0,    /* Best Effort Queue */
0960     RAVB_NC,    /* Network Control Queue */
0961 };
0962 
0963 enum CXR31_BIT {
0964     CXR31_SEL_LINK0 = 0x00000001,
0965     CXR31_SEL_LINK1 = 0x00000008,
0966 };
0967 
0968 enum CSR0_BIT {
0969     CSR0_TPE    = 0x00000010,
0970     CSR0_RPE    = 0x00000020,
0971 };
0972 
0973 #define DBAT_ENTRY_NUM  22
0974 #define RX_QUEUE_OFFSET 4
0975 #define NUM_RX_QUEUE    2
0976 #define NUM_TX_QUEUE    2
0977 
0978 #define RX_BUF_SZ   (2048 - ETH_FCS_LEN + sizeof(__sum16))
0979 
0980 #define GBETH_RX_BUFF_MAX 8192
0981 #define GBETH_RX_DESC_DATA_SIZE 4080
0982 
0983 struct ravb_tstamp_skb {
0984     struct list_head list;
0985     struct sk_buff *skb;
0986     u16 tag;
0987 };
0988 
0989 struct ravb_ptp_perout {
0990     u32 target;
0991     u32 period;
0992 };
0993 
0994 #define N_EXT_TS    1
0995 #define N_PER_OUT   1
0996 
0997 struct ravb_ptp {
0998     struct ptp_clock *clock;
0999     struct ptp_clock_info info;
1000     u32 default_addend;
1001     u32 current_addend;
1002     int extts[N_EXT_TS];
1003     struct ravb_ptp_perout perout[N_PER_OUT];
1004 };
1005 
1006 struct ravb_hw_info {
1007     void (*rx_ring_free)(struct net_device *ndev, int q);
1008     void (*rx_ring_format)(struct net_device *ndev, int q);
1009     void *(*alloc_rx_desc)(struct net_device *ndev, int q);
1010     bool (*receive)(struct net_device *ndev, int *quota, int q);
1011     void (*set_rate)(struct net_device *ndev);
1012     int (*set_feature)(struct net_device *ndev, netdev_features_t features);
1013     int (*dmac_init)(struct net_device *ndev);
1014     void (*emac_init)(struct net_device *ndev);
1015     const char (*gstrings_stats)[ETH_GSTRING_LEN];
1016     size_t gstrings_size;
1017     netdev_features_t net_hw_features;
1018     netdev_features_t net_features;
1019     int stats_len;
1020     size_t max_rx_len;
1021     u32 tccr_mask;
1022     u32 rx_max_buf_size;
1023     unsigned aligned_tx: 1;
1024 
1025     /* hardware features */
1026     unsigned internal_delay:1;  /* AVB-DMAC has internal delays */
1027     unsigned tx_counters:1;     /* E-MAC has TX counters */
1028     unsigned carrier_counters:1;    /* E-MAC has carrier counters */
1029     unsigned multi_irqs:1;      /* AVB-DMAC and E-MAC has multiple irqs */
1030     unsigned irq_en_dis:1;      /* Has separate irq enable and disable regs */
1031     unsigned err_mgmt_irqs:1;   /* Line1 (Err) and Line2 (Mgmt) irqs are separate */
1032     unsigned gptp:1;        /* AVB-DMAC has gPTP support */
1033     unsigned ccc_gac:1;     /* AVB-DMAC has gPTP support active in config mode */
1034     unsigned gptp_ref_clk:1;    /* gPTP has separate reference clock */
1035     unsigned nc_queues:1;       /* AVB-DMAC has RX and TX NC queues */
1036     unsigned magic_pkt:1;       /* E-MAC supports magic packet detection */
1037     unsigned half_duplex:1;     /* E-MAC supports half duplex mode */
1038 };
1039 
1040 struct ravb_private {
1041     struct net_device *ndev;
1042     struct platform_device *pdev;
1043     void __iomem *addr;
1044     struct clk *clk;
1045     struct clk *refclk;
1046     struct clk *gptp_clk;
1047     struct mdiobb_ctrl mdiobb;
1048     u32 num_rx_ring[NUM_RX_QUEUE];
1049     u32 num_tx_ring[NUM_TX_QUEUE];
1050     u32 desc_bat_size;
1051     dma_addr_t desc_bat_dma;
1052     struct ravb_desc *desc_bat;
1053     dma_addr_t rx_desc_dma[NUM_RX_QUEUE];
1054     dma_addr_t tx_desc_dma[NUM_TX_QUEUE];
1055     struct ravb_rx_desc *gbeth_rx_ring;
1056     struct ravb_ex_rx_desc *rx_ring[NUM_RX_QUEUE];
1057     struct ravb_tx_desc *tx_ring[NUM_TX_QUEUE];
1058     void *tx_align[NUM_TX_QUEUE];
1059     struct sk_buff *rx_1st_skb;
1060     struct sk_buff **rx_skb[NUM_RX_QUEUE];
1061     struct sk_buff **tx_skb[NUM_TX_QUEUE];
1062     u32 rx_over_errors;
1063     u32 rx_fifo_errors;
1064     struct net_device_stats stats[NUM_RX_QUEUE];
1065     u32 tstamp_tx_ctrl;
1066     u32 tstamp_rx_ctrl;
1067     struct list_head ts_skb_list;
1068     u32 ts_skb_tag;
1069     struct ravb_ptp ptp;
1070     spinlock_t lock;        /* Register access lock */
1071     u32 cur_rx[NUM_RX_QUEUE];   /* Consumer ring indices */
1072     u32 dirty_rx[NUM_RX_QUEUE]; /* Producer ring indices */
1073     u32 cur_tx[NUM_TX_QUEUE];
1074     u32 dirty_tx[NUM_TX_QUEUE];
1075     struct napi_struct napi[NUM_RX_QUEUE];
1076     struct work_struct work;
1077     /* MII transceiver section. */
1078     struct mii_bus *mii_bus;    /* MDIO bus control */
1079     int link;
1080     phy_interface_t phy_interface;
1081     int msg_enable;
1082     int speed;
1083     int emac_irq;
1084     int erra_irq;
1085     int mgmta_irq;
1086     int rx_irqs[NUM_RX_QUEUE];
1087     int tx_irqs[NUM_TX_QUEUE];
1088 
1089     unsigned no_avb_link:1;
1090     unsigned avb_link_active_low:1;
1091     unsigned wol_enabled:1;
1092     unsigned rxcidm:1;      /* RX Clock Internal Delay Mode */
1093     unsigned txcidm:1;      /* TX Clock Internal Delay Mode */
1094     unsigned rgmii_override:1;  /* Deprecated rgmii-*id behavior */
1095     unsigned int num_tx_desc;   /* TX descriptors per packet */
1096 
1097     int duplex;
1098 
1099     const struct ravb_hw_info *info;
1100     struct reset_control *rstc;
1101 };
1102 
1103 static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg)
1104 {
1105     struct ravb_private *priv = netdev_priv(ndev);
1106 
1107     return ioread32(priv->addr + reg);
1108 }
1109 
1110 static inline void ravb_write(struct net_device *ndev, u32 data,
1111                   enum ravb_reg reg)
1112 {
1113     struct ravb_private *priv = netdev_priv(ndev);
1114 
1115     iowrite32(data, priv->addr + reg);
1116 }
1117 
1118 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
1119          u32 set);
1120 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value);
1121 
1122 void ravb_ptp_interrupt(struct net_device *ndev);
1123 void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev);
1124 void ravb_ptp_stop(struct net_device *ndev);
1125 
1126 #endif  /* #ifndef __RAVB_H__ */
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