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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * r8169_phy_config.c: RealTek 8169/8168/8101 ethernet driver.
0004  *
0005  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
0006  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
0007  * Copyright (c) a lot of people too. Please respect their work.
0008  *
0009  * See MAINTAINERS file for support contact information.
0010  */
0011 
0012 #include <linux/delay.h>
0013 #include <linux/phy.h>
0014 
0015 #include "r8169.h"
0016 
0017 typedef void (*rtl_phy_cfg_fct)(struct rtl8169_private *tp,
0018                 struct phy_device *phydev);
0019 
0020 static void r8168d_modify_extpage(struct phy_device *phydev, int extpage,
0021                   int reg, u16 mask, u16 val)
0022 {
0023     int oldpage = phy_select_page(phydev, 0x0007);
0024 
0025     __phy_write(phydev, 0x1e, extpage);
0026     __phy_modify(phydev, reg, mask, val);
0027 
0028     phy_restore_page(phydev, oldpage, 0);
0029 }
0030 
0031 static void r8168d_phy_param(struct phy_device *phydev, u16 parm,
0032                  u16 mask, u16 val)
0033 {
0034     int oldpage = phy_select_page(phydev, 0x0005);
0035 
0036     __phy_write(phydev, 0x05, parm);
0037     __phy_modify(phydev, 0x06, mask, val);
0038 
0039     phy_restore_page(phydev, oldpage, 0);
0040 }
0041 
0042 static void r8168g_phy_param(struct phy_device *phydev, u16 parm,
0043                  u16 mask, u16 val)
0044 {
0045     int oldpage = phy_select_page(phydev, 0x0a43);
0046 
0047     __phy_write(phydev, 0x13, parm);
0048     __phy_modify(phydev, 0x14, mask, val);
0049 
0050     phy_restore_page(phydev, oldpage, 0);
0051 }
0052 
0053 struct phy_reg {
0054     u16 reg;
0055     u16 val;
0056 };
0057 
0058 static void __rtl_writephy_batch(struct phy_device *phydev,
0059                  const struct phy_reg *regs, int len)
0060 {
0061     phy_lock_mdio_bus(phydev);
0062 
0063     while (len-- > 0) {
0064         __phy_write(phydev, regs->reg, regs->val);
0065         regs++;
0066     }
0067 
0068     phy_unlock_mdio_bus(phydev);
0069 }
0070 
0071 #define rtl_writephy_batch(p, a) __rtl_writephy_batch(p, a, ARRAY_SIZE(a))
0072 
0073 static void rtl8168f_config_eee_phy(struct phy_device *phydev)
0074 {
0075     r8168d_modify_extpage(phydev, 0x0020, 0x15, 0, BIT(8));
0076     r8168d_phy_param(phydev, 0x8b85, 0, BIT(13));
0077 }
0078 
0079 static void rtl8168g_config_eee_phy(struct phy_device *phydev)
0080 {
0081     phy_modify_paged(phydev, 0x0a43, 0x11, 0, BIT(4));
0082 }
0083 
0084 static void rtl8168h_config_eee_phy(struct phy_device *phydev)
0085 {
0086     rtl8168g_config_eee_phy(phydev);
0087 
0088     phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200);
0089     phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080);
0090 }
0091 
0092 static void rtl8125a_config_eee_phy(struct phy_device *phydev)
0093 {
0094     rtl8168h_config_eee_phy(phydev);
0095 
0096     phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000);
0097     phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000);
0098 }
0099 
0100 static void rtl8125b_config_eee_phy(struct phy_device *phydev)
0101 {
0102     phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000);
0103     phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000);
0104     phy_modify_paged(phydev, 0xa42, 0x14, 0x0080, 0x0000);
0105     phy_modify_paged(phydev, 0xa4a, 0x11, 0x0200, 0x0000);
0106 }
0107 
0108 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp,
0109                    struct phy_device *phydev)
0110 {
0111     static const struct phy_reg phy_reg_init[] = {
0112         { 0x1f, 0x0001 },
0113         { 0x06, 0x006e },
0114         { 0x08, 0x0708 },
0115         { 0x15, 0x4000 },
0116         { 0x18, 0x65c7 },
0117 
0118         { 0x1f, 0x0001 },
0119         { 0x03, 0x00a1 },
0120         { 0x02, 0x0008 },
0121         { 0x01, 0x0120 },
0122         { 0x00, 0x1000 },
0123         { 0x04, 0x0800 },
0124         { 0x04, 0x0000 },
0125 
0126         { 0x03, 0xff41 },
0127         { 0x02, 0xdf60 },
0128         { 0x01, 0x0140 },
0129         { 0x00, 0x0077 },
0130         { 0x04, 0x7800 },
0131         { 0x04, 0x7000 },
0132 
0133         { 0x03, 0x802f },
0134         { 0x02, 0x4f02 },
0135         { 0x01, 0x0409 },
0136         { 0x00, 0xf0f9 },
0137         { 0x04, 0x9800 },
0138         { 0x04, 0x9000 },
0139 
0140         { 0x03, 0xdf01 },
0141         { 0x02, 0xdf20 },
0142         { 0x01, 0xff95 },
0143         { 0x00, 0xba00 },
0144         { 0x04, 0xa800 },
0145         { 0x04, 0xa000 },
0146 
0147         { 0x03, 0xff41 },
0148         { 0x02, 0xdf20 },
0149         { 0x01, 0x0140 },
0150         { 0x00, 0x00bb },
0151         { 0x04, 0xb800 },
0152         { 0x04, 0xb000 },
0153 
0154         { 0x03, 0xdf41 },
0155         { 0x02, 0xdc60 },
0156         { 0x01, 0x6340 },
0157         { 0x00, 0x007d },
0158         { 0x04, 0xd800 },
0159         { 0x04, 0xd000 },
0160 
0161         { 0x03, 0xdf01 },
0162         { 0x02, 0xdf20 },
0163         { 0x01, 0x100a },
0164         { 0x00, 0xa0ff },
0165         { 0x04, 0xf800 },
0166         { 0x04, 0xf000 },
0167 
0168         { 0x1f, 0x0000 },
0169         { 0x0b, 0x0000 },
0170         { 0x00, 0x9200 }
0171     };
0172 
0173     rtl_writephy_batch(phydev, phy_reg_init);
0174 }
0175 
0176 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp,
0177                     struct phy_device *phydev)
0178 {
0179     phy_write_paged(phydev, 0x0002, 0x01, 0x90d0);
0180 }
0181 
0182 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
0183                      struct phy_device *phydev)
0184 {
0185     static const struct phy_reg phy_reg_init[] = {
0186         { 0x1f, 0x0001 },
0187         { 0x04, 0x0000 },
0188         { 0x03, 0x00a1 },
0189         { 0x02, 0x0008 },
0190         { 0x01, 0x0120 },
0191         { 0x00, 0x1000 },
0192         { 0x04, 0x0800 },
0193         { 0x04, 0x9000 },
0194         { 0x03, 0x802f },
0195         { 0x02, 0x4f02 },
0196         { 0x01, 0x0409 },
0197         { 0x00, 0xf099 },
0198         { 0x04, 0x9800 },
0199         { 0x04, 0xa000 },
0200         { 0x03, 0xdf01 },
0201         { 0x02, 0xdf20 },
0202         { 0x01, 0xff95 },
0203         { 0x00, 0xba00 },
0204         { 0x04, 0xa800 },
0205         { 0x04, 0xf000 },
0206         { 0x03, 0xdf01 },
0207         { 0x02, 0xdf20 },
0208         { 0x01, 0x101a },
0209         { 0x00, 0xa0ff },
0210         { 0x04, 0xf800 },
0211         { 0x04, 0x0000 },
0212         { 0x1f, 0x0000 },
0213 
0214         { 0x1f, 0x0001 },
0215         { 0x10, 0xf41b },
0216         { 0x14, 0xfb54 },
0217         { 0x18, 0xf5c7 },
0218         { 0x1f, 0x0000 },
0219 
0220         { 0x1f, 0x0001 },
0221         { 0x17, 0x0cc0 },
0222         { 0x1f, 0x0000 }
0223     };
0224 
0225     rtl_writephy_batch(phydev, phy_reg_init);
0226 }
0227 
0228 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp,
0229                      struct phy_device *phydev)
0230 {
0231     static const struct phy_reg phy_reg_init[] = {
0232         { 0x1f, 0x0001 },
0233         { 0x04, 0x0000 },
0234         { 0x03, 0x00a1 },
0235         { 0x02, 0x0008 },
0236         { 0x01, 0x0120 },
0237         { 0x00, 0x1000 },
0238         { 0x04, 0x0800 },
0239         { 0x04, 0x9000 },
0240         { 0x03, 0x802f },
0241         { 0x02, 0x4f02 },
0242         { 0x01, 0x0409 },
0243         { 0x00, 0xf099 },
0244         { 0x04, 0x9800 },
0245         { 0x04, 0xa000 },
0246         { 0x03, 0xdf01 },
0247         { 0x02, 0xdf20 },
0248         { 0x01, 0xff95 },
0249         { 0x00, 0xba00 },
0250         { 0x04, 0xa800 },
0251         { 0x04, 0xf000 },
0252         { 0x03, 0xdf01 },
0253         { 0x02, 0xdf20 },
0254         { 0x01, 0x101a },
0255         { 0x00, 0xa0ff },
0256         { 0x04, 0xf800 },
0257         { 0x04, 0x0000 },
0258         { 0x1f, 0x0000 },
0259 
0260         { 0x1f, 0x0001 },
0261         { 0x0b, 0x8480 },
0262         { 0x1f, 0x0000 },
0263 
0264         { 0x1f, 0x0001 },
0265         { 0x18, 0x67c7 },
0266         { 0x04, 0x2000 },
0267         { 0x03, 0x002f },
0268         { 0x02, 0x4360 },
0269         { 0x01, 0x0109 },
0270         { 0x00, 0x3022 },
0271         { 0x04, 0x2800 },
0272         { 0x1f, 0x0000 },
0273 
0274         { 0x1f, 0x0001 },
0275         { 0x17, 0x0cc0 },
0276         { 0x1f, 0x0000 }
0277     };
0278 
0279     rtl_writephy_batch(phydev, phy_reg_init);
0280 }
0281 
0282 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp,
0283                     struct phy_device *phydev)
0284 {
0285     phy_write(phydev, 0x1f, 0x0001);
0286     phy_set_bits(phydev, 0x16, BIT(0));
0287     phy_write(phydev, 0x10, 0xf41b);
0288     phy_write(phydev, 0x1f, 0x0000);
0289 }
0290 
0291 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp,
0292                      struct phy_device *phydev)
0293 {
0294     phy_write_paged(phydev, 0x0001, 0x10, 0xf41b);
0295 }
0296 
0297 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp,
0298                       struct phy_device *phydev)
0299 {
0300     phy_write(phydev, 0x1d, 0x0f00);
0301     phy_write_paged(phydev, 0x0002, 0x0c, 0x1ec8);
0302 }
0303 
0304 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp,
0305                       struct phy_device *phydev)
0306 {
0307     phy_set_bits(phydev, 0x14, BIT(5));
0308     phy_set_bits(phydev, 0x0d, BIT(5));
0309     phy_write_paged(phydev, 0x0001, 0x1d, 0x3d98);
0310 }
0311 
0312 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp,
0313                      struct phy_device *phydev)
0314 {
0315     static const struct phy_reg phy_reg_init[] = {
0316         { 0x1f, 0x0001 },
0317         { 0x12, 0x2300 },
0318         { 0x1f, 0x0002 },
0319         { 0x00, 0x88d4 },
0320         { 0x01, 0x82b1 },
0321         { 0x03, 0x7002 },
0322         { 0x08, 0x9e30 },
0323         { 0x09, 0x01f0 },
0324         { 0x0a, 0x5500 },
0325         { 0x0c, 0x00c8 },
0326         { 0x1f, 0x0003 },
0327         { 0x12, 0xc096 },
0328         { 0x16, 0x000a },
0329         { 0x1f, 0x0000 },
0330         { 0x1f, 0x0000 },
0331         { 0x09, 0x2000 },
0332         { 0x09, 0x0000 }
0333     };
0334 
0335     rtl_writephy_batch(phydev, phy_reg_init);
0336 
0337     phy_set_bits(phydev, 0x14, BIT(5));
0338     phy_set_bits(phydev, 0x0d, BIT(5));
0339 }
0340 
0341 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp,
0342                      struct phy_device *phydev)
0343 {
0344     static const struct phy_reg phy_reg_init[] = {
0345         { 0x1f, 0x0001 },
0346         { 0x12, 0x2300 },
0347         { 0x03, 0x802f },
0348         { 0x02, 0x4f02 },
0349         { 0x01, 0x0409 },
0350         { 0x00, 0xf099 },
0351         { 0x04, 0x9800 },
0352         { 0x04, 0x9000 },
0353         { 0x1d, 0x3d98 },
0354         { 0x1f, 0x0002 },
0355         { 0x0c, 0x7eb8 },
0356         { 0x06, 0x0761 },
0357         { 0x1f, 0x0003 },
0358         { 0x16, 0x0f0a },
0359         { 0x1f, 0x0000 }
0360     };
0361 
0362     rtl_writephy_batch(phydev, phy_reg_init);
0363 
0364     phy_set_bits(phydev, 0x16, BIT(0));
0365     phy_set_bits(phydev, 0x14, BIT(5));
0366     phy_set_bits(phydev, 0x0d, BIT(5));
0367 }
0368 
0369 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp,
0370                      struct phy_device *phydev)
0371 {
0372     static const struct phy_reg phy_reg_init[] = {
0373         { 0x1f, 0x0001 },
0374         { 0x12, 0x2300 },
0375         { 0x1d, 0x3d98 },
0376         { 0x1f, 0x0002 },
0377         { 0x0c, 0x7eb8 },
0378         { 0x06, 0x5461 },
0379         { 0x1f, 0x0003 },
0380         { 0x16, 0x0f0a },
0381         { 0x1f, 0x0000 }
0382     };
0383 
0384     rtl_writephy_batch(phydev, phy_reg_init);
0385 
0386     phy_set_bits(phydev, 0x16, BIT(0));
0387     phy_set_bits(phydev, 0x14, BIT(5));
0388     phy_set_bits(phydev, 0x0d, BIT(5));
0389 }
0390 
0391 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
0392     /* Channel Estimation */
0393     { 0x1f, 0x0001 },
0394     { 0x06, 0x4064 },
0395     { 0x07, 0x2863 },
0396     { 0x08, 0x059c },
0397     { 0x09, 0x26b4 },
0398     { 0x0a, 0x6a19 },
0399     { 0x0b, 0xdcc8 },
0400     { 0x10, 0xf06d },
0401     { 0x14, 0x7f68 },
0402     { 0x18, 0x7fd9 },
0403     { 0x1c, 0xf0ff },
0404     { 0x1d, 0x3d9c },
0405     { 0x1f, 0x0003 },
0406     { 0x12, 0xf49f },
0407     { 0x13, 0x070b },
0408     { 0x1a, 0x05ad },
0409     { 0x14, 0x94c0 },
0410 
0411     /*
0412      * Tx Error Issue
0413      * Enhance line driver power
0414      */
0415     { 0x1f, 0x0002 },
0416     { 0x06, 0x5561 },
0417     { 0x1f, 0x0005 },
0418     { 0x05, 0x8332 },
0419     { 0x06, 0x5561 },
0420 
0421     /*
0422      * Can not link to 1Gbps with bad cable
0423      * Decrease SNR threshold form 21.07dB to 19.04dB
0424      */
0425     { 0x1f, 0x0001 },
0426     { 0x17, 0x0cc0 },
0427 
0428     { 0x1f, 0x0000 },
0429     { 0x0d, 0xf880 }
0430 };
0431 
0432 static void rtl8168d_apply_firmware_cond(struct rtl8169_private *tp,
0433                      struct phy_device *phydev,
0434                      u16 val)
0435 {
0436     u16 reg_val;
0437 
0438     phy_write(phydev, 0x1f, 0x0005);
0439     phy_write(phydev, 0x05, 0x001b);
0440     reg_val = phy_read(phydev, 0x06);
0441     phy_write(phydev, 0x1f, 0x0000);
0442 
0443     if (reg_val != val)
0444         phydev_warn(phydev, "chipset not ready for firmware\n");
0445     else
0446         r8169_apply_firmware(tp);
0447 }
0448 
0449 static void rtl8168d_1_common(struct phy_device *phydev)
0450 {
0451     u16 val;
0452 
0453     phy_write_paged(phydev, 0x0002, 0x05, 0x669a);
0454     r8168d_phy_param(phydev, 0x8330, 0xffff, 0x669a);
0455     phy_write(phydev, 0x1f, 0x0002);
0456 
0457     val = phy_read(phydev, 0x0d);
0458 
0459     if ((val & 0x00ff) != 0x006c) {
0460         static const u16 set[] = {
0461             0x0065, 0x0066, 0x0067, 0x0068,
0462             0x0069, 0x006a, 0x006b, 0x006c
0463         };
0464         int i;
0465 
0466         val &= 0xff00;
0467         for (i = 0; i < ARRAY_SIZE(set); i++)
0468             phy_write(phydev, 0x0d, val | set[i]);
0469     }
0470 }
0471 
0472 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp,
0473                      struct phy_device *phydev)
0474 {
0475     rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0);
0476 
0477     /*
0478      * Rx Error Issue
0479      * Fine Tune Switching regulator parameter
0480      */
0481     phy_write(phydev, 0x1f, 0x0002);
0482     phy_modify(phydev, 0x0b, 0x00ef, 0x0010);
0483     phy_modify(phydev, 0x0c, 0x5d00, 0xa200);
0484 
0485     if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
0486         rtl8168d_1_common(phydev);
0487     } else {
0488         phy_write_paged(phydev, 0x0002, 0x05, 0x6662);
0489         r8168d_phy_param(phydev, 0x8330, 0xffff, 0x6662);
0490     }
0491 
0492     /* RSET couple improve */
0493     phy_write(phydev, 0x1f, 0x0002);
0494     phy_set_bits(phydev, 0x0d, 0x0300);
0495     phy_set_bits(phydev, 0x0f, 0x0010);
0496 
0497     /* Fine tune PLL performance */
0498     phy_write(phydev, 0x1f, 0x0002);
0499     phy_modify(phydev, 0x02, 0x0600, 0x0100);
0500     phy_clear_bits(phydev, 0x03, 0xe000);
0501     phy_write(phydev, 0x1f, 0x0000);
0502 
0503     rtl8168d_apply_firmware_cond(tp, phydev, 0xbf00);
0504 }
0505 
0506 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp,
0507                      struct phy_device *phydev)
0508 {
0509     rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0);
0510 
0511     if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
0512         rtl8168d_1_common(phydev);
0513     } else {
0514         phy_write_paged(phydev, 0x0002, 0x05, 0x2642);
0515         r8168d_phy_param(phydev, 0x8330, 0xffff, 0x2642);
0516     }
0517 
0518     /* Fine tune PLL performance */
0519     phy_write(phydev, 0x1f, 0x0002);
0520     phy_modify(phydev, 0x02, 0x0600, 0x0100);
0521     phy_clear_bits(phydev, 0x03, 0xe000);
0522     phy_write(phydev, 0x1f, 0x0000);
0523 
0524     /* Switching regulator Slew rate */
0525     phy_modify_paged(phydev, 0x0002, 0x0f, 0x0000, 0x0017);
0526 
0527     rtl8168d_apply_firmware_cond(tp, phydev, 0xb300);
0528 }
0529 
0530 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp,
0531                      struct phy_device *phydev)
0532 {
0533     phy_write_paged(phydev, 0x0001, 0x17, 0x0cc0);
0534     r8168d_modify_extpage(phydev, 0x002d, 0x18, 0xffff, 0x0040);
0535     phy_set_bits(phydev, 0x0d, BIT(5));
0536 }
0537 
0538 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp,
0539                      struct phy_device *phydev)
0540 {
0541     static const struct phy_reg phy_reg_init[] = {
0542         /* Channel estimation fine tune */
0543         { 0x1f, 0x0001 },
0544         { 0x0b, 0x6c20 },
0545         { 0x07, 0x2872 },
0546         { 0x1c, 0xefff },
0547         { 0x1f, 0x0003 },
0548         { 0x14, 0x6420 },
0549         { 0x1f, 0x0000 },
0550     };
0551 
0552     r8169_apply_firmware(tp);
0553 
0554     /* Enable Delay cap */
0555     r8168d_phy_param(phydev, 0x8b80, 0xffff, 0xc896);
0556 
0557     rtl_writephy_batch(phydev, phy_reg_init);
0558 
0559     /* Update PFM & 10M TX idle timer */
0560     r8168d_modify_extpage(phydev, 0x002f, 0x15, 0xffff, 0x1919);
0561 
0562     r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006);
0563 
0564     /* DCO enable for 10M IDLE Power */
0565     r8168d_modify_extpage(phydev, 0x0023, 0x17, 0x0000, 0x0006);
0566 
0567     /* For impedance matching */
0568     phy_modify_paged(phydev, 0x0002, 0x08, 0x7f00, 0x8000);
0569 
0570     /* PHY auto speed down */
0571     r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0050);
0572     phy_set_bits(phydev, 0x14, BIT(15));
0573 
0574     r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001);
0575     r8168d_phy_param(phydev, 0x8b85, 0x2000, 0x0000);
0576 
0577     r8168d_modify_extpage(phydev, 0x0020, 0x15, 0x1100, 0x0000);
0578     phy_write_paged(phydev, 0x0006, 0x00, 0x5a00);
0579 
0580     phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0000);
0581 }
0582 
0583 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp,
0584                      struct phy_device *phydev)
0585 {
0586     r8169_apply_firmware(tp);
0587 
0588     /* Enable Delay cap */
0589     r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006);
0590 
0591     /* Channel estimation fine tune */
0592     phy_write_paged(phydev, 0x0003, 0x09, 0xa20f);
0593 
0594     /* Green Setting */
0595     r8168d_phy_param(phydev, 0x8b5b, 0xffff, 0x9222);
0596     r8168d_phy_param(phydev, 0x8b6d, 0xffff, 0x8000);
0597     r8168d_phy_param(phydev, 0x8b76, 0xffff, 0x8000);
0598 
0599     /* For 4-corner performance improve */
0600     phy_write(phydev, 0x1f, 0x0005);
0601     phy_write(phydev, 0x05, 0x8b80);
0602     phy_set_bits(phydev, 0x17, 0x0006);
0603     phy_write(phydev, 0x1f, 0x0000);
0604 
0605     /* PHY auto speed down */
0606     r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010);
0607     phy_set_bits(phydev, 0x14, BIT(15));
0608 
0609     /* improve 10M EEE waveform */
0610     r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001);
0611 
0612     /* Improve 2-pair detection performance */
0613     r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000);
0614 
0615     rtl8168f_config_eee_phy(phydev);
0616 
0617     /* Green feature */
0618     phy_write(phydev, 0x1f, 0x0003);
0619     phy_set_bits(phydev, 0x19, BIT(0));
0620     phy_set_bits(phydev, 0x10, BIT(10));
0621     phy_write(phydev, 0x1f, 0x0000);
0622     phy_modify_paged(phydev, 0x0005, 0x01, 0, BIT(8));
0623 }
0624 
0625 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp,
0626                    struct phy_device *phydev)
0627 {
0628     /* For 4-corner performance improve */
0629     r8168d_phy_param(phydev, 0x8b80, 0x0000, 0x0006);
0630 
0631     /* PHY auto speed down */
0632     r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010);
0633     phy_set_bits(phydev, 0x14, BIT(15));
0634 
0635     /* Improve 10M EEE waveform */
0636     r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001);
0637 
0638     rtl8168f_config_eee_phy(phydev);
0639 }
0640 
0641 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp,
0642                      struct phy_device *phydev)
0643 {
0644     r8169_apply_firmware(tp);
0645 
0646     /* Channel estimation fine tune */
0647     phy_write_paged(phydev, 0x0003, 0x09, 0xa20f);
0648 
0649     /* Modify green table for giga & fnet */
0650     r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000);
0651     r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000);
0652     r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000);
0653     r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000);
0654     r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000);
0655     r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00fb);
0656 
0657     /* Modify green table for 10M */
0658     r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00);
0659 
0660     /* Disable hiimpedance detection (RTCT) */
0661     phy_write_paged(phydev, 0x0003, 0x01, 0x328a);
0662 
0663     rtl8168f_hw_phy_config(tp, phydev);
0664 
0665     /* Improve 2-pair detection performance */
0666     r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000);
0667 }
0668 
0669 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp,
0670                      struct phy_device *phydev)
0671 {
0672     r8169_apply_firmware(tp);
0673 
0674     rtl8168f_hw_phy_config(tp, phydev);
0675 }
0676 
0677 static void rtl8411_hw_phy_config(struct rtl8169_private *tp,
0678                   struct phy_device *phydev)
0679 {
0680     r8169_apply_firmware(tp);
0681 
0682     rtl8168f_hw_phy_config(tp, phydev);
0683 
0684     /* Improve 2-pair detection performance */
0685     r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000);
0686 
0687     /* Channel estimation fine tune */
0688     phy_write_paged(phydev, 0x0003, 0x09, 0xa20f);
0689 
0690     /* Modify green table for giga & fnet */
0691     r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000);
0692     r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000);
0693     r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000);
0694     r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000);
0695     r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000);
0696     r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00aa);
0697 
0698     /* Modify green table for 10M */
0699     r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00);
0700 
0701     /* Disable hiimpedance detection (RTCT) */
0702     phy_write_paged(phydev, 0x0003, 0x01, 0x328a);
0703 
0704     /* Modify green table for giga */
0705     r8168d_phy_param(phydev, 0x8b54, 0x0800, 0x0000);
0706     r8168d_phy_param(phydev, 0x8b5d, 0x0800, 0x0000);
0707     r8168d_phy_param(phydev, 0x8a7c, 0x0100, 0x0000);
0708     r8168d_phy_param(phydev, 0x8a7f, 0x0000, 0x0100);
0709     r8168d_phy_param(phydev, 0x8a82, 0x0100, 0x0000);
0710     r8168d_phy_param(phydev, 0x8a85, 0x0100, 0x0000);
0711     r8168d_phy_param(phydev, 0x8a88, 0x0100, 0x0000);
0712 
0713     /* uc same-seed solution */
0714     r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x8000);
0715 
0716     /* Green feature */
0717     phy_write(phydev, 0x1f, 0x0003);
0718     phy_clear_bits(phydev, 0x19, BIT(0));
0719     phy_clear_bits(phydev, 0x10, BIT(10));
0720     phy_write(phydev, 0x1f, 0x0000);
0721 }
0722 
0723 static void rtl8168g_disable_aldps(struct phy_device *phydev)
0724 {
0725     phy_modify_paged(phydev, 0x0a43, 0x10, BIT(2), 0);
0726 }
0727 
0728 static void rtl8168g_enable_gphy_10m(struct phy_device *phydev)
0729 {
0730     phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(11));
0731 }
0732 
0733 static void rtl8168g_phy_adjust_10m_aldps(struct phy_device *phydev)
0734 {
0735     phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
0736     phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
0737     r8168g_phy_param(phydev, 0x8084, 0x6000, 0x0000);
0738     phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x1003);
0739 }
0740 
0741 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp,
0742                      struct phy_device *phydev)
0743 {
0744     int ret;
0745 
0746     r8169_apply_firmware(tp);
0747 
0748     ret = phy_read_paged(phydev, 0x0a46, 0x10);
0749     if (ret & BIT(8))
0750         phy_modify_paged(phydev, 0x0bcc, 0x12, BIT(15), 0);
0751     else
0752         phy_modify_paged(phydev, 0x0bcc, 0x12, 0, BIT(15));
0753 
0754     ret = phy_read_paged(phydev, 0x0a46, 0x13);
0755     if (ret & BIT(8))
0756         phy_modify_paged(phydev, 0x0c41, 0x15, 0, BIT(1));
0757     else
0758         phy_modify_paged(phydev, 0x0c41, 0x15, BIT(1), 0);
0759 
0760     /* Enable PHY auto speed down */
0761     phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
0762 
0763     rtl8168g_phy_adjust_10m_aldps(phydev);
0764 
0765     /* EEE auto-fallback function */
0766     phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2));
0767 
0768     /* Enable UC LPF tune function */
0769     r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000);
0770 
0771     phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14));
0772 
0773     /* Improve SWR Efficiency */
0774     phy_write(phydev, 0x1f, 0x0bcd);
0775     phy_write(phydev, 0x14, 0x5065);
0776     phy_write(phydev, 0x14, 0xd065);
0777     phy_write(phydev, 0x1f, 0x0bc8);
0778     phy_write(phydev, 0x11, 0x5655);
0779     phy_write(phydev, 0x1f, 0x0bcd);
0780     phy_write(phydev, 0x14, 0x1065);
0781     phy_write(phydev, 0x14, 0x9065);
0782     phy_write(phydev, 0x14, 0x1065);
0783     phy_write(phydev, 0x1f, 0x0000);
0784 
0785     rtl8168g_disable_aldps(phydev);
0786     rtl8168g_config_eee_phy(phydev);
0787 }
0788 
0789 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp,
0790                      struct phy_device *phydev)
0791 {
0792     r8169_apply_firmware(tp);
0793     rtl8168g_config_eee_phy(phydev);
0794 }
0795 
0796 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp,
0797                      struct phy_device *phydev)
0798 {
0799     u16 dout_tapbin;
0800     u32 data;
0801 
0802     r8169_apply_firmware(tp);
0803 
0804     /* CHN EST parameters adjust - giga master */
0805     r8168g_phy_param(phydev, 0x809b, 0xf800, 0x8000);
0806     r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x8000);
0807     r8168g_phy_param(phydev, 0x80a4, 0xff00, 0x8500);
0808     r8168g_phy_param(phydev, 0x809c, 0xff00, 0xbd00);
0809 
0810     /* CHN EST parameters adjust - giga slave */
0811     r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x7000);
0812     r8168g_phy_param(phydev, 0x80b4, 0xff00, 0x5000);
0813     r8168g_phy_param(phydev, 0x80ac, 0xff00, 0x4000);
0814 
0815     /* CHN EST parameters adjust - fnet */
0816     r8168g_phy_param(phydev, 0x808e, 0xff00, 0x1200);
0817     r8168g_phy_param(phydev, 0x8090, 0xff00, 0xe500);
0818     r8168g_phy_param(phydev, 0x8092, 0xff00, 0x9f00);
0819 
0820     /* enable R-tune & PGA-retune function */
0821     dout_tapbin = 0;
0822     data = phy_read_paged(phydev, 0x0a46, 0x13);
0823     data &= 3;
0824     data <<= 2;
0825     dout_tapbin |= data;
0826     data = phy_read_paged(phydev, 0x0a46, 0x12);
0827     data &= 0xc000;
0828     data >>= 14;
0829     dout_tapbin |= data;
0830     dout_tapbin = ~(dout_tapbin ^ 0x08);
0831     dout_tapbin <<= 12;
0832     dout_tapbin &= 0xf000;
0833 
0834     r8168g_phy_param(phydev, 0x827a, 0xf000, dout_tapbin);
0835     r8168g_phy_param(phydev, 0x827b, 0xf000, dout_tapbin);
0836     r8168g_phy_param(phydev, 0x827c, 0xf000, dout_tapbin);
0837     r8168g_phy_param(phydev, 0x827d, 0xf000, dout_tapbin);
0838     r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800);
0839     phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002);
0840 
0841     rtl8168g_enable_gphy_10m(phydev);
0842 
0843     /* SAR ADC performance */
0844     phy_modify_paged(phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
0845 
0846     r8168g_phy_param(phydev, 0x803f, 0x3000, 0x0000);
0847     r8168g_phy_param(phydev, 0x8047, 0x3000, 0x0000);
0848     r8168g_phy_param(phydev, 0x804f, 0x3000, 0x0000);
0849     r8168g_phy_param(phydev, 0x8057, 0x3000, 0x0000);
0850     r8168g_phy_param(phydev, 0x805f, 0x3000, 0x0000);
0851     r8168g_phy_param(phydev, 0x8067, 0x3000, 0x0000);
0852     r8168g_phy_param(phydev, 0x806f, 0x3000, 0x0000);
0853 
0854     /* disable phy pfm mode */
0855     phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0);
0856 
0857     rtl8168g_disable_aldps(phydev);
0858     rtl8168h_config_eee_phy(phydev);
0859 }
0860 
0861 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp,
0862                      struct phy_device *phydev)
0863 {
0864     u16 ioffset, rlen;
0865     u32 data;
0866 
0867     r8169_apply_firmware(tp);
0868 
0869     /* CHIN EST parameter update */
0870     r8168g_phy_param(phydev, 0x808a, 0x003f, 0x000a);
0871 
0872     /* enable R-tune & PGA-retune function */
0873     r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800);
0874     phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002);
0875 
0876     rtl8168g_enable_gphy_10m(phydev);
0877 
0878     ioffset = rtl8168h_2_get_adc_bias_ioffset(tp);
0879     if (ioffset != 0xffff)
0880         phy_write_paged(phydev, 0x0bcf, 0x16, ioffset);
0881 
0882     /* Modify rlen (TX LPF corner frequency) level */
0883     data = phy_read_paged(phydev, 0x0bcd, 0x16);
0884     data &= 0x000f;
0885     rlen = 0;
0886     if (data > 3)
0887         rlen = data - 3;
0888     data = rlen | (rlen << 4) | (rlen << 8) | (rlen << 12);
0889     phy_write_paged(phydev, 0x0bcd, 0x17, data);
0890 
0891     /* disable phy pfm mode */
0892     phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0);
0893 
0894     rtl8168g_disable_aldps(phydev);
0895     rtl8168g_config_eee_phy(phydev);
0896 }
0897 
0898 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp,
0899                       struct phy_device *phydev)
0900 {
0901     /* Enable PHY auto speed down */
0902     phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
0903 
0904     rtl8168g_phy_adjust_10m_aldps(phydev);
0905 
0906     /* Enable EEE auto-fallback function */
0907     phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2));
0908 
0909     /* Enable UC LPF tune function */
0910     r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000);
0911 
0912     /* set rg_sel_sdm_rate */
0913     phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14));
0914 
0915     rtl8168g_disable_aldps(phydev);
0916     rtl8168g_config_eee_phy(phydev);
0917 }
0918 
0919 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp,
0920                       struct phy_device *phydev)
0921 {
0922     rtl8168g_phy_adjust_10m_aldps(phydev);
0923 
0924     /* Enable UC LPF tune function */
0925     r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000);
0926 
0927     /* Set rg_sel_sdm_rate */
0928     phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14));
0929 
0930     /* Channel estimation parameters */
0931     r8168g_phy_param(phydev, 0x80f3, 0xff00, 0x8b00);
0932     r8168g_phy_param(phydev, 0x80f0, 0xff00, 0x3a00);
0933     r8168g_phy_param(phydev, 0x80ef, 0xff00, 0x0500);
0934     r8168g_phy_param(phydev, 0x80f6, 0xff00, 0x6e00);
0935     r8168g_phy_param(phydev, 0x80ec, 0xff00, 0x6800);
0936     r8168g_phy_param(phydev, 0x80ed, 0xff00, 0x7c00);
0937     r8168g_phy_param(phydev, 0x80f2, 0xff00, 0xf400);
0938     r8168g_phy_param(phydev, 0x80f4, 0xff00, 0x8500);
0939     r8168g_phy_param(phydev, 0x8110, 0xff00, 0xa800);
0940     r8168g_phy_param(phydev, 0x810f, 0xff00, 0x1d00);
0941     r8168g_phy_param(phydev, 0x8111, 0xff00, 0xf500);
0942     r8168g_phy_param(phydev, 0x8113, 0xff00, 0x6100);
0943     r8168g_phy_param(phydev, 0x8115, 0xff00, 0x9200);
0944     r8168g_phy_param(phydev, 0x810e, 0xff00, 0x0400);
0945     r8168g_phy_param(phydev, 0x810c, 0xff00, 0x7c00);
0946     r8168g_phy_param(phydev, 0x810b, 0xff00, 0x5a00);
0947     r8168g_phy_param(phydev, 0x80d1, 0xff00, 0xff00);
0948     r8168g_phy_param(phydev, 0x80cd, 0xff00, 0x9e00);
0949     r8168g_phy_param(phydev, 0x80d3, 0xff00, 0x0e00);
0950     r8168g_phy_param(phydev, 0x80d5, 0xff00, 0xca00);
0951     r8168g_phy_param(phydev, 0x80d7, 0xff00, 0x8400);
0952 
0953     /* Force PWM-mode */
0954     phy_write(phydev, 0x1f, 0x0bcd);
0955     phy_write(phydev, 0x14, 0x5065);
0956     phy_write(phydev, 0x14, 0xd065);
0957     phy_write(phydev, 0x1f, 0x0bc8);
0958     phy_write(phydev, 0x12, 0x00ed);
0959     phy_write(phydev, 0x1f, 0x0bcd);
0960     phy_write(phydev, 0x14, 0x1065);
0961     phy_write(phydev, 0x14, 0x9065);
0962     phy_write(phydev, 0x14, 0x1065);
0963     phy_write(phydev, 0x1f, 0x0000);
0964 
0965     rtl8168g_disable_aldps(phydev);
0966     rtl8168g_config_eee_phy(phydev);
0967 }
0968 
0969 static void rtl8117_hw_phy_config(struct rtl8169_private *tp,
0970                   struct phy_device *phydev)
0971 {
0972     /* CHN EST parameters adjust - fnet */
0973     r8168g_phy_param(phydev, 0x808e, 0xff00, 0x4800);
0974     r8168g_phy_param(phydev, 0x8090, 0xff00, 0xcc00);
0975     r8168g_phy_param(phydev, 0x8092, 0xff00, 0xb000);
0976 
0977     r8168g_phy_param(phydev, 0x8088, 0xff00, 0x6000);
0978     r8168g_phy_param(phydev, 0x808b, 0x3f00, 0x0b00);
0979     r8168g_phy_param(phydev, 0x808d, 0x1f00, 0x0600);
0980     r8168g_phy_param(phydev, 0x808c, 0xff00, 0xb000);
0981     r8168g_phy_param(phydev, 0x80a0, 0xff00, 0x2800);
0982     r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x5000);
0983     r8168g_phy_param(phydev, 0x809b, 0xf800, 0xb000);
0984     r8168g_phy_param(phydev, 0x809a, 0xff00, 0x4b00);
0985     r8168g_phy_param(phydev, 0x809d, 0x3f00, 0x0800);
0986     r8168g_phy_param(phydev, 0x80a1, 0xff00, 0x7000);
0987     r8168g_phy_param(phydev, 0x809f, 0x1f00, 0x0300);
0988     r8168g_phy_param(phydev, 0x809e, 0xff00, 0x8800);
0989     r8168g_phy_param(phydev, 0x80b2, 0xff00, 0x2200);
0990     r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x9800);
0991     r8168g_phy_param(phydev, 0x80af, 0x3f00, 0x0800);
0992     r8168g_phy_param(phydev, 0x80b3, 0xff00, 0x6f00);
0993     r8168g_phy_param(phydev, 0x80b1, 0x1f00, 0x0300);
0994     r8168g_phy_param(phydev, 0x80b0, 0xff00, 0x9300);
0995 
0996     r8168g_phy_param(phydev, 0x8011, 0x0000, 0x0800);
0997 
0998     rtl8168g_enable_gphy_10m(phydev);
0999 
1000     r8168g_phy_param(phydev, 0x8016, 0x0000, 0x0400);
1001 
1002     rtl8168g_disable_aldps(phydev);
1003     rtl8168h_config_eee_phy(phydev);
1004 }
1005 
1006 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp,
1007                    struct phy_device *phydev)
1008 {
1009     static const struct phy_reg phy_reg_init[] = {
1010         { 0x1f, 0x0003 },
1011         { 0x08, 0x441d },
1012         { 0x01, 0x9100 },
1013         { 0x1f, 0x0000 }
1014     };
1015 
1016     phy_set_bits(phydev, 0x11, BIT(12));
1017     phy_set_bits(phydev, 0x19, BIT(13));
1018     phy_set_bits(phydev, 0x10, BIT(15));
1019 
1020     rtl_writephy_batch(phydev, phy_reg_init);
1021 }
1022 
1023 static void rtl8401_hw_phy_config(struct rtl8169_private *tp,
1024                   struct phy_device *phydev)
1025 {
1026     phy_set_bits(phydev, 0x11, BIT(12));
1027     phy_modify_paged(phydev, 0x0002, 0x0f, 0x0000, 0x0003);
1028 }
1029 
1030 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp,
1031                    struct phy_device *phydev)
1032 {
1033     /* Disable ALDPS before ram code */
1034     phy_write(phydev, 0x18, 0x0310);
1035     msleep(100);
1036 
1037     r8169_apply_firmware(tp);
1038 
1039     phy_write_paged(phydev, 0x0005, 0x1a, 0x0000);
1040     phy_write_paged(phydev, 0x0004, 0x1c, 0x0000);
1041     phy_write_paged(phydev, 0x0001, 0x15, 0x7701);
1042 }
1043 
1044 static void rtl8402_hw_phy_config(struct rtl8169_private *tp,
1045                   struct phy_device *phydev)
1046 {
1047     /* Disable ALDPS before setting firmware */
1048     phy_write(phydev, 0x18, 0x0310);
1049     msleep(20);
1050 
1051     r8169_apply_firmware(tp);
1052 
1053     /* EEE setting */
1054     phy_write(phydev, 0x1f, 0x0004);
1055     phy_write(phydev, 0x10, 0x401f);
1056     phy_write(phydev, 0x19, 0x7030);
1057     phy_write(phydev, 0x1f, 0x0000);
1058 }
1059 
1060 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp,
1061                    struct phy_device *phydev)
1062 {
1063     static const struct phy_reg phy_reg_init[] = {
1064         { 0x1f, 0x0004 },
1065         { 0x10, 0xc07f },
1066         { 0x19, 0x7030 },
1067         { 0x1f, 0x0000 }
1068     };
1069 
1070     /* Disable ALDPS before ram code */
1071     phy_write(phydev, 0x18, 0x0310);
1072     msleep(100);
1073 
1074     r8169_apply_firmware(tp);
1075 
1076     rtl_writephy_batch(phydev, phy_reg_init);
1077 }
1078 
1079 static void rtl8125_legacy_force_mode(struct phy_device *phydev)
1080 {
1081     phy_modify_paged(phydev, 0xa5b, 0x12, BIT(15), 0);
1082 }
1083 
1084 static void rtl8125a_1_hw_phy_config(struct rtl8169_private *tp,
1085                      struct phy_device *phydev)
1086 {
1087     phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084);
1088     phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
1089     phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006);
1090     phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
1091     phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100);
1092     phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000);
1093     phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400);
1094     phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff);
1095     phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff);
1096 
1097     r8168g_phy_param(phydev, 0x80ea, 0xff00, 0xc400);
1098     r8168g_phy_param(phydev, 0x80eb, 0x0700, 0x0300);
1099     r8168g_phy_param(phydev, 0x80f8, 0xff00, 0x1c00);
1100     r8168g_phy_param(phydev, 0x80f1, 0xff00, 0x3000);
1101     r8168g_phy_param(phydev, 0x80fe, 0xff00, 0xa500);
1102     r8168g_phy_param(phydev, 0x8102, 0xff00, 0x5000);
1103     r8168g_phy_param(phydev, 0x8105, 0xff00, 0x3300);
1104     r8168g_phy_param(phydev, 0x8100, 0xff00, 0x7000);
1105     r8168g_phy_param(phydev, 0x8104, 0xff00, 0xf000);
1106     r8168g_phy_param(phydev, 0x8106, 0xff00, 0x6500);
1107     r8168g_phy_param(phydev, 0x80dc, 0xff00, 0xed00);
1108     r8168g_phy_param(phydev, 0x80df, 0x0000, 0x0100);
1109     r8168g_phy_param(phydev, 0x80e1, 0x0100, 0x0000);
1110 
1111     phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038);
1112     r8168g_phy_param(phydev, 0x819f, 0xffff, 0xd0b6);
1113 
1114     phy_write_paged(phydev, 0xbc3, 0x12, 0x5555);
1115     phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00);
1116     phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000);
1117     rtl8168g_enable_gphy_10m(phydev);
1118 
1119     rtl8125a_config_eee_phy(phydev);
1120 }
1121 
1122 static void rtl8125a_2_hw_phy_config(struct rtl8169_private *tp,
1123                      struct phy_device *phydev)
1124 {
1125     int i;
1126 
1127     phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
1128     phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff);
1129     phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
1130     phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000);
1131     phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002);
1132     phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044);
1133     phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000);
1134     phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000);
1135     phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002);
1136     phy_write_paged(phydev, 0xad4, 0x16, 0x00a8);
1137     phy_write_paged(phydev, 0xac5, 0x16, 0x01ff);
1138     phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030);
1139 
1140     phy_write(phydev, 0x1f, 0x0b87);
1141     phy_write(phydev, 0x16, 0x80a2);
1142     phy_write(phydev, 0x17, 0x0153);
1143     phy_write(phydev, 0x16, 0x809c);
1144     phy_write(phydev, 0x17, 0x0153);
1145     phy_write(phydev, 0x1f, 0x0000);
1146 
1147     phy_write(phydev, 0x1f, 0x0a43);
1148     phy_write(phydev, 0x13, 0x81B3);
1149     phy_write(phydev, 0x14, 0x0043);
1150     phy_write(phydev, 0x14, 0x00A7);
1151     phy_write(phydev, 0x14, 0x00D6);
1152     phy_write(phydev, 0x14, 0x00EC);
1153     phy_write(phydev, 0x14, 0x00F6);
1154     phy_write(phydev, 0x14, 0x00FB);
1155     phy_write(phydev, 0x14, 0x00FD);
1156     phy_write(phydev, 0x14, 0x00FF);
1157     phy_write(phydev, 0x14, 0x00BB);
1158     phy_write(phydev, 0x14, 0x0058);
1159     phy_write(phydev, 0x14, 0x0029);
1160     phy_write(phydev, 0x14, 0x0013);
1161     phy_write(phydev, 0x14, 0x0009);
1162     phy_write(phydev, 0x14, 0x0004);
1163     phy_write(phydev, 0x14, 0x0002);
1164     for (i = 0; i < 25; i++)
1165         phy_write(phydev, 0x14, 0x0000);
1166     phy_write(phydev, 0x1f, 0x0000);
1167 
1168     r8168g_phy_param(phydev, 0x8257, 0xffff, 0x020F);
1169     r8168g_phy_param(phydev, 0x80ea, 0xffff, 0x7843);
1170 
1171     r8169_apply_firmware(tp);
1172 
1173     phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000);
1174 
1175     r8168g_phy_param(phydev, 0x81a2, 0x0000, 0x0100);
1176 
1177     phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00);
1178     phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000);
1179     phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020);
1180     phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000);
1181     phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000);
1182     rtl8168g_enable_gphy_10m(phydev);
1183 
1184     rtl8125a_config_eee_phy(phydev);
1185 }
1186 
1187 static void rtl8125b_hw_phy_config(struct rtl8169_private *tp,
1188                    struct phy_device *phydev)
1189 {
1190     r8169_apply_firmware(tp);
1191 
1192     phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
1193     phy_modify_paged(phydev, 0xac4, 0x13, 0x00f0, 0x0090);
1194     phy_modify_paged(phydev, 0xad3, 0x10, 0x0003, 0x0001);
1195 
1196     phy_write(phydev, 0x1f, 0x0b87);
1197     phy_write(phydev, 0x16, 0x80f5);
1198     phy_write(phydev, 0x17, 0x760e);
1199     phy_write(phydev, 0x16, 0x8107);
1200     phy_write(phydev, 0x17, 0x360e);
1201     phy_write(phydev, 0x16, 0x8551);
1202     phy_modify(phydev, 0x17, 0xff00, 0x0800);
1203     phy_write(phydev, 0x1f, 0x0000);
1204 
1205     phy_modify_paged(phydev, 0xbf0, 0x10, 0xe000, 0xa000);
1206     phy_modify_paged(phydev, 0xbf4, 0x13, 0x0f00, 0x0300);
1207 
1208     r8168g_phy_param(phydev, 0x8044, 0xffff, 0x2417);
1209     r8168g_phy_param(phydev, 0x804a, 0xffff, 0x2417);
1210     r8168g_phy_param(phydev, 0x8050, 0xffff, 0x2417);
1211     r8168g_phy_param(phydev, 0x8056, 0xffff, 0x2417);
1212     r8168g_phy_param(phydev, 0x805c, 0xffff, 0x2417);
1213     r8168g_phy_param(phydev, 0x8062, 0xffff, 0x2417);
1214     r8168g_phy_param(phydev, 0x8068, 0xffff, 0x2417);
1215     r8168g_phy_param(phydev, 0x806e, 0xffff, 0x2417);
1216     r8168g_phy_param(phydev, 0x8074, 0xffff, 0x2417);
1217     r8168g_phy_param(phydev, 0x807a, 0xffff, 0x2417);
1218 
1219     phy_modify_paged(phydev, 0xa4c, 0x15, 0x0000, 0x0040);
1220     phy_modify_paged(phydev, 0xbf8, 0x12, 0xe000, 0xa000);
1221 
1222     rtl8125_legacy_force_mode(phydev);
1223     rtl8125b_config_eee_phy(phydev);
1224 }
1225 
1226 void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev,
1227              enum mac_version ver)
1228 {
1229     static const rtl_phy_cfg_fct phy_configs[] = {
1230         /* PCI devices. */
1231         [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
1232         [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
1233         [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
1234         [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
1235         [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
1236         /* PCI-E devices. */
1237         [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
1238         [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
1239         [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
1240         [RTL_GIGA_MAC_VER_10] = NULL,
1241         [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
1242         [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
1243         [RTL_GIGA_MAC_VER_13] = NULL,
1244         [RTL_GIGA_MAC_VER_14] = rtl8401_hw_phy_config,
1245         [RTL_GIGA_MAC_VER_16] = NULL,
1246         [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
1247         [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
1248         [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
1249         [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
1250         [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
1251         [RTL_GIGA_MAC_VER_22] = rtl8168c_3_hw_phy_config,
1252         [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
1253         [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
1254         [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
1255         [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
1256         [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
1257         [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
1258         [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
1259         [RTL_GIGA_MAC_VER_31] = NULL,
1260         [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
1261         [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
1262         [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
1263         [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
1264         [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
1265         [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
1266         [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
1267         [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
1268         [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
1269         [RTL_GIGA_MAC_VER_41] = NULL,
1270         [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
1271         [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
1272         [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
1273         [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
1274         [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
1275         [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
1276         [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
1277         [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
1278         [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
1279         [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
1280         [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config,
1281         [RTL_GIGA_MAC_VER_53] = rtl8117_hw_phy_config,
1282         [RTL_GIGA_MAC_VER_60] = rtl8125a_1_hw_phy_config,
1283         [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config,
1284         [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config,
1285     };
1286 
1287     if (phy_configs[ver])
1288         phy_configs[ver](tp, phydev);
1289 }
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