ethernet/realtek/atp.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Linux header file for the ATP pocket ethernet adapter. */
0003 /* v1.09 8/9/2000 becker@scyld.com. */
0004
0005 #include <linux/if_ether.h>
0006 #include <linux/types.h>
0007
0008 /* The header prepended to received packets. */
0009 struct rx_header {
0010     ushort pad;     /* Pad. */
0011     ushort rx_count;
0012     ushort rx_status;   /* Unknown bit assignments :-<.  */
0013     ushort cur_addr;    /* Apparently the current buffer address(?) */
0014 };
0015
0016 #define PAR_DATA    0
0017 #define PAR_STATUS  1
0018 #define PAR_CONTROL 2
0019
0020 #define Ctrl_LNibRead   0x08    /* LP_PSELECP */
0021 #define Ctrl_HNibRead   0
0022 #define Ctrl_LNibWrite  0x08    /* LP_PSELECP */
0023 #define Ctrl_HNibWrite  0
0024 #define Ctrl_SelData    0x04    /* LP_PINITP */
0025 #define Ctrl_IRQEN  0x10    /* LP_PINTEN */
0026
0027 #define EOW 0xE0
0028 #define EOC 0xE0
0029 #define WrAddr  0x40    /* Set address of EPLC read, write register. */
0030 #define RdAddr  0xC0
0031 #define HNib    0x10
0032
0033 enum page0_regs {
0034     /* The first six registers hold
0035      * the ethernet physical station address.
0036      */
0037     PAR0 = 0, PAR1 = 1, PAR2 = 2, PAR3 = 3, PAR4 = 4, PAR5 = 5,
0038     TxCNT0 = 6, TxCNT1 = 7,     /* The transmit byte count. */
0039     TxSTAT = 8, RxSTAT = 9,     /* Tx and Rx status. */
0040     ISR = 10, IMR = 11,     /* Interrupt status and mask. */
0041     CMR1 = 12,          /* Command register 1. */
0042     CMR2 = 13,          /* Command register 2. */
0043     MODSEL = 14,        /* Mode select register. */
0044     MAR = 14,           /* Memory address register (?). */
0045     CMR2_h = 0x1d,
0046 };
0047
0048 enum eepage_regs {
0049     PROM_CMD = 6,
0050     PROM_DATA = 7   /* Note that PROM_CMD is in the "high" bits. */
0051 };
0052
0053 #define ISR_TxOK    0x01
0054 #define ISR_RxOK    0x04
0055 #define ISR_TxErr   0x02
0056 #define ISRh_RxErr  0x11    /* ISR, high nibble */
0057
0058 #define CMR1h_MUX   0x08    /* Select printer multiplexor on 8012. */
0059 #define CMR1h_RESET 0x04    /* Reset. */
0060 #define CMR1h_RxENABLE  0x02    /* Rx unit enable.  */
0061 #define CMR1h_TxENABLE  0x01    /* Tx unit enable.  */
0062 #define CMR1h_TxRxOFF   0x00
0063 #define CMR1_ReXmit 0x08    /* Trigger a retransmit. */
0064 #define CMR1_Xmit   0x04    /* Trigger a transmit. */
0065 #define CMR1_IRQ    0x02    /* Interrupt active. */
0066 #define CMR1_BufEnb 0x01    /* Enable the buffer(?). */
0067 #define CMR1_NextPkt    0x01    /* Enable the buffer(?). */
0068
0069 #define CMR2_NULL   8
0070 #define CMR2_IRQOUT 9
0071 #define CMR2_RAMTEST    10
0072 #define CMR2_EEPROM 12  /* Set to page 1, for reading the EEPROM. */
0073
0074 #define CMR2h_OFF   0   /* No accept mode. */
0075 #define CMR2h_Physical  1   /* Accept a physical address match only. */
0076 #define CMR2h_Normal    2   /* Accept physical and broadcast address. */
0077 #define CMR2h_PROMISC   3   /* Promiscuous mode. */
0078
0079 /* An inline function used below: it differs from inb() by explicitly
0080  * return an unsigned char, saving a truncation.
0081  */
0082 static inline unsigned char inbyte(unsigned short port)
0083 {
0084     unsigned char _v;
0085
0086     __asm__ __volatile__ ("inb %w1,%b0" : "=a" (_v) : "d" (port));
0087     return _v;
0088 }
0089
0090 /* Read register OFFSET.
0091  * This command should always be terminated with read_end().
0092  */
0093 static inline unsigned char read_nibble(short port, unsigned char offset)
0094 {
0095     unsigned char retval;
0096
0097     outb(EOC+offset, port + PAR_DATA);
0098     outb(RdAddr+offset, port + PAR_DATA);
0099     inbyte(port + PAR_STATUS);  /* Settling time delay */
0100     retval = inbyte(port + PAR_STATUS);
0101     outb(EOC+offset, port + PAR_DATA);
0102
0103     return retval;
0104 }
0105
0106 /* Functions for bulk data read.  The interrupt line is always disabled. */
0107 /* Get a byte using read mode 0, reading data from the control lines. */
0108 static inline unsigned char read_byte_mode0(short ioaddr)
0109 {
0110     unsigned char low_nib;
0111
0112     outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
0113     inbyte(ioaddr + PAR_STATUS);
0114     low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
0115     outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
0116     inbyte(ioaddr + PAR_STATUS);    /* Settling time delay -- needed!  */
0117     inbyte(ioaddr + PAR_STATUS);    /* Settling time delay -- needed!  */
0118     return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
0119 }
0120
0121 /* The same as read_byte_mode0(), but does multiple inb()s for stability. */
0122 static inline unsigned char read_byte_mode2(short ioaddr)
0123 {
0124     unsigned char low_nib;
0125
0126     outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
0127     inbyte(ioaddr + PAR_STATUS);
0128     low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
0129     outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
0130     inbyte(ioaddr + PAR_STATUS);    /* Settling time delay -- needed!  */
0131     return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
0132 }
0133
0134 /* Read a byte through the data register. */
0135 static inline unsigned char read_byte_mode4(short ioaddr)
0136 {
0137     unsigned char low_nib;
0138
0139     outb(RdAddr | MAR, ioaddr + PAR_DATA);
0140     low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
0141     outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
0142     return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
0143 }
0144
0145 /* Read a byte through the data register, double reading to allow settling. */
0146 static inline unsigned char read_byte_mode6(short ioaddr)
0147 {
0148     unsigned char low_nib;
0149
0150     outb(RdAddr | MAR, ioaddr + PAR_DATA);
0151     inbyte(ioaddr + PAR_STATUS);
0152     low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
0153     outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
0154     inbyte(ioaddr + PAR_STATUS);
0155     return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
0156 }
0157
0158 static inline void
0159 write_reg(short port, unsigned char reg, unsigned char value)
0160 {
0161     unsigned char outval;
0162
0163     outb(EOC | reg, port + PAR_DATA);
0164     outval = WrAddr | reg;
0165     outb(outval, port + PAR_DATA);
0166     outb(outval, port + PAR_DATA);  /* Double write for PS/2. */
0167
0168     outval &= 0xf0;
0169     outval |= value;
0170     outb(outval, port + PAR_DATA);
0171     outval &= 0x1f;
0172     outb(outval, port + PAR_DATA);
0173     outb(outval, port + PAR_DATA);
0174
0175     outb(EOC | outval, port + PAR_DATA);
0176 }
0177
0178 static inline void
0179 write_reg_high(short port, unsigned char reg, unsigned char value)
0180 {
0181     unsigned char outval = EOC | HNib | reg;
0182
0183     outb(outval, port + PAR_DATA);
0184     outval &= WrAddr | HNib | 0x0f;
0185     outb(outval, port + PAR_DATA);
0186     outb(outval, port + PAR_DATA);  /* Double write for PS/2. */
0187
0188     outval = WrAddr | HNib | value;
0189     outb(outval, port + PAR_DATA);
0190     outval &= HNib | 0x0f;      /* HNib | value */
0191     outb(outval, port + PAR_DATA);
0192     outb(outval, port + PAR_DATA);
0193
0194     outb(EOC | HNib | outval, port + PAR_DATA);
0195 }
0196
0197 /* Write a byte out using nibble mode.  The low nibble is written first. */
0198 static inline void
0199 write_reg_byte(short port, unsigned char reg, unsigned char value)
0200 {
0201     unsigned char outval;
0202
0203     outb(EOC | reg, port + PAR_DATA); /* Reset the address register. */
0204     outval = WrAddr | reg;
0205     outb(outval, port + PAR_DATA);
0206     outb(outval, port + PAR_DATA);  /* Double write for PS/2. */
0207
0208     outb((outval & 0xf0) | (value & 0x0f), port + PAR_DATA);
0209     outb(value & 0x0f, port + PAR_DATA);
0210     value >>= 4;
0211     outb(value, port + PAR_DATA);
0212     outb(0x10 | value, port + PAR_DATA);
0213     outb(0x10 | value, port + PAR_DATA);
0214
0215     outb(EOC  | value, port + PAR_DATA); /* Reset the address register. */
0216 }
0217
0218 /* Bulk data writes to the packet buffer.  The interrupt line remains enabled.
0219  * The first, faster method uses only the dataport (data modes 0, 2 & 4).
0220  * The second (backup) method uses data and control regs (modes 1, 3 & 5).
0221  * It should only be needed when there is skew between the individual data
0222  * lines.
0223  */
0224 static inline void write_byte_mode0(short ioaddr, unsigned char value)
0225 {
0226     outb(value & 0x0f, ioaddr + PAR_DATA);
0227     outb((value>>4) | 0x10, ioaddr + PAR_DATA);
0228 }
0229
0230 static inline void write_byte_mode1(short ioaddr, unsigned char value)
0231 {
0232     outb(value & 0x0f, ioaddr + PAR_DATA);
0233     outb(Ctrl_IRQEN | Ctrl_LNibWrite, ioaddr + PAR_CONTROL);
0234     outb((value>>4) | 0x10, ioaddr + PAR_DATA);
0235     outb(Ctrl_IRQEN | Ctrl_HNibWrite, ioaddr + PAR_CONTROL);
0236 }
0237
0238 /* Write 16bit VALUE to the packet buffer: the same as above just doubled. */
0239 static inline void write_word_mode0(short ioaddr, unsigned short value)
0240 {
0241     outb(value & 0x0f, ioaddr + PAR_DATA);
0242     value >>= 4;
0243     outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
0244     value >>= 4;
0245     outb(value & 0x0f, ioaddr + PAR_DATA);
0246     value >>= 4;
0247     outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
0248 }
0249
0250 /*  EEPROM_Ctrl bits. */
0251 #define EE_SHIFT_CLK    0x04    /* EEPROM shift clock. */
0252 #define EE_CS       0x02    /* EEPROM chip select. */
0253 #define EE_CLK_HIGH 0x12
0254 #define EE_CLK_LOW  0x16
0255 #define EE_DATA_WRITE   0x01    /* EEPROM chip data in. */
0256 #define EE_DATA_READ    0x08    /* EEPROM chip data out. */
0257
0258 /* The EEPROM commands include the alway-set leading bit. */
0259 #define EE_WRITE_CMD(offset)    (((5 << 6) + (offset)) << 17)
0260 #define EE_READ(offset)     (((6 << 6) + (offset)) << 17)
0261 #define EE_ERASE(offset)    (((7 << 6) + (offset)) << 17)
0262 #define EE_CMD_SIZE 27  /* The command+address+data size. */