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0034 static const char version[] =
0035 "atp.c:v1.09=ac 2002/10/01 Donald Becker <becker@scyld.com>\n";
0036
0037
0038
0039
0040 static int debug = 1;
0041 #define net_debug debug
0042
0043
0044 static int max_interrupt_work = 15;
0045
0046 #define NUM_UNITS 2
0047
0048 static int io[NUM_UNITS];
0049 static int irq[NUM_UNITS];
0050 static int xcvr[NUM_UNITS];
0051
0052
0053
0054
0055 #define TX_TIMEOUT (400*HZ/1000)
0056
0057
0058
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0125 #include <linux/kernel.h>
0126 #include <linux/module.h>
0127 #include <linux/types.h>
0128 #include <linux/fcntl.h>
0129 #include <linux/interrupt.h>
0130 #include <linux/ioport.h>
0131 #include <linux/in.h>
0132 #include <linux/string.h>
0133 #include <linux/errno.h>
0134 #include <linux/init.h>
0135 #include <linux/crc32.h>
0136 #include <linux/netdevice.h>
0137 #include <linux/etherdevice.h>
0138 #include <linux/skbuff.h>
0139 #include <linux/spinlock.h>
0140 #include <linux/delay.h>
0141 #include <linux/bitops.h>
0142
0143 #include <asm/io.h>
0144 #include <asm/dma.h>
0145
0146 #include "atp.h"
0147
0148 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
0149 MODULE_DESCRIPTION("RealTek RTL8002/8012 parallel port Ethernet driver");
0150 MODULE_LICENSE("GPL");
0151
0152 module_param(max_interrupt_work, int, 0);
0153 module_param(debug, int, 0);
0154 module_param_hw_array(io, int, ioport, NULL, 0);
0155 module_param_hw_array(irq, int, irq, NULL, 0);
0156 module_param_array(xcvr, int, NULL, 0);
0157 MODULE_PARM_DESC(max_interrupt_work, "ATP maximum events handled per interrupt");
0158 MODULE_PARM_DESC(debug, "ATP debug level (0-7)");
0159 MODULE_PARM_DESC(io, "ATP I/O base address(es)");
0160 MODULE_PARM_DESC(irq, "ATP IRQ number(s)");
0161 MODULE_PARM_DESC(xcvr, "ATP transceiver(s) (0=internal, 1=external)");
0162
0163
0164 #define ETHERCARD_TOTAL_SIZE 3
0165
0166
0167 static char mux_8012[] = { 0xff, 0xf7, 0xff, 0xfb, 0xf3, 0xfb, 0xff, 0xf7,};
0168
0169 struct net_local {
0170 spinlock_t lock;
0171 struct net_device *next_module;
0172 struct timer_list timer;
0173 struct net_device *dev;
0174 unsigned long last_rx_time;
0175 int saved_tx_size;
0176 unsigned int tx_unit_busy:1;
0177 unsigned char re_tx,
0178 addr_mode,
0179 pac_cnt_in_tx_buf;
0180 };
0181
0182
0183
0184
0185 #define TIMED_CHECKER (HZ/4)
0186 #ifdef TIMED_CHECKER
0187 #include <linux/timer.h>
0188 static void atp_timed_checker(struct timer_list *t);
0189 #endif
0190
0191
0192
0193 static int atp_probe1(long ioaddr);
0194 static void get_node_ID(struct net_device *dev);
0195 static unsigned short eeprom_op(long ioaddr, unsigned int cmd);
0196 static int net_open(struct net_device *dev);
0197 static void hardware_init(struct net_device *dev);
0198 static void write_packet(long ioaddr, int length, unsigned char *packet, int pad, int mode);
0199 static void trigger_send(long ioaddr, int length);
0200 static netdev_tx_t atp_send_packet(struct sk_buff *skb,
0201 struct net_device *dev);
0202 static irqreturn_t atp_interrupt(int irq, void *dev_id);
0203 static void net_rx(struct net_device *dev);
0204 static void read_block(long ioaddr, int length, unsigned char *buffer, int data_mode);
0205 static int net_close(struct net_device *dev);
0206 static void set_rx_mode(struct net_device *dev);
0207 static void tx_timeout(struct net_device *dev, unsigned int txqueue);
0208
0209
0210
0211 static struct net_device *root_atp_dev;
0212
0213
0214
0215
0216
0217
0218
0219
0220
0221 static int __init atp_init(void)
0222 {
0223 int *port, ports[] = {0x378, 0x278, 0x3bc, 0};
0224 int base_addr = io[0];
0225
0226 if (base_addr > 0x1ff)
0227 return atp_probe1(base_addr);
0228 else if (base_addr == 1)
0229 return -ENXIO;
0230
0231 for (port = ports; *port; port++) {
0232 long ioaddr = *port;
0233 outb(0x57, ioaddr + PAR_DATA);
0234 if (inb(ioaddr + PAR_DATA) != 0x57)
0235 continue;
0236 if (atp_probe1(ioaddr) == 0)
0237 return 0;
0238 }
0239
0240 return -ENODEV;
0241 }
0242
0243 static const struct net_device_ops atp_netdev_ops = {
0244 .ndo_open = net_open,
0245 .ndo_stop = net_close,
0246 .ndo_start_xmit = atp_send_packet,
0247 .ndo_set_rx_mode = set_rx_mode,
0248 .ndo_tx_timeout = tx_timeout,
0249 .ndo_set_mac_address = eth_mac_addr,
0250 .ndo_validate_addr = eth_validate_addr,
0251 };
0252
0253 static int __init atp_probe1(long ioaddr)
0254 {
0255 struct net_device *dev = NULL;
0256 struct net_local *lp;
0257 int saved_ctrl_reg, status, i;
0258 int res;
0259
0260 outb(0xff, ioaddr + PAR_DATA);
0261
0262
0263 saved_ctrl_reg = inb(ioaddr + PAR_CONTROL);
0264 if (net_debug > 3)
0265 printk("atp: Control register was %#2.2x.\n", saved_ctrl_reg);
0266
0267 outb(0x04, ioaddr + PAR_CONTROL);
0268 #ifndef final_version
0269 if (net_debug > 3) {
0270
0271 for (i = 0; i < 8; i++)
0272 outb(mux_8012[i], ioaddr + PAR_DATA);
0273 write_reg(ioaddr, MODSEL, 0x00);
0274 printk("atp: Registers are ");
0275 for (i = 0; i < 32; i++)
0276 printk(" %2.2x", read_nibble(ioaddr, i));
0277 printk(".\n");
0278 }
0279 #endif
0280
0281 for (i = 0; i < 8; i++)
0282 outb(mux_8012[i], ioaddr + PAR_DATA);
0283 write_reg_high(ioaddr, CMR1, CMR1h_RESET);
0284
0285 status = read_nibble(ioaddr, CMR1);
0286
0287 if (net_debug > 3) {
0288 printk(KERN_DEBUG "atp: Status nibble was %#2.2x..", status);
0289 for (i = 0; i < 32; i++)
0290 printk(" %2.2x", read_nibble(ioaddr, i));
0291 printk("\n");
0292 }
0293
0294 if ((status & 0x78) != 0x08) {
0295
0296 outb(saved_ctrl_reg, ioaddr + PAR_CONTROL);
0297 return -ENODEV;
0298 }
0299 status = read_nibble(ioaddr, CMR2_h);
0300 if ((status & 0x78) != 0x10) {
0301 outb(saved_ctrl_reg, ioaddr + PAR_CONTROL);
0302 return -ENODEV;
0303 }
0304
0305 dev = alloc_etherdev(sizeof(struct net_local));
0306 if (!dev)
0307 return -ENOMEM;
0308
0309
0310 write_reg_byte(ioaddr, CMR2, 0x01);
0311 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
0312
0313
0314 if (irq[0])
0315 dev->irq = irq[0];
0316 else if (ioaddr == 0x378)
0317 dev->irq = 7;
0318 else
0319 dev->irq = 5;
0320 write_reg_high(ioaddr, CMR1, CMR1h_TxRxOFF);
0321 write_reg(ioaddr, CMR2, CMR2_NULL);
0322
0323 dev->base_addr = ioaddr;
0324
0325
0326 get_node_ID(dev);
0327
0328 #ifndef MODULE
0329 if (net_debug)
0330 printk(KERN_INFO "%s", version);
0331 #endif
0332
0333 printk(KERN_NOTICE "%s: Pocket adapter found at %#3lx, IRQ %d, "
0334 "SAPROM %pM.\n",
0335 dev->name, dev->base_addr, dev->irq, dev->dev_addr);
0336
0337
0338 write_reg_high(ioaddr, CMR1, CMR1h_RESET | CMR1h_MUX);
0339
0340 lp = netdev_priv(dev);
0341 lp->addr_mode = CMR2h_Normal;
0342 spin_lock_init(&lp->lock);
0343
0344
0345 if (xcvr[0])
0346 dev->if_port = xcvr[0];
0347 else
0348 dev->if_port = (dev->mem_start & 0xf) ? (dev->mem_start & 0x7) : 4;
0349 if (dev->mem_end & 0xf)
0350 net_debug = dev->mem_end & 7;
0351
0352 dev->netdev_ops = &atp_netdev_ops;
0353 dev->watchdog_timeo = TX_TIMEOUT;
0354
0355 res = register_netdev(dev);
0356 if (res) {
0357 free_netdev(dev);
0358 return res;
0359 }
0360
0361 lp->next_module = root_atp_dev;
0362 root_atp_dev = dev;
0363
0364 return 0;
0365 }
0366
0367
0368 static void __init get_node_ID(struct net_device *dev)
0369 {
0370 long ioaddr = dev->base_addr;
0371 __be16 addr[ETH_ALEN / 2];
0372 int sa_offset = 0;
0373 int i;
0374
0375 write_reg(ioaddr, CMR2, CMR2_EEPROM);
0376
0377
0378
0379 if (eeprom_op(ioaddr, EE_READ(0)) == 0xffff)
0380 sa_offset = 15;
0381
0382 for (i = 0; i < 3; i++)
0383 addr[i] =
0384 cpu_to_be16(eeprom_op(ioaddr, EE_READ(sa_offset + i)));
0385 eth_hw_addr_set(dev, (u8 *)addr);
0386
0387 write_reg(ioaddr, CMR2, CMR2_NULL);
0388 }
0389
0390
0391
0392
0393
0394
0395
0396
0397
0398
0399
0400
0401
0402 static unsigned short __init eeprom_op(long ioaddr, u32 cmd)
0403 {
0404 unsigned eedata_out = 0;
0405 int num_bits = EE_CMD_SIZE;
0406
0407 while (--num_bits >= 0) {
0408 char outval = (cmd & (1<<num_bits)) ? EE_DATA_WRITE : 0;
0409 write_reg_high(ioaddr, PROM_CMD, outval | EE_CLK_LOW);
0410 write_reg_high(ioaddr, PROM_CMD, outval | EE_CLK_HIGH);
0411 eedata_out <<= 1;
0412 if (read_nibble(ioaddr, PROM_DATA) & EE_DATA_READ)
0413 eedata_out++;
0414 }
0415 write_reg_high(ioaddr, PROM_CMD, EE_CLK_LOW & ~EE_CS);
0416 return eedata_out;
0417 }
0418
0419
0420
0421
0422
0423
0424
0425
0426
0427
0428
0429
0430 static int net_open(struct net_device *dev)
0431 {
0432 struct net_local *lp = netdev_priv(dev);
0433 int ret;
0434
0435
0436
0437
0438 ret = request_irq(dev->irq, atp_interrupt, 0, dev->name, dev);
0439 if (ret)
0440 return ret;
0441
0442 hardware_init(dev);
0443
0444 lp->dev = dev;
0445 timer_setup(&lp->timer, atp_timed_checker, 0);
0446 lp->timer.expires = jiffies + TIMED_CHECKER;
0447 add_timer(&lp->timer);
0448
0449 netif_start_queue(dev);
0450 return 0;
0451 }
0452
0453
0454
0455 static void hardware_init(struct net_device *dev)
0456 {
0457 struct net_local *lp = netdev_priv(dev);
0458 long ioaddr = dev->base_addr;
0459 int i;
0460
0461
0462 for (i = 0; i < 8; i++)
0463 outb(mux_8012[i], ioaddr + PAR_DATA);
0464 write_reg_high(ioaddr, CMR1, CMR1h_RESET);
0465
0466 for (i = 0; i < 6; i++)
0467 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]);
0468
0469 write_reg_high(ioaddr, CMR2, lp->addr_mode);
0470
0471 if (net_debug > 2) {
0472 printk(KERN_DEBUG "%s: Reset: current Rx mode %d.\n", dev->name,
0473 (read_nibble(ioaddr, CMR2_h) >> 3) & 0x0f);
0474 }
0475
0476 write_reg(ioaddr, CMR2, CMR2_IRQOUT);
0477 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
0478
0479
0480 outb(Ctrl_SelData + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
0481
0482
0483 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK);
0484 write_reg_high(ioaddr, IMR, ISRh_RxErr);
0485
0486 lp->tx_unit_busy = 0;
0487 lp->pac_cnt_in_tx_buf = 0;
0488 lp->saved_tx_size = 0;
0489 }
0490
0491 static void trigger_send(long ioaddr, int length)
0492 {
0493 write_reg_byte(ioaddr, TxCNT0, length & 0xff);
0494 write_reg(ioaddr, TxCNT1, length >> 8);
0495 write_reg(ioaddr, CMR1, CMR1_Xmit);
0496 }
0497
0498 static void write_packet(long ioaddr, int length, unsigned char *packet, int pad_len, int data_mode)
0499 {
0500 if (length & 1)
0501 {
0502 length++;
0503 pad_len++;
0504 }
0505
0506 outb(EOC+MAR, ioaddr + PAR_DATA);
0507 if ((data_mode & 1) == 0) {
0508
0509 outb(WrAddr+MAR, ioaddr + PAR_DATA);
0510 do {
0511 write_byte_mode0(ioaddr, *packet++);
0512 } while (--length > pad_len) ;
0513 do {
0514 write_byte_mode0(ioaddr, 0);
0515 } while (--length > 0) ;
0516 } else {
0517
0518 unsigned char outbyte = *packet++;
0519
0520 outb(Ctrl_LNibWrite + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
0521 outb(WrAddr+MAR, ioaddr + PAR_DATA);
0522
0523 outb((outbyte & 0x0f)|0x40, ioaddr + PAR_DATA);
0524 outb(outbyte & 0x0f, ioaddr + PAR_DATA);
0525 outbyte >>= 4;
0526 outb(outbyte & 0x0f, ioaddr + PAR_DATA);
0527 outb(Ctrl_HNibWrite + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
0528 while (--length > pad_len)
0529 write_byte_mode1(ioaddr, *packet++);
0530 while (--length > 0)
0531 write_byte_mode1(ioaddr, 0);
0532 }
0533
0534 outb(0xff, ioaddr + PAR_DATA);
0535 outb(Ctrl_HNibWrite | Ctrl_SelData | Ctrl_IRQEN, ioaddr + PAR_CONTROL);
0536 }
0537
0538 static void tx_timeout(struct net_device *dev, unsigned int txqueue)
0539 {
0540 long ioaddr = dev->base_addr;
0541
0542 printk(KERN_WARNING "%s: Transmit timed out, %s?\n", dev->name,
0543 inb(ioaddr + PAR_CONTROL) & 0x10 ? "network cable problem"
0544 : "IRQ conflict");
0545 dev->stats.tx_errors++;
0546
0547 hardware_init(dev);
0548 netif_trans_update(dev);
0549 netif_wake_queue(dev);
0550 dev->stats.tx_errors++;
0551 }
0552
0553 static netdev_tx_t atp_send_packet(struct sk_buff *skb,
0554 struct net_device *dev)
0555 {
0556 struct net_local *lp = netdev_priv(dev);
0557 long ioaddr = dev->base_addr;
0558 int length;
0559 unsigned long flags;
0560
0561 length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
0562
0563 netif_stop_queue(dev);
0564
0565
0566
0567
0568 spin_lock_irqsave(&lp->lock, flags);
0569 write_reg(ioaddr, IMR, 0);
0570 write_reg_high(ioaddr, IMR, 0);
0571 spin_unlock_irqrestore(&lp->lock, flags);
0572
0573 write_packet(ioaddr, length, skb->data, length-skb->len, dev->if_port);
0574
0575 lp->pac_cnt_in_tx_buf++;
0576 if (lp->tx_unit_busy == 0) {
0577 trigger_send(ioaddr, length);
0578 lp->saved_tx_size = 0;
0579 lp->re_tx = 0;
0580 lp->tx_unit_busy = 1;
0581 } else
0582 lp->saved_tx_size = length;
0583
0584 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK);
0585 write_reg_high(ioaddr, IMR, ISRh_RxErr);
0586
0587 dev_kfree_skb (skb);
0588 return NETDEV_TX_OK;
0589 }
0590
0591
0592
0593
0594 static irqreturn_t atp_interrupt(int irq, void *dev_instance)
0595 {
0596 struct net_device *dev = dev_instance;
0597 struct net_local *lp;
0598 long ioaddr;
0599 static int num_tx_since_rx;
0600 int boguscount = max_interrupt_work;
0601 int handled = 0;
0602
0603 ioaddr = dev->base_addr;
0604 lp = netdev_priv(dev);
0605
0606 spin_lock(&lp->lock);
0607
0608
0609 outb(Ctrl_SelData, ioaddr + PAR_CONTROL);
0610
0611
0612 write_reg(ioaddr, CMR2, CMR2_NULL);
0613 write_reg(ioaddr, IMR, 0);
0614
0615 if (net_debug > 5)
0616 printk(KERN_DEBUG "%s: In interrupt ", dev->name);
0617 while (--boguscount > 0) {
0618 int status = read_nibble(ioaddr, ISR);
0619 if (net_debug > 5)
0620 printk("loop status %02x..", status);
0621
0622 if (status & (ISR_RxOK<<3)) {
0623 handled = 1;
0624 write_reg(ioaddr, ISR, ISR_RxOK);
0625 do {
0626 int read_status = read_nibble(ioaddr, CMR1);
0627 if (net_debug > 6)
0628 printk("handling Rx packet %02x..", read_status);
0629
0630
0631 if (read_status & (CMR1_IRQ << 3)) {
0632 dev->stats.rx_over_errors++;
0633
0634 write_reg_high(ioaddr, CMR2, CMR2h_OFF);
0635 net_rx(dev);
0636
0637 write_reg_high(ioaddr, ISR, ISRh_RxErr);
0638 write_reg_high(ioaddr, CMR2, lp->addr_mode);
0639 } else if ((read_status & (CMR1_BufEnb << 3)) == 0) {
0640 net_rx(dev);
0641 num_tx_since_rx = 0;
0642 } else
0643 break;
0644 } while (--boguscount > 0);
0645 } else if (status & ((ISR_TxErr + ISR_TxOK)<<3)) {
0646 handled = 1;
0647 if (net_debug > 6)
0648 printk("handling Tx done..");
0649
0650
0651 write_reg(ioaddr, ISR, ISR_TxErr + ISR_TxOK);
0652 if (status & (ISR_TxErr<<3)) {
0653 dev->stats.collisions++;
0654 if (++lp->re_tx > 15) {
0655 dev->stats.tx_aborted_errors++;
0656 hardware_init(dev);
0657 break;
0658 }
0659
0660 if (net_debug > 6) printk("attempting to ReTx");
0661 write_reg(ioaddr, CMR1, CMR1_ReXmit + CMR1_Xmit);
0662 } else {
0663
0664 dev->stats.tx_packets++;
0665 lp->pac_cnt_in_tx_buf--;
0666 if ( lp->saved_tx_size) {
0667 trigger_send(ioaddr, lp->saved_tx_size);
0668 lp->saved_tx_size = 0;
0669 lp->re_tx = 0;
0670 } else
0671 lp->tx_unit_busy = 0;
0672 netif_wake_queue(dev);
0673 }
0674 num_tx_since_rx++;
0675 } else if (num_tx_since_rx > 8 &&
0676 time_after(jiffies, lp->last_rx_time + HZ)) {
0677 if (net_debug > 2)
0678 printk(KERN_DEBUG "%s: Missed packet? No Rx after %d Tx and "
0679 "%ld jiffies status %02x CMR1 %02x.\n", dev->name,
0680 num_tx_since_rx, jiffies - lp->last_rx_time, status,
0681 (read_nibble(ioaddr, CMR1) >> 3) & 15);
0682 dev->stats.rx_missed_errors++;
0683 hardware_init(dev);
0684 num_tx_since_rx = 0;
0685 break;
0686 } else
0687 break;
0688 }
0689
0690
0691
0692 {
0693 int i;
0694 for (i = 0; i < 6; i++)
0695 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]);
0696 #if 0 && defined(TIMED_CHECKER)
0697 mod_timer(&lp->timer, jiffies + TIMED_CHECKER);
0698 #endif
0699 }
0700
0701
0702 write_reg(ioaddr, CMR2, CMR2_IRQOUT);
0703
0704 outb(Ctrl_SelData + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
0705
0706 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK);
0707 write_reg_high(ioaddr, IMR, ISRh_RxErr);
0708
0709 spin_unlock(&lp->lock);
0710
0711 if (net_debug > 5) printk("exiting interrupt.\n");
0712 return IRQ_RETVAL(handled);
0713 }
0714
0715 #ifdef TIMED_CHECKER
0716
0717
0718 static void atp_timed_checker(struct timer_list *t)
0719 {
0720 struct net_local *lp = from_timer(lp, t, timer);
0721 struct net_device *dev = lp->dev;
0722 long ioaddr = dev->base_addr;
0723 int tickssofar = jiffies - lp->last_rx_time;
0724 int i;
0725
0726 spin_lock(&lp->lock);
0727 if (tickssofar > 2*HZ) {
0728 #if 1
0729 for (i = 0; i < 6; i++)
0730 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]);
0731 lp->last_rx_time = jiffies;
0732 #else
0733 for (i = 0; i < 6; i++)
0734 if (read_cmd_byte(ioaddr, PAR0 + i) != atp_timed_dev->dev_addr[i])
0735 {
0736 struct net_local *lp = netdev_priv(atp_timed_dev);
0737 write_reg_byte(ioaddr, PAR0 + i, atp_timed_dev->dev_addr[i]);
0738 if (i == 2)
0739 dev->stats.tx_errors++;
0740 else if (i == 3)
0741 dev->stats.tx_dropped++;
0742 else if (i == 4)
0743 dev->stats.collisions++;
0744 else
0745 dev->stats.rx_errors++;
0746 }
0747 #endif
0748 }
0749 spin_unlock(&lp->lock);
0750 lp->timer.expires = jiffies + TIMED_CHECKER;
0751 add_timer(&lp->timer);
0752 }
0753 #endif
0754
0755
0756 static void net_rx(struct net_device *dev)
0757 {
0758 struct net_local *lp = netdev_priv(dev);
0759 long ioaddr = dev->base_addr;
0760 struct rx_header rx_head;
0761
0762
0763 outb(EOC+MAR, ioaddr + PAR_DATA);
0764 read_block(ioaddr, 8, (unsigned char*)&rx_head, dev->if_port);
0765 if (net_debug > 5)
0766 printk(KERN_DEBUG " rx_count %04x %04x %04x %04x..", rx_head.pad,
0767 rx_head.rx_count, rx_head.rx_status, rx_head.cur_addr);
0768 if ((rx_head.rx_status & 0x77) != 0x01) {
0769 dev->stats.rx_errors++;
0770 if (rx_head.rx_status & 0x0004) dev->stats.rx_frame_errors++;
0771 else if (rx_head.rx_status & 0x0002) dev->stats.rx_crc_errors++;
0772 if (net_debug > 3)
0773 printk(KERN_DEBUG "%s: Unknown ATP Rx error %04x.\n",
0774 dev->name, rx_head.rx_status);
0775 if (rx_head.rx_status & 0x0020) {
0776 dev->stats.rx_fifo_errors++;
0777 write_reg_high(ioaddr, CMR1, CMR1h_TxENABLE);
0778 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
0779 } else if (rx_head.rx_status & 0x0050)
0780 hardware_init(dev);
0781 return;
0782 } else {
0783
0784 int pkt_len = (rx_head.rx_count & 0x7ff) - 4;
0785 struct sk_buff *skb;
0786
0787 skb = netdev_alloc_skb(dev, pkt_len + 2);
0788 if (skb == NULL) {
0789 dev->stats.rx_dropped++;
0790 goto done;
0791 }
0792
0793 skb_reserve(skb, 2);
0794 read_block(ioaddr, pkt_len, skb_put(skb,pkt_len), dev->if_port);
0795 skb->protocol = eth_type_trans(skb, dev);
0796 netif_rx(skb);
0797 dev->stats.rx_packets++;
0798 dev->stats.rx_bytes += pkt_len;
0799 }
0800 done:
0801 write_reg(ioaddr, CMR1, CMR1_NextPkt);
0802 lp->last_rx_time = jiffies;
0803 }
0804
0805 static void read_block(long ioaddr, int length, unsigned char *p, int data_mode)
0806 {
0807 if (data_mode <= 3) {
0808 outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
0809 outb(length == 8 ? RdAddr | HNib | MAR : RdAddr | MAR,
0810 ioaddr + PAR_DATA);
0811 if (data_mode <= 1) {
0812 do { *p++ = read_byte_mode0(ioaddr); } while (--length > 0);
0813 } else {
0814 do { *p++ = read_byte_mode2(ioaddr); } while (--length > 0);
0815 }
0816 } else if (data_mode <= 5) {
0817 do { *p++ = read_byte_mode4(ioaddr); } while (--length > 0);
0818 } else {
0819 do { *p++ = read_byte_mode6(ioaddr); } while (--length > 0);
0820 }
0821
0822 outb(EOC+HNib+MAR, ioaddr + PAR_DATA);
0823 outb(Ctrl_SelData, ioaddr + PAR_CONTROL);
0824 }
0825
0826
0827 static int
0828 net_close(struct net_device *dev)
0829 {
0830 struct net_local *lp = netdev_priv(dev);
0831 long ioaddr = dev->base_addr;
0832
0833 netif_stop_queue(dev);
0834
0835 del_timer_sync(&lp->timer);
0836
0837
0838 lp->addr_mode = CMR2h_OFF;
0839 write_reg_high(ioaddr, CMR2, CMR2h_OFF);
0840
0841
0842 outb(0x00, ioaddr + PAR_CONTROL);
0843 free_irq(dev->irq, dev);
0844
0845
0846 write_reg_high(ioaddr, CMR1, CMR1h_RESET | CMR1h_MUX);
0847 return 0;
0848 }
0849
0850
0851
0852
0853
0854 static void set_rx_mode(struct net_device *dev)
0855 {
0856 struct net_local *lp = netdev_priv(dev);
0857 long ioaddr = dev->base_addr;
0858
0859 if (!netdev_mc_empty(dev) || (dev->flags & (IFF_ALLMULTI|IFF_PROMISC)))
0860 lp->addr_mode = CMR2h_PROMISC;
0861 else
0862 lp->addr_mode = CMR2h_Normal;
0863 write_reg_high(ioaddr, CMR2, lp->addr_mode);
0864 }
0865
0866 static int __init atp_init_module(void) {
0867 if (debug)
0868 printk(KERN_INFO "%s", version);
0869 return atp_init();
0870 }
0871
0872 static void __exit atp_cleanup_module(void) {
0873 struct net_device *next_dev;
0874
0875 while (root_atp_dev) {
0876 struct net_local *atp_local = netdev_priv(root_atp_dev);
0877 next_dev = atp_local->next_module;
0878 unregister_netdev(root_atp_dev);
0879
0880 free_netdev(root_atp_dev);
0881 root_atp_dev = next_dev;
0882 }
0883 }
0884
0885 module_init(atp_init_module);
0886 module_exit(atp_cleanup_module);