ethernet/qualcomm/qca_7k.h

0001 /*
0002  *   Copyright (c) 2011, 2012, Qualcomm Atheros Communications Inc.
0003  *   Copyright (c) 2014, I2SE GmbH
0004  *
0005  *   Permission to use, copy, modify, and/or distribute this software
0006  *   for any purpose with or without fee is hereby granted, provided
0007  *   that the above copyright notice and this permission notice appear
0008  *   in all copies.
0009  *
0010  *   THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
0011  *   WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
0012  *   WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL
0013  *   THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR
0014  *   CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
0015  *   LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
0016  *   NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
0017  *   CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0018  *
0019  */
0020
0021 /*   Qualcomm Atheros SPI register definition.
0022  *
0023  *   This module is designed to define the Qualcomm Atheros SPI
0024  *   register placeholders.
0025  */
0026
0027 #ifndef _QCA_7K_H
0028 #define _QCA_7K_H
0029
0030 #include <linux/types.h>
0031
0032 #include "qca_spi.h"
0033
0034 #define QCA7K_SPI_READ     (1 << 15)
0035 #define QCA7K_SPI_WRITE    (0 << 15)
0036 #define QCA7K_SPI_INTERNAL (1 << 14)
0037 #define QCA7K_SPI_EXTERNAL (0 << 14)
0038
0039 #define QCASPI_CMD_LEN    2
0040 #define QCASPI_HW_PKT_LEN 4
0041 #define QCASPI_HW_BUF_LEN 0xC5B
0042
0043 /*   SPI registers;                               */
0044 #define SPI_REG_BFR_SIZE        0x0100
0045 #define SPI_REG_WRBUF_SPC_AVA   0x0200
0046 #define SPI_REG_RDBUF_BYTE_AVA  0x0300
0047 #define SPI_REG_SPI_CONFIG      0x0400
0048 #define SPI_REG_SPI_STATUS      0x0500
0049 #define SPI_REG_INTR_CAUSE      0x0C00
0050 #define SPI_REG_INTR_ENABLE     0x0D00
0051 #define SPI_REG_RDBUF_WATERMARK 0x1200
0052 #define SPI_REG_WRBUF_WATERMARK 0x1300
0053 #define SPI_REG_SIGNATURE       0x1A00
0054 #define SPI_REG_ACTION_CTRL     0x1B00
0055
0056 /*   SPI_CONFIG register definition;             */
0057 #define QCASPI_SLAVE_RESET_BIT  BIT(6)
0058
0059 /*   INTR_CAUSE/ENABLE register definition.      */
0060 #define SPI_INT_WRBUF_BELOW_WM  BIT(10)
0061 #define SPI_INT_CPU_ON          BIT(6)
0062 #define SPI_INT_ADDR_ERR        BIT(3)
0063 #define SPI_INT_WRBUF_ERR       BIT(2)
0064 #define SPI_INT_RDBUF_ERR       BIT(1)
0065 #define SPI_INT_PKT_AVLBL       BIT(0)
0066
0067 void qcaspi_spi_error(struct qcaspi *qca);
0068 int qcaspi_read_register(struct qcaspi *qca, u16 reg, u16 *result);
0069 int qcaspi_write_register(struct qcaspi *qca, u16 reg, u16 value, int retry);
0070
0071 #endif /* _QCA_7K_H */