qualcomm/emac/emac-sgmii-qdf2432.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
0003  */
0004
0005 /* Qualcomm Technologies, Inc. QDF2432 EMAC SGMII Controller driver.
0006  */
0007
0008 #include <linux/iopoll.h>
0009 #include "emac.h"
0010
0011 /* EMAC_SGMII register offsets */
0012 #define EMAC_SGMII_PHY_TX_PWR_CTRL      0x000C
0013 #define EMAC_SGMII_PHY_LANE_CTRL1       0x0018
0014 #define EMAC_SGMII_PHY_CDR_CTRL0        0x0058
0015 #define EMAC_SGMII_PHY_POW_DWN_CTRL0        0x0080
0016 #define EMAC_SGMII_PHY_RESET_CTRL       0x00a8
0017 #define EMAC_SGMII_PHY_INTERRUPT_MASK       0x00b4
0018
0019 /* SGMII digital lane registers */
0020 #define EMAC_SGMII_LN_DRVR_CTRL0        0x000C
0021 #define EMAC_SGMII_LN_DRVR_TAP_EN       0x0018
0022 #define EMAC_SGMII_LN_TX_MARGINING      0x001C
0023 #define EMAC_SGMII_LN_TX_PRE            0x0020
0024 #define EMAC_SGMII_LN_TX_POST           0x0024
0025 #define EMAC_SGMII_LN_TX_BAND_MODE      0x0060
0026 #define EMAC_SGMII_LN_LANE_MODE         0x0064
0027 #define EMAC_SGMII_LN_PARALLEL_RATE     0x0078
0028 #define EMAC_SGMII_LN_CML_CTRL_MODE0        0x00B8
0029 #define EMAC_SGMII_LN_MIXER_CTRL_MODE0      0x00D0
0030 #define EMAC_SGMII_LN_VGA_INITVAL       0x0134
0031 #define EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0    0x017C
0032 #define EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0    0x0188
0033 #define EMAC_SGMII_LN_UCDR_SO_CONFIG        0x0194
0034 #define EMAC_SGMII_LN_RX_BAND           0x019C
0035 #define EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0   0x01B8
0036 #define EMAC_SGMII_LN_RSM_CONFIG        0x01F0
0037 #define EMAC_SGMII_LN_SIGDET_ENABLES        0x0224
0038 #define EMAC_SGMII_LN_SIGDET_CNTRL      0x0228
0039 #define EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL 0x022C
0040 #define EMAC_SGMII_LN_RX_EN_SIGNAL      0x02A0
0041 #define EMAC_SGMII_LN_RX_MISC_CNTRL0        0x02AC
0042 #define EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV     0x02BC
0043
0044 /* SGMII digital lane register values */
0045 #define UCDR_STEP_BY_TWO_MODE0          BIT(7)
0046 #define UCDR_xO_GAIN_MODE(x)            ((x) & 0x7f)
0047 #define UCDR_ENABLE             BIT(6)
0048 #define UCDR_SO_SATURATION(x)           ((x) & 0x3f)
0049
0050 #define SIGDET_LP_BYP_PS4           BIT(7)
0051 #define SIGDET_EN_PS0_TO_PS2            BIT(6)
0052
0053 #define TXVAL_VALID_INIT            BIT(4)
0054 #define KR_PCIGEN3_MODE             BIT(0)
0055
0056 #define MAIN_EN                 BIT(0)
0057
0058 #define TX_MARGINING_MUX            BIT(6)
0059 #define TX_MARGINING(x)             ((x) & 0x3f)
0060
0061 #define TX_PRE_MUX              BIT(6)
0062
0063 #define TX_POST_MUX             BIT(6)
0064
0065 #define CML_GEAR_MODE(x)            (((x) & 7) << 3)
0066 #define CML2CMOS_IBOOST_MODE(x)         ((x) & 7)
0067
0068 #define MIXER_LOADB_MODE(x)         (((x) & 0xf) << 2)
0069 #define MIXER_DATARATE_MODE(x)          ((x) & 3)
0070
0071 #define VGA_THRESH_DFE(x)           ((x) & 0x3f)
0072
0073 #define SIGDET_LP_BYP_PS0_TO_PS2        BIT(5)
0074 #define SIGDET_FLT_BYP              BIT(0)
0075
0076 #define SIGDET_LVL(x)               (((x) & 0xf) << 4)
0077
0078 #define SIGDET_DEGLITCH_CTRL(x)         (((x) & 0xf) << 1)
0079
0080 #define DRVR_LOGIC_CLK_EN           BIT(4)
0081 #define DRVR_LOGIC_CLK_DIV(x)           ((x) & 0xf)
0082
0083 #define PARALLEL_RATE_MODE0(x)          ((x) & 0x3)
0084
0085 #define BAND_MODE0(x)               ((x) & 0x3)
0086
0087 #define LANE_MODE(x)                ((x) & 0x1f)
0088
0089 #define CDR_PD_SEL_MODE0(x)         (((x) & 0x3) << 5)
0090 #define BYPASS_RSM_SAMP_CAL         BIT(1)
0091 #define BYPASS_RSM_DLL_CAL          BIT(0)
0092
0093 #define L0_RX_EQUALIZE_ENABLE           BIT(6)
0094
0095 #define PWRDN_B                 BIT(0)
0096
0097 #define CDR_MAX_CNT(x)              ((x) & 0xff)
0098
0099 #define SERDES_START_WAIT_TIMES         100
0100
0101 struct emac_reg_write {
0102     unsigned int offset;
0103     u32 val;
0104 };
0105
0106 static void emac_reg_write_all(void __iomem *base,
0107                    const struct emac_reg_write *itr, size_t size)
0108 {
0109     size_t i;
0110
0111     for (i = 0; i < size; ++itr, ++i)
0112         writel(itr->val, base + itr->offset);
0113 }
0114
0115 static const struct emac_reg_write sgmii_laned[] = {
0116     /* CDR Settings */
0117     {EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0,
0118         UCDR_STEP_BY_TWO_MODE0 | UCDR_xO_GAIN_MODE(10)},
0119     {EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0, UCDR_xO_GAIN_MODE(0)},
0120     {EMAC_SGMII_LN_UCDR_SO_CONFIG, UCDR_ENABLE | UCDR_SO_SATURATION(12)},
0121
0122     /* TX/RX Settings */
0123     {EMAC_SGMII_LN_RX_EN_SIGNAL, SIGDET_LP_BYP_PS4 | SIGDET_EN_PS0_TO_PS2},
0124
0125     {EMAC_SGMII_LN_DRVR_CTRL0, TXVAL_VALID_INIT | KR_PCIGEN3_MODE},
0126     {EMAC_SGMII_LN_DRVR_TAP_EN, MAIN_EN},
0127     {EMAC_SGMII_LN_TX_MARGINING, TX_MARGINING_MUX | TX_MARGINING(25)},
0128     {EMAC_SGMII_LN_TX_PRE, TX_PRE_MUX},
0129     {EMAC_SGMII_LN_TX_POST, TX_POST_MUX},
0130
0131     {EMAC_SGMII_LN_CML_CTRL_MODE0,
0132         CML_GEAR_MODE(1) | CML2CMOS_IBOOST_MODE(1)},
0133     {EMAC_SGMII_LN_MIXER_CTRL_MODE0,
0134         MIXER_LOADB_MODE(12) | MIXER_DATARATE_MODE(1)},
0135     {EMAC_SGMII_LN_VGA_INITVAL, VGA_THRESH_DFE(31)},
0136     {EMAC_SGMII_LN_SIGDET_ENABLES,
0137         SIGDET_LP_BYP_PS0_TO_PS2 | SIGDET_FLT_BYP},
0138     {EMAC_SGMII_LN_SIGDET_CNTRL, SIGDET_LVL(8)},
0139
0140     {EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL, SIGDET_DEGLITCH_CTRL(4)},
0141     {EMAC_SGMII_LN_RX_MISC_CNTRL0, 0},
0142     {EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV,
0143         DRVR_LOGIC_CLK_EN | DRVR_LOGIC_CLK_DIV(4)},
0144
0145     {EMAC_SGMII_LN_PARALLEL_RATE, PARALLEL_RATE_MODE0(1)},
0146     {EMAC_SGMII_LN_TX_BAND_MODE, BAND_MODE0(2)},
0147     {EMAC_SGMII_LN_RX_BAND, BAND_MODE0(3)},
0148     {EMAC_SGMII_LN_LANE_MODE, LANE_MODE(26)},
0149     {EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0, CDR_PD_SEL_MODE0(3)},
0150     {EMAC_SGMII_LN_RSM_CONFIG, BYPASS_RSM_SAMP_CAL | BYPASS_RSM_DLL_CAL},
0151 };
0152
0153 static const struct emac_reg_write physical_coding_sublayer_programming[] = {
0154     {EMAC_SGMII_PHY_POW_DWN_CTRL0, PWRDN_B},
0155     {EMAC_SGMII_PHY_CDR_CTRL0, CDR_MAX_CNT(15)},
0156     {EMAC_SGMII_PHY_TX_PWR_CTRL, 0},
0157     {EMAC_SGMII_PHY_LANE_CTRL1, L0_RX_EQUALIZE_ENABLE},
0158 };
0159
0160 int emac_sgmii_init_qdf2432(struct emac_adapter *adpt)
0161 {
0162     struct emac_sgmii *phy = &adpt->phy;
0163     void __iomem *phy_regs = phy->base;
0164     void __iomem *laned = phy->digital;
0165     unsigned int i;
0166     u32 lnstatus;
0167
0168     /* PCS lane-x init */
0169     emac_reg_write_all(phy->base, physical_coding_sublayer_programming,
0170                ARRAY_SIZE(physical_coding_sublayer_programming));
0171
0172     /* SGMII lane-x init */
0173     emac_reg_write_all(phy->digital, sgmii_laned, ARRAY_SIZE(sgmii_laned));
0174
0175     /* Power up PCS and start reset lane state machine */
0176
0177     writel(0, phy_regs + EMAC_SGMII_PHY_RESET_CTRL);
0178     writel(1, laned + SGMII_LN_RSM_START);
0179
0180     /* Wait for c_ready assertion */
0181     for (i = 0; i < SERDES_START_WAIT_TIMES; i++) {
0182         lnstatus = readl(phy_regs + SGMII_PHY_LN_LANE_STATUS);
0183         if (lnstatus & BIT(1))
0184             break;
0185         usleep_range(100, 200);
0186     }
0187
0188     if (i == SERDES_START_WAIT_TIMES) {
0189         netdev_err(adpt->netdev, "SGMII failed to start\n");
0190         return -EIO;
0191     }
0192
0193     /* Disable digital and SERDES loopback */
0194     writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN0);
0195     writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN2);
0196     writel(0, phy_regs + SGMII_PHY_LN_CDR_CTRL1);
0197
0198     /* Mask out all the SGMII Interrupt */
0199     writel(0, phy_regs + EMAC_SGMII_PHY_INTERRUPT_MASK);
0200
0201     return 0;
0202 }