qualcomm/emac/emac-sgmii-fsm9900.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
0003  */
0004
0005 /* Qualcomm Technologies, Inc. FSM9900 EMAC SGMII Controller driver.
0006  */
0007
0008 #include <linux/iopoll.h>
0009 #include "emac.h"
0010
0011 /* EMAC_QSERDES register offsets */
0012 #define EMAC_QSERDES_COM_SYS_CLK_CTRL       0x0000
0013 #define EMAC_QSERDES_COM_PLL_CNTRL      0x0014
0014 #define EMAC_QSERDES_COM_PLL_IP_SETI        0x0018
0015 #define EMAC_QSERDES_COM_PLL_CP_SETI        0x0024
0016 #define EMAC_QSERDES_COM_PLL_IP_SETP        0x0028
0017 #define EMAC_QSERDES_COM_PLL_CP_SETP        0x002c
0018 #define EMAC_QSERDES_COM_SYSCLK_EN_SEL      0x0038
0019 #define EMAC_QSERDES_COM_RESETSM_CNTRL      0x0040
0020 #define EMAC_QSERDES_COM_PLLLOCK_CMP1       0x0044
0021 #define EMAC_QSERDES_COM_PLLLOCK_CMP2       0x0048
0022 #define EMAC_QSERDES_COM_PLLLOCK_CMP3       0x004c
0023 #define EMAC_QSERDES_COM_PLLLOCK_CMP_EN     0x0050
0024 #define EMAC_QSERDES_COM_DEC_START1     0x0064
0025 #define EMAC_QSERDES_COM_DIV_FRAC_START1    0x0098
0026 #define EMAC_QSERDES_COM_DIV_FRAC_START2    0x009c
0027 #define EMAC_QSERDES_COM_DIV_FRAC_START3    0x00a0
0028 #define EMAC_QSERDES_COM_DEC_START2     0x00a4
0029 #define EMAC_QSERDES_COM_PLL_CRCTRL     0x00ac
0030 #define EMAC_QSERDES_COM_RESET_SM       0x00bc
0031 #define EMAC_QSERDES_TX_BIST_MODE_LANENO    0x0100
0032 #define EMAC_QSERDES_TX_TX_EMP_POST1_LVL    0x0108
0033 #define EMAC_QSERDES_TX_TX_DRV_LVL      0x010c
0034 #define EMAC_QSERDES_TX_LANE_MODE       0x0150
0035 #define EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN    0x0170
0036 #define EMAC_QSERDES_RX_CDR_CONTROL     0x0200
0037 #define EMAC_QSERDES_RX_CDR_CONTROL2        0x0210
0038 #define EMAC_QSERDES_RX_RX_EQ_GAIN12        0x0230
0039
0040 /* EMAC_SGMII register offsets */
0041 #define EMAC_SGMII_PHY_SERDES_START     0x0000
0042 #define EMAC_SGMII_PHY_CMN_PWR_CTRL     0x0004
0043 #define EMAC_SGMII_PHY_RX_PWR_CTRL      0x0008
0044 #define EMAC_SGMII_PHY_TX_PWR_CTRL      0x000C
0045 #define EMAC_SGMII_PHY_LANE_CTRL1       0x0018
0046 #define EMAC_SGMII_PHY_CDR_CTRL0        0x0058
0047 #define EMAC_SGMII_PHY_POW_DWN_CTRL0        0x0080
0048 #define EMAC_SGMII_PHY_INTERRUPT_MASK       0x00b4
0049
0050 #define PLL_IPSETI(x)               ((x) & 0x3f)
0051
0052 #define PLL_CPSETI(x)               ((x) & 0xff)
0053
0054 #define PLL_IPSETP(x)               ((x) & 0x3f)
0055
0056 #define PLL_CPSETP(x)               ((x) & 0x1f)
0057
0058 #define PLL_RCTRL(x)                (((x) & 0xf) << 4)
0059 #define PLL_CCTRL(x)                ((x) & 0xf)
0060
0061 #define LANE_MODE(x)                ((x) & 0x1f)
0062
0063 #define SYSCLK_CM               BIT(4)
0064 #define SYSCLK_AC_COUPLE            BIT(3)
0065
0066 #define OCP_EN                  BIT(5)
0067 #define PLL_DIV_FFEN                BIT(2)
0068 #define PLL_DIV_ORD             BIT(1)
0069
0070 #define SYSCLK_SEL_CMOS             BIT(3)
0071
0072 #define FRQ_TUNE_MODE               BIT(4)
0073
0074 #define PLLLOCK_CMP_EN              BIT(0)
0075
0076 #define DEC_START1_MUX              BIT(7)
0077 #define DEC_START1(x)               ((x) & 0x7f)
0078
0079 #define DIV_FRAC_START_MUX          BIT(7)
0080 #define DIV_FRAC_START(x)           ((x) & 0x7f)
0081
0082 #define DIV_FRAC_START3_MUX         BIT(4)
0083 #define DIV_FRAC_START3(x)          ((x) & 0xf)
0084
0085 #define DEC_START2_MUX              BIT(1)
0086 #define DEC_START2              BIT(0)
0087
0088 #define READY                   BIT(5)
0089
0090 #define TX_EMP_POST1_LVL_MUX            BIT(5)
0091 #define TX_EMP_POST1_LVL(x)         ((x) & 0x1f)
0092
0093 #define TX_DRV_LVL_MUX              BIT(4)
0094 #define TX_DRV_LVL(x)               ((x) & 0xf)
0095
0096 #define EMP_EN_MUX              BIT(1)
0097 #define EMP_EN                  BIT(0)
0098
0099 #define SECONDORDERENABLE           BIT(6)
0100 #define FIRSTORDER_THRESH(x)            (((x) & 0x7) << 3)
0101 #define SECONDORDERGAIN(x)          ((x) & 0x7)
0102
0103 #define RX_EQ_GAIN2(x)              (((x) & 0xf) << 4)
0104 #define RX_EQ_GAIN1(x)              ((x) & 0xf)
0105
0106 #define SERDES_START                BIT(0)
0107
0108 #define BIAS_EN                 BIT(6)
0109 #define PLL_EN                  BIT(5)
0110 #define SYSCLK_EN               BIT(4)
0111 #define CLKBUF_L_EN             BIT(3)
0112 #define PLL_TXCLK_EN                BIT(1)
0113 #define PLL_RXCLK_EN                BIT(0)
0114
0115 #define L0_RX_SIGDET_EN             BIT(7)
0116 #define L0_RX_TERM_MODE(x)          (((x) & 3) << 4)
0117 #define L0_RX_I_EN              BIT(1)
0118
0119 #define L0_TX_EN                BIT(5)
0120 #define L0_CLKBUF_EN                BIT(4)
0121 #define L0_TRAN_BIAS_EN             BIT(1)
0122
0123 #define L0_RX_EQUALIZE_ENABLE           BIT(6)
0124 #define L0_RESET_TSYNC_EN           BIT(4)
0125 #define L0_DRV_LVL(x)               ((x) & 0xf)
0126
0127 #define PWRDN_B                 BIT(0)
0128 #define CDR_MAX_CNT(x)              ((x) & 0xff)
0129
0130 #define PLLLOCK_CMP(x)              ((x) & 0xff)
0131
0132 #define SERDES_START_WAIT_TIMES         100
0133
0134 struct emac_reg_write {
0135     unsigned int offset;
0136     u32 val;
0137 };
0138
0139 static void emac_reg_write_all(void __iomem *base,
0140                    const struct emac_reg_write *itr, size_t size)
0141 {
0142     size_t i;
0143
0144     for (i = 0; i < size; ++itr, ++i)
0145         writel(itr->val, base + itr->offset);
0146 }
0147
0148 static const struct emac_reg_write physical_coding_sublayer_programming[] = {
0149     {EMAC_SGMII_PHY_CDR_CTRL0, CDR_MAX_CNT(15)},
0150     {EMAC_SGMII_PHY_POW_DWN_CTRL0, PWRDN_B},
0151     {EMAC_SGMII_PHY_CMN_PWR_CTRL,
0152         BIAS_EN | SYSCLK_EN | CLKBUF_L_EN | PLL_TXCLK_EN | PLL_RXCLK_EN},
0153     {EMAC_SGMII_PHY_TX_PWR_CTRL, L0_TX_EN | L0_CLKBUF_EN | L0_TRAN_BIAS_EN},
0154     {EMAC_SGMII_PHY_RX_PWR_CTRL,
0155         L0_RX_SIGDET_EN | L0_RX_TERM_MODE(1) | L0_RX_I_EN},
0156     {EMAC_SGMII_PHY_CMN_PWR_CTRL,
0157         BIAS_EN | PLL_EN | SYSCLK_EN | CLKBUF_L_EN | PLL_TXCLK_EN |
0158         PLL_RXCLK_EN},
0159     {EMAC_SGMII_PHY_LANE_CTRL1,
0160         L0_RX_EQUALIZE_ENABLE | L0_RESET_TSYNC_EN | L0_DRV_LVL(15)},
0161 };
0162
0163 static const struct emac_reg_write sysclk_refclk_setting[] = {
0164     {EMAC_QSERDES_COM_SYSCLK_EN_SEL, SYSCLK_SEL_CMOS},
0165     {EMAC_QSERDES_COM_SYS_CLK_CTRL, SYSCLK_CM | SYSCLK_AC_COUPLE},
0166 };
0167
0168 static const struct emac_reg_write pll_setting[] = {
0169     {EMAC_QSERDES_COM_PLL_IP_SETI, PLL_IPSETI(1)},
0170     {EMAC_QSERDES_COM_PLL_CP_SETI, PLL_CPSETI(59)},
0171     {EMAC_QSERDES_COM_PLL_IP_SETP, PLL_IPSETP(10)},
0172     {EMAC_QSERDES_COM_PLL_CP_SETP, PLL_CPSETP(9)},
0173     {EMAC_QSERDES_COM_PLL_CRCTRL, PLL_RCTRL(15) | PLL_CCTRL(11)},
0174     {EMAC_QSERDES_COM_PLL_CNTRL, OCP_EN | PLL_DIV_FFEN | PLL_DIV_ORD},
0175     {EMAC_QSERDES_COM_DEC_START1, DEC_START1_MUX | DEC_START1(2)},
0176     {EMAC_QSERDES_COM_DEC_START2, DEC_START2_MUX | DEC_START2},
0177     {EMAC_QSERDES_COM_DIV_FRAC_START1,
0178         DIV_FRAC_START_MUX | DIV_FRAC_START(85)},
0179     {EMAC_QSERDES_COM_DIV_FRAC_START2,
0180         DIV_FRAC_START_MUX | DIV_FRAC_START(42)},
0181     {EMAC_QSERDES_COM_DIV_FRAC_START3,
0182         DIV_FRAC_START3_MUX | DIV_FRAC_START3(3)},
0183     {EMAC_QSERDES_COM_PLLLOCK_CMP1, PLLLOCK_CMP(43)},
0184     {EMAC_QSERDES_COM_PLLLOCK_CMP2, PLLLOCK_CMP(104)},
0185     {EMAC_QSERDES_COM_PLLLOCK_CMP3, PLLLOCK_CMP(0)},
0186     {EMAC_QSERDES_COM_PLLLOCK_CMP_EN, PLLLOCK_CMP_EN},
0187     {EMAC_QSERDES_COM_RESETSM_CNTRL, FRQ_TUNE_MODE},
0188 };
0189
0190 static const struct emac_reg_write cdr_setting[] = {
0191     {EMAC_QSERDES_RX_CDR_CONTROL,
0192         SECONDORDERENABLE | FIRSTORDER_THRESH(3) | SECONDORDERGAIN(2)},
0193     {EMAC_QSERDES_RX_CDR_CONTROL2,
0194         SECONDORDERENABLE | FIRSTORDER_THRESH(3) | SECONDORDERGAIN(4)},
0195 };
0196
0197 static const struct emac_reg_write tx_rx_setting[] = {
0198     {EMAC_QSERDES_TX_BIST_MODE_LANENO, 0},
0199     {EMAC_QSERDES_TX_TX_DRV_LVL, TX_DRV_LVL_MUX | TX_DRV_LVL(15)},
0200     {EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN, EMP_EN_MUX | EMP_EN},
0201     {EMAC_QSERDES_TX_TX_EMP_POST1_LVL,
0202         TX_EMP_POST1_LVL_MUX | TX_EMP_POST1_LVL(1)},
0203     {EMAC_QSERDES_RX_RX_EQ_GAIN12, RX_EQ_GAIN2(15) | RX_EQ_GAIN1(15)},
0204     {EMAC_QSERDES_TX_LANE_MODE, LANE_MODE(8)},
0205 };
0206
0207 int emac_sgmii_init_fsm9900(struct emac_adapter *adpt)
0208 {
0209     struct emac_sgmii *phy = &adpt->phy;
0210     unsigned int i;
0211
0212     emac_reg_write_all(phy->base, physical_coding_sublayer_programming,
0213                ARRAY_SIZE(physical_coding_sublayer_programming));
0214     emac_reg_write_all(phy->base, sysclk_refclk_setting,
0215                ARRAY_SIZE(sysclk_refclk_setting));
0216     emac_reg_write_all(phy->base, pll_setting, ARRAY_SIZE(pll_setting));
0217     emac_reg_write_all(phy->base, cdr_setting, ARRAY_SIZE(cdr_setting));
0218     emac_reg_write_all(phy->base, tx_rx_setting, ARRAY_SIZE(tx_rx_setting));
0219
0220     /* Power up the Ser/Des engine */
0221     writel(SERDES_START, phy->base + EMAC_SGMII_PHY_SERDES_START);
0222
0223     for (i = 0; i < SERDES_START_WAIT_TIMES; i++) {
0224         if (readl(phy->base + EMAC_QSERDES_COM_RESET_SM) & READY)
0225             break;
0226         usleep_range(100, 200);
0227     }
0228
0229     if (i == SERDES_START_WAIT_TIMES) {
0230         netdev_err(adpt->netdev, "error: ser/des failed to start\n");
0231         return -EIO;
0232     }
0233     /* Mask out all the SGMII Interrupt */
0234     writel(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
0235
0236     return 0;
0237 }