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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * QLogic qlcnic NIC Driver
0004  * Copyright (c) 2009-2013 QLogic Corporation
0005  */
0006 
0007 #include <linux/types.h>
0008 
0009 #include "qlcnic_sriov.h"
0010 #include "qlcnic.h"
0011 #include "qlcnic_83xx_hw.h"
0012 
0013 #define QLC_BC_COMMAND  0
0014 #define QLC_BC_RESPONSE 1
0015 
0016 #define QLC_MBOX_RESP_TIMEOUT       (10 * HZ)
0017 #define QLC_MBOX_CH_FREE_TIMEOUT    (10 * HZ)
0018 
0019 #define QLC_BC_MSG      0
0020 #define QLC_BC_CFREE        1
0021 #define QLC_BC_FLR      2
0022 #define QLC_BC_HDR_SZ       16
0023 #define QLC_BC_PAYLOAD_SZ   (1024 - QLC_BC_HDR_SZ)
0024 
0025 #define QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF        2048
0026 #define QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF  512
0027 
0028 #define QLC_83XX_VF_RESET_FAIL_THRESH   8
0029 #define QLC_BC_CMD_MAX_RETRY_CNT    5
0030 
0031 static void qlcnic_sriov_handle_async_issue_cmd(struct work_struct *work);
0032 static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter *);
0033 static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *, u32);
0034 static void qlcnic_sriov_vf_poll_dev_state(struct work_struct *);
0035 static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter *);
0036 static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *);
0037 static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter *,
0038                   struct qlcnic_cmd_args *);
0039 static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *, u8);
0040 static void qlcnic_sriov_process_bc_cmd(struct work_struct *);
0041 static int qlcnic_sriov_vf_shutdown(struct pci_dev *);
0042 static int qlcnic_sriov_vf_resume(struct qlcnic_adapter *);
0043 static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter *,
0044                     struct qlcnic_cmd_args *);
0045 
0046 static struct qlcnic_hardware_ops qlcnic_sriov_vf_hw_ops = {
0047     .read_crb           = qlcnic_83xx_read_crb,
0048     .write_crb          = qlcnic_83xx_write_crb,
0049     .read_reg           = qlcnic_83xx_rd_reg_indirect,
0050     .write_reg          = qlcnic_83xx_wrt_reg_indirect,
0051     .get_mac_address        = qlcnic_83xx_get_mac_address,
0052     .setup_intr         = qlcnic_83xx_setup_intr,
0053     .alloc_mbx_args         = qlcnic_83xx_alloc_mbx_args,
0054     .mbx_cmd            = qlcnic_sriov_issue_cmd,
0055     .get_func_no            = qlcnic_83xx_get_func_no,
0056     .api_lock           = qlcnic_83xx_cam_lock,
0057     .api_unlock         = qlcnic_83xx_cam_unlock,
0058     .process_lb_rcv_ring_diag   = qlcnic_83xx_process_rcv_ring_diag,
0059     .create_rx_ctx          = qlcnic_83xx_create_rx_ctx,
0060     .create_tx_ctx          = qlcnic_83xx_create_tx_ctx,
0061     .del_rx_ctx         = qlcnic_83xx_del_rx_ctx,
0062     .del_tx_ctx         = qlcnic_83xx_del_tx_ctx,
0063     .setup_link_event       = qlcnic_83xx_setup_link_event,
0064     .get_nic_info           = qlcnic_83xx_get_nic_info,
0065     .get_pci_info           = qlcnic_83xx_get_pci_info,
0066     .set_nic_info           = qlcnic_83xx_set_nic_info,
0067     .change_macvlan         = qlcnic_83xx_sre_macaddr_change,
0068     .napi_enable            = qlcnic_83xx_napi_enable,
0069     .napi_disable           = qlcnic_83xx_napi_disable,
0070     .config_intr_coal       = qlcnic_83xx_config_intr_coal,
0071     .config_rss         = qlcnic_83xx_config_rss,
0072     .config_hw_lro          = qlcnic_83xx_config_hw_lro,
0073     .config_promisc_mode        = qlcnic_83xx_nic_set_promisc,
0074     .change_l2_filter       = qlcnic_83xx_change_l2_filter,
0075     .get_board_info         = qlcnic_83xx_get_port_info,
0076     .free_mac_list          = qlcnic_sriov_vf_free_mac_list,
0077     .enable_sds_intr        = qlcnic_83xx_enable_sds_intr,
0078     .disable_sds_intr       = qlcnic_83xx_disable_sds_intr,
0079     .encap_rx_offload               = qlcnic_83xx_encap_rx_offload,
0080     .encap_tx_offload               = qlcnic_83xx_encap_tx_offload,
0081 };
0082 
0083 static struct qlcnic_nic_template qlcnic_sriov_vf_ops = {
0084     .config_bridged_mode    = qlcnic_config_bridged_mode,
0085     .config_led     = qlcnic_config_led,
0086     .cancel_idc_work        = qlcnic_sriov_vf_cancel_fw_work,
0087     .napi_add       = qlcnic_83xx_napi_add,
0088     .napi_del       = qlcnic_83xx_napi_del,
0089     .shutdown       = qlcnic_sriov_vf_shutdown,
0090     .resume         = qlcnic_sriov_vf_resume,
0091     .config_ipaddr      = qlcnic_83xx_config_ipaddr,
0092     .clear_legacy_intr  = qlcnic_83xx_clear_legacy_intr,
0093 };
0094 
0095 static const struct qlcnic_mailbox_metadata qlcnic_sriov_bc_mbx_tbl[] = {
0096     {QLCNIC_BC_CMD_CHANNEL_INIT, 2, 2},
0097     {QLCNIC_BC_CMD_CHANNEL_TERM, 2, 2},
0098     {QLCNIC_BC_CMD_GET_ACL, 3, 14},
0099     {QLCNIC_BC_CMD_CFG_GUEST_VLAN, 2, 2},
0100 };
0101 
0102 static inline bool qlcnic_sriov_bc_msg_check(u32 val)
0103 {
0104     return (val & (1 << QLC_BC_MSG)) ? true : false;
0105 }
0106 
0107 static inline bool qlcnic_sriov_channel_free_check(u32 val)
0108 {
0109     return (val & (1 << QLC_BC_CFREE)) ? true : false;
0110 }
0111 
0112 static inline bool qlcnic_sriov_flr_check(u32 val)
0113 {
0114     return (val & (1 << QLC_BC_FLR)) ? true : false;
0115 }
0116 
0117 static inline u8 qlcnic_sriov_target_func_id(u32 val)
0118 {
0119     return (val >> 4) & 0xff;
0120 }
0121 
0122 static int qlcnic_sriov_virtid_fn(struct qlcnic_adapter *adapter, int vf_id)
0123 {
0124     struct pci_dev *dev = adapter->pdev;
0125     int pos;
0126     u16 stride, offset;
0127 
0128     if (qlcnic_sriov_vf_check(adapter))
0129         return 0;
0130 
0131     pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
0132     if (!pos)
0133         return 0;
0134     pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset);
0135     pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &stride);
0136 
0137     return (dev->devfn + offset + stride * vf_id) & 0xff;
0138 }
0139 
0140 int qlcnic_sriov_init(struct qlcnic_adapter *adapter, int num_vfs)
0141 {
0142     struct qlcnic_sriov *sriov;
0143     struct qlcnic_back_channel *bc;
0144     struct workqueue_struct *wq;
0145     struct qlcnic_vport *vp;
0146     struct qlcnic_vf_info *vf;
0147     int err, i;
0148 
0149     if (!qlcnic_sriov_enable_check(adapter))
0150         return -EIO;
0151 
0152     sriov  = kzalloc(sizeof(struct qlcnic_sriov), GFP_KERNEL);
0153     if (!sriov)
0154         return -ENOMEM;
0155 
0156     adapter->ahw->sriov = sriov;
0157     sriov->num_vfs = num_vfs;
0158     bc = &sriov->bc;
0159     sriov->vf_info = kcalloc(num_vfs, sizeof(struct qlcnic_vf_info),
0160                  GFP_KERNEL);
0161     if (!sriov->vf_info) {
0162         err = -ENOMEM;
0163         goto qlcnic_free_sriov;
0164     }
0165 
0166     wq = create_singlethread_workqueue("bc-trans");
0167     if (wq == NULL) {
0168         err = -ENOMEM;
0169         dev_err(&adapter->pdev->dev,
0170             "Cannot create bc-trans workqueue\n");
0171         goto qlcnic_free_vf_info;
0172     }
0173 
0174     bc->bc_trans_wq = wq;
0175 
0176     wq = create_singlethread_workqueue("async");
0177     if (wq == NULL) {
0178         err = -ENOMEM;
0179         dev_err(&adapter->pdev->dev, "Cannot create async workqueue\n");
0180         goto qlcnic_destroy_trans_wq;
0181     }
0182 
0183     bc->bc_async_wq =  wq;
0184     INIT_LIST_HEAD(&bc->async_cmd_list);
0185     INIT_WORK(&bc->vf_async_work, qlcnic_sriov_handle_async_issue_cmd);
0186     spin_lock_init(&bc->queue_lock);
0187     bc->adapter = adapter;
0188 
0189     for (i = 0; i < num_vfs; i++) {
0190         vf = &sriov->vf_info[i];
0191         vf->adapter = adapter;
0192         vf->pci_func = qlcnic_sriov_virtid_fn(adapter, i);
0193         mutex_init(&vf->send_cmd_lock);
0194         spin_lock_init(&vf->vlan_list_lock);
0195         INIT_LIST_HEAD(&vf->rcv_act.wait_list);
0196         INIT_LIST_HEAD(&vf->rcv_pend.wait_list);
0197         spin_lock_init(&vf->rcv_act.lock);
0198         spin_lock_init(&vf->rcv_pend.lock);
0199         init_completion(&vf->ch_free_cmpl);
0200 
0201         INIT_WORK(&vf->trans_work, qlcnic_sriov_process_bc_cmd);
0202 
0203         if (qlcnic_sriov_pf_check(adapter)) {
0204             vp = kzalloc(sizeof(struct qlcnic_vport), GFP_KERNEL);
0205             if (!vp) {
0206                 err = -ENOMEM;
0207                 goto qlcnic_destroy_async_wq;
0208             }
0209             sriov->vf_info[i].vp = vp;
0210             vp->vlan_mode = QLC_GUEST_VLAN_MODE;
0211             vp->max_tx_bw = MAX_BW;
0212             vp->min_tx_bw = MIN_BW;
0213             vp->spoofchk = false;
0214             eth_random_addr(vp->mac);
0215             dev_info(&adapter->pdev->dev,
0216                  "MAC Address %pM is configured for VF %d\n",
0217                  vp->mac, i);
0218         }
0219     }
0220 
0221     return 0;
0222 
0223 qlcnic_destroy_async_wq:
0224     destroy_workqueue(bc->bc_async_wq);
0225 
0226 qlcnic_destroy_trans_wq:
0227     destroy_workqueue(bc->bc_trans_wq);
0228 
0229 qlcnic_free_vf_info:
0230     kfree(sriov->vf_info);
0231 
0232 qlcnic_free_sriov:
0233     kfree(adapter->ahw->sriov);
0234     return err;
0235 }
0236 
0237 void qlcnic_sriov_cleanup_list(struct qlcnic_trans_list *t_list)
0238 {
0239     struct qlcnic_bc_trans *trans;
0240     struct qlcnic_cmd_args cmd;
0241     unsigned long flags;
0242 
0243     spin_lock_irqsave(&t_list->lock, flags);
0244 
0245     while (!list_empty(&t_list->wait_list)) {
0246         trans = list_first_entry(&t_list->wait_list,
0247                      struct qlcnic_bc_trans, list);
0248         list_del(&trans->list);
0249         t_list->count--;
0250         cmd.req.arg = (u32 *)trans->req_pay;
0251         cmd.rsp.arg = (u32 *)trans->rsp_pay;
0252         qlcnic_free_mbx_args(&cmd);
0253         qlcnic_sriov_cleanup_transaction(trans);
0254     }
0255 
0256     spin_unlock_irqrestore(&t_list->lock, flags);
0257 }
0258 
0259 void __qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter)
0260 {
0261     struct qlcnic_sriov *sriov = adapter->ahw->sriov;
0262     struct qlcnic_back_channel *bc = &sriov->bc;
0263     struct qlcnic_vf_info *vf;
0264     int i;
0265 
0266     if (!qlcnic_sriov_enable_check(adapter))
0267         return;
0268 
0269     qlcnic_sriov_cleanup_async_list(bc);
0270     destroy_workqueue(bc->bc_async_wq);
0271 
0272     for (i = 0; i < sriov->num_vfs; i++) {
0273         vf = &sriov->vf_info[i];
0274         qlcnic_sriov_cleanup_list(&vf->rcv_pend);
0275         cancel_work_sync(&vf->trans_work);
0276         qlcnic_sriov_cleanup_list(&vf->rcv_act);
0277     }
0278 
0279     destroy_workqueue(bc->bc_trans_wq);
0280 
0281     for (i = 0; i < sriov->num_vfs; i++)
0282         kfree(sriov->vf_info[i].vp);
0283 
0284     kfree(sriov->vf_info);
0285     kfree(adapter->ahw->sriov);
0286 }
0287 
0288 static void qlcnic_sriov_vf_cleanup(struct qlcnic_adapter *adapter)
0289 {
0290     qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
0291     qlcnic_sriov_cfg_bc_intr(adapter, 0);
0292     __qlcnic_sriov_cleanup(adapter);
0293 }
0294 
0295 void qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter)
0296 {
0297     if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state))
0298         return;
0299 
0300     qlcnic_sriov_free_vlans(adapter);
0301 
0302     if (qlcnic_sriov_pf_check(adapter))
0303         qlcnic_sriov_pf_cleanup(adapter);
0304 
0305     if (qlcnic_sriov_vf_check(adapter))
0306         qlcnic_sriov_vf_cleanup(adapter);
0307 }
0308 
0309 static int qlcnic_sriov_post_bc_msg(struct qlcnic_adapter *adapter, u32 *hdr,
0310                     u32 *pay, u8 pci_func, u8 size)
0311 {
0312     struct qlcnic_hardware_context *ahw = adapter->ahw;
0313     struct qlcnic_mailbox *mbx = ahw->mailbox;
0314     struct qlcnic_cmd_args cmd;
0315     unsigned long timeout;
0316     int err;
0317 
0318     memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
0319     cmd.hdr = hdr;
0320     cmd.pay = pay;
0321     cmd.pay_size = size;
0322     cmd.func_num = pci_func;
0323     cmd.op_type = QLC_83XX_MBX_POST_BC_OP;
0324     cmd.cmd_op = ((struct qlcnic_bc_hdr *)hdr)->cmd_op;
0325 
0326     err = mbx->ops->enqueue_cmd(adapter, &cmd, &timeout);
0327     if (err) {
0328         dev_err(&adapter->pdev->dev,
0329             "%s: Mailbox not available, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
0330             __func__, cmd.cmd_op, cmd.type, ahw->pci_func,
0331             ahw->op_mode);
0332         return err;
0333     }
0334 
0335     if (!wait_for_completion_timeout(&cmd.completion, timeout)) {
0336         dev_err(&adapter->pdev->dev,
0337             "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
0338             __func__, cmd.cmd_op, cmd.type, ahw->pci_func,
0339             ahw->op_mode);
0340         flush_workqueue(mbx->work_q);
0341     }
0342 
0343     return cmd.rsp_opcode;
0344 }
0345 
0346 static void qlcnic_sriov_vf_cfg_buff_desc(struct qlcnic_adapter *adapter)
0347 {
0348     adapter->num_rxd = QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF;
0349     adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
0350     adapter->num_jumbo_rxd = QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF;
0351     adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
0352     adapter->num_txd = MAX_CMD_DESCRIPTORS;
0353     adapter->max_rds_rings = MAX_RDS_RINGS;
0354 }
0355 
0356 int qlcnic_sriov_get_vf_vport_info(struct qlcnic_adapter *adapter,
0357                    struct qlcnic_info *npar_info, u16 vport_id)
0358 {
0359     struct device *dev = &adapter->pdev->dev;
0360     struct qlcnic_cmd_args cmd;
0361     int err;
0362     u32 status;
0363 
0364     err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
0365     if (err)
0366         return err;
0367 
0368     cmd.req.arg[1] = vport_id << 16 | 0x1;
0369     err = qlcnic_issue_cmd(adapter, &cmd);
0370     if (err) {
0371         dev_err(&adapter->pdev->dev,
0372             "Failed to get vport info, err=%d\n", err);
0373         qlcnic_free_mbx_args(&cmd);
0374         return err;
0375     }
0376 
0377     status = cmd.rsp.arg[2] & 0xffff;
0378     if (status & BIT_0)
0379         npar_info->min_tx_bw = MSW(cmd.rsp.arg[2]);
0380     if (status & BIT_1)
0381         npar_info->max_tx_bw = LSW(cmd.rsp.arg[3]);
0382     if (status & BIT_2)
0383         npar_info->max_tx_ques = MSW(cmd.rsp.arg[3]);
0384     if (status & BIT_3)
0385         npar_info->max_tx_mac_filters = LSW(cmd.rsp.arg[4]);
0386     if (status & BIT_4)
0387         npar_info->max_rx_mcast_mac_filters = MSW(cmd.rsp.arg[4]);
0388     if (status & BIT_5)
0389         npar_info->max_rx_ucast_mac_filters = LSW(cmd.rsp.arg[5]);
0390     if (status & BIT_6)
0391         npar_info->max_rx_ip_addr = MSW(cmd.rsp.arg[5]);
0392     if (status & BIT_7)
0393         npar_info->max_rx_lro_flow = LSW(cmd.rsp.arg[6]);
0394     if (status & BIT_8)
0395         npar_info->max_rx_status_rings = MSW(cmd.rsp.arg[6]);
0396     if (status & BIT_9)
0397         npar_info->max_rx_buf_rings = LSW(cmd.rsp.arg[7]);
0398 
0399     npar_info->max_rx_ques = MSW(cmd.rsp.arg[7]);
0400     npar_info->max_tx_vlan_keys = LSW(cmd.rsp.arg[8]);
0401     npar_info->max_local_ipv6_addrs = MSW(cmd.rsp.arg[8]);
0402     npar_info->max_remote_ipv6_addrs = LSW(cmd.rsp.arg[9]);
0403 
0404     dev_info(dev, "\n\tmin_tx_bw: %d, max_tx_bw: %d max_tx_ques: %d,\n"
0405          "\tmax_tx_mac_filters: %d max_rx_mcast_mac_filters: %d,\n"
0406          "\tmax_rx_ucast_mac_filters: 0x%x, max_rx_ip_addr: %d,\n"
0407          "\tmax_rx_lro_flow: %d max_rx_status_rings: %d,\n"
0408          "\tmax_rx_buf_rings: %d, max_rx_ques: %d, max_tx_vlan_keys %d\n"
0409          "\tlocal_ipv6_addr: %d, remote_ipv6_addr: %d\n",
0410          npar_info->min_tx_bw, npar_info->max_tx_bw,
0411          npar_info->max_tx_ques, npar_info->max_tx_mac_filters,
0412          npar_info->max_rx_mcast_mac_filters,
0413          npar_info->max_rx_ucast_mac_filters, npar_info->max_rx_ip_addr,
0414          npar_info->max_rx_lro_flow, npar_info->max_rx_status_rings,
0415          npar_info->max_rx_buf_rings, npar_info->max_rx_ques,
0416          npar_info->max_tx_vlan_keys, npar_info->max_local_ipv6_addrs,
0417          npar_info->max_remote_ipv6_addrs);
0418 
0419     qlcnic_free_mbx_args(&cmd);
0420     return err;
0421 }
0422 
0423 static int qlcnic_sriov_set_pvid_mode(struct qlcnic_adapter *adapter,
0424                       struct qlcnic_cmd_args *cmd)
0425 {
0426     adapter->rx_pvid = MSW(cmd->rsp.arg[1]) & 0xffff;
0427     adapter->flags &= ~QLCNIC_TAGGING_ENABLED;
0428     return 0;
0429 }
0430 
0431 static int qlcnic_sriov_set_guest_vlan_mode(struct qlcnic_adapter *adapter,
0432                         struct qlcnic_cmd_args *cmd)
0433 {
0434     struct qlcnic_sriov *sriov = adapter->ahw->sriov;
0435     int i, num_vlans, ret;
0436     u16 *vlans;
0437 
0438     if (sriov->allowed_vlans)
0439         return 0;
0440 
0441     sriov->any_vlan = cmd->rsp.arg[2] & 0xf;
0442     sriov->num_allowed_vlans = cmd->rsp.arg[2] >> 16;
0443     dev_info(&adapter->pdev->dev, "Number of allowed Guest VLANs = %d\n",
0444          sriov->num_allowed_vlans);
0445 
0446     ret = qlcnic_sriov_alloc_vlans(adapter);
0447     if (ret)
0448         return ret;
0449 
0450     if (!sriov->any_vlan)
0451         return 0;
0452 
0453     num_vlans = sriov->num_allowed_vlans;
0454     sriov->allowed_vlans = kcalloc(num_vlans, sizeof(u16), GFP_KERNEL);
0455     if (!sriov->allowed_vlans)
0456         return -ENOMEM;
0457 
0458     vlans = (u16 *)&cmd->rsp.arg[3];
0459     for (i = 0; i < num_vlans; i++)
0460         sriov->allowed_vlans[i] = vlans[i];
0461 
0462     return 0;
0463 }
0464 
0465 static int qlcnic_sriov_get_vf_acl(struct qlcnic_adapter *adapter)
0466 {
0467     struct qlcnic_sriov *sriov = adapter->ahw->sriov;
0468     struct qlcnic_cmd_args cmd;
0469     int ret = 0;
0470 
0471     memset(&cmd, 0, sizeof(cmd));
0472     ret = qlcnic_sriov_alloc_bc_mbx_args(&cmd, QLCNIC_BC_CMD_GET_ACL);
0473     if (ret)
0474         return ret;
0475 
0476     ret = qlcnic_issue_cmd(adapter, &cmd);
0477     if (ret) {
0478         dev_err(&adapter->pdev->dev, "Failed to get ACL, err=%d\n",
0479             ret);
0480     } else {
0481         sriov->vlan_mode = cmd.rsp.arg[1] & 0x3;
0482         switch (sriov->vlan_mode) {
0483         case QLC_GUEST_VLAN_MODE:
0484             ret = qlcnic_sriov_set_guest_vlan_mode(adapter, &cmd);
0485             break;
0486         case QLC_PVID_MODE:
0487             ret = qlcnic_sriov_set_pvid_mode(adapter, &cmd);
0488             break;
0489         }
0490     }
0491 
0492     qlcnic_free_mbx_args(&cmd);
0493     return ret;
0494 }
0495 
0496 static int qlcnic_sriov_vf_init_driver(struct qlcnic_adapter *adapter)
0497 {
0498     struct qlcnic_hardware_context *ahw = adapter->ahw;
0499     struct qlcnic_info nic_info;
0500     int err;
0501 
0502     err = qlcnic_sriov_get_vf_vport_info(adapter, &nic_info, 0);
0503     if (err)
0504         return err;
0505 
0506     ahw->max_mc_count = nic_info.max_rx_mcast_mac_filters;
0507 
0508     err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
0509     if (err)
0510         return -EIO;
0511 
0512     if (qlcnic_83xx_get_port_info(adapter))
0513         return -EIO;
0514 
0515     qlcnic_sriov_vf_cfg_buff_desc(adapter);
0516     adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
0517     dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
0518          adapter->ahw->fw_hal_version);
0519 
0520     ahw->physical_port = (u8) nic_info.phys_port;
0521     ahw->switch_mode = nic_info.switch_mode;
0522     ahw->max_mtu = nic_info.max_mtu;
0523     ahw->op_mode = nic_info.op_mode;
0524     ahw->capabilities = nic_info.capabilities;
0525     return 0;
0526 }
0527 
0528 static int qlcnic_sriov_setup_vf(struct qlcnic_adapter *adapter)
0529 {
0530     int err;
0531 
0532     adapter->flags |= QLCNIC_VLAN_FILTERING;
0533     adapter->ahw->total_nic_func = 1;
0534     INIT_LIST_HEAD(&adapter->vf_mc_list);
0535     if (!qlcnic_use_msi_x && !!qlcnic_use_msi)
0536         dev_warn(&adapter->pdev->dev,
0537              "Device does not support MSI interrupts\n");
0538 
0539     /* compute and set default and max tx/sds rings */
0540     qlcnic_set_tx_ring_count(adapter, QLCNIC_SINGLE_RING);
0541     qlcnic_set_sds_ring_count(adapter, QLCNIC_SINGLE_RING);
0542 
0543     err = qlcnic_setup_intr(adapter);
0544     if (err) {
0545         dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
0546         goto err_out_disable_msi;
0547     }
0548 
0549     err = qlcnic_83xx_setup_mbx_intr(adapter);
0550     if (err)
0551         goto err_out_disable_msi;
0552 
0553     err = qlcnic_sriov_init(adapter, 1);
0554     if (err)
0555         goto err_out_disable_mbx_intr;
0556 
0557     err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
0558     if (err)
0559         goto err_out_cleanup_sriov;
0560 
0561     err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
0562     if (err)
0563         goto err_out_disable_bc_intr;
0564 
0565     err = qlcnic_sriov_vf_init_driver(adapter);
0566     if (err)
0567         goto err_out_send_channel_term;
0568 
0569     err = qlcnic_sriov_get_vf_acl(adapter);
0570     if (err)
0571         goto err_out_send_channel_term;
0572 
0573     err = qlcnic_setup_netdev(adapter, adapter->netdev);
0574     if (err)
0575         goto err_out_send_channel_term;
0576 
0577     pci_set_drvdata(adapter->pdev, adapter);
0578     dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n",
0579          adapter->netdev->name);
0580 
0581     qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
0582                  adapter->ahw->idc.delay);
0583     return 0;
0584 
0585 err_out_send_channel_term:
0586     qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
0587 
0588 err_out_disable_bc_intr:
0589     qlcnic_sriov_cfg_bc_intr(adapter, 0);
0590 
0591 err_out_cleanup_sriov:
0592     __qlcnic_sriov_cleanup(adapter);
0593 
0594 err_out_disable_mbx_intr:
0595     qlcnic_83xx_free_mbx_intr(adapter);
0596 
0597 err_out_disable_msi:
0598     qlcnic_teardown_intr(adapter);
0599     return err;
0600 }
0601 
0602 static int qlcnic_sriov_check_dev_ready(struct qlcnic_adapter *adapter)
0603 {
0604     u32 state;
0605 
0606     do {
0607         msleep(20);
0608         if (++adapter->fw_fail_cnt > QLC_BC_CMD_MAX_RETRY_CNT)
0609             return -EIO;
0610         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
0611     } while (state != QLC_83XX_IDC_DEV_READY);
0612 
0613     return 0;
0614 }
0615 
0616 int qlcnic_sriov_vf_init(struct qlcnic_adapter *adapter)
0617 {
0618     struct qlcnic_hardware_context *ahw = adapter->ahw;
0619     int err;
0620 
0621     set_bit(QLC_83XX_MODULE_LOADED, &ahw->idc.status);
0622     ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
0623     ahw->reset_context = 0;
0624     adapter->fw_fail_cnt = 0;
0625     ahw->msix_supported = 1;
0626     adapter->need_fw_reset = 0;
0627     adapter->flags |= QLCNIC_TX_INTR_SHARED;
0628 
0629     err = qlcnic_sriov_check_dev_ready(adapter);
0630     if (err)
0631         return err;
0632 
0633     err = qlcnic_sriov_setup_vf(adapter);
0634     if (err)
0635         return err;
0636 
0637     if (qlcnic_read_mac_addr(adapter))
0638         dev_warn(&adapter->pdev->dev, "failed to read mac addr\n");
0639 
0640     INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
0641 
0642     clear_bit(__QLCNIC_RESETTING, &adapter->state);
0643     return 0;
0644 }
0645 
0646 void qlcnic_sriov_vf_set_ops(struct qlcnic_adapter *adapter)
0647 {
0648     struct qlcnic_hardware_context *ahw = adapter->ahw;
0649 
0650     ahw->op_mode = QLCNIC_SRIOV_VF_FUNC;
0651     dev_info(&adapter->pdev->dev,
0652          "HAL Version: %d Non Privileged SRIOV function\n",
0653          ahw->fw_hal_version);
0654     adapter->nic_ops = &qlcnic_sriov_vf_ops;
0655     set_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state);
0656     return;
0657 }
0658 
0659 void qlcnic_sriov_vf_register_map(struct qlcnic_hardware_context *ahw)
0660 {
0661     ahw->hw_ops     = &qlcnic_sriov_vf_hw_ops;
0662     ahw->reg_tbl        = (u32 *)qlcnic_83xx_reg_tbl;
0663     ahw->ext_reg_tbl    = (u32 *)qlcnic_83xx_ext_reg_tbl;
0664 }
0665 
0666 static u32 qlcnic_sriov_get_bc_paysize(u32 real_pay_size, u8 curr_frag)
0667 {
0668     u32 pay_size;
0669 
0670     pay_size = real_pay_size / ((curr_frag + 1) * QLC_BC_PAYLOAD_SZ);
0671 
0672     if (pay_size)
0673         pay_size = QLC_BC_PAYLOAD_SZ;
0674     else
0675         pay_size = real_pay_size % QLC_BC_PAYLOAD_SZ;
0676 
0677     return pay_size;
0678 }
0679 
0680 int qlcnic_sriov_func_to_index(struct qlcnic_adapter *adapter, u8 pci_func)
0681 {
0682     struct qlcnic_vf_info *vf_info = adapter->ahw->sriov->vf_info;
0683     u8 i;
0684 
0685     if (qlcnic_sriov_vf_check(adapter))
0686         return 0;
0687 
0688     for (i = 0; i < adapter->ahw->sriov->num_vfs; i++) {
0689         if (vf_info[i].pci_func == pci_func)
0690             return i;
0691     }
0692 
0693     return -EINVAL;
0694 }
0695 
0696 static inline int qlcnic_sriov_alloc_bc_trans(struct qlcnic_bc_trans **trans)
0697 {
0698     *trans = kzalloc(sizeof(struct qlcnic_bc_trans), GFP_ATOMIC);
0699     if (!*trans)
0700         return -ENOMEM;
0701 
0702     init_completion(&(*trans)->resp_cmpl);
0703     return 0;
0704 }
0705 
0706 static inline int qlcnic_sriov_alloc_bc_msg(struct qlcnic_bc_hdr **hdr,
0707                         u32 size)
0708 {
0709     *hdr = kcalloc(size, sizeof(struct qlcnic_bc_hdr), GFP_ATOMIC);
0710     if (!*hdr)
0711         return -ENOMEM;
0712 
0713     return 0;
0714 }
0715 
0716 static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *mbx, u32 type)
0717 {
0718     const struct qlcnic_mailbox_metadata *mbx_tbl;
0719     int i, size;
0720 
0721     mbx_tbl = qlcnic_sriov_bc_mbx_tbl;
0722     size = ARRAY_SIZE(qlcnic_sriov_bc_mbx_tbl);
0723 
0724     for (i = 0; i < size; i++) {
0725         if (type == mbx_tbl[i].cmd) {
0726             mbx->op_type = QLC_BC_CMD;
0727             mbx->req.num = mbx_tbl[i].in_args;
0728             mbx->rsp.num = mbx_tbl[i].out_args;
0729             mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
0730                            GFP_ATOMIC);
0731             if (!mbx->req.arg)
0732                 return -ENOMEM;
0733             mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
0734                            GFP_ATOMIC);
0735             if (!mbx->rsp.arg) {
0736                 kfree(mbx->req.arg);
0737                 mbx->req.arg = NULL;
0738                 return -ENOMEM;
0739             }
0740             mbx->req.arg[0] = (type | (mbx->req.num << 16) |
0741                        (3 << 29));
0742             mbx->rsp.arg[0] = (type & 0xffff) | mbx->rsp.num << 16;
0743             return 0;
0744         }
0745     }
0746     return -EINVAL;
0747 }
0748 
0749 static int qlcnic_sriov_prepare_bc_hdr(struct qlcnic_bc_trans *trans,
0750                        struct qlcnic_cmd_args *cmd,
0751                        u16 seq, u8 msg_type)
0752 {
0753     struct qlcnic_bc_hdr *hdr;
0754     int i;
0755     u32 num_regs, bc_pay_sz;
0756     u16 remainder;
0757     u8 cmd_op, num_frags, t_num_frags;
0758 
0759     bc_pay_sz = QLC_BC_PAYLOAD_SZ;
0760     if (msg_type == QLC_BC_COMMAND) {
0761         trans->req_pay = (struct qlcnic_bc_payload *)cmd->req.arg;
0762         trans->rsp_pay = (struct qlcnic_bc_payload *)cmd->rsp.arg;
0763         num_regs = cmd->req.num;
0764         trans->req_pay_size = (num_regs * 4);
0765         num_regs = cmd->rsp.num;
0766         trans->rsp_pay_size = (num_regs * 4);
0767         cmd_op = cmd->req.arg[0] & 0xff;
0768         remainder = (trans->req_pay_size) % (bc_pay_sz);
0769         num_frags = (trans->req_pay_size) / (bc_pay_sz);
0770         if (remainder)
0771             num_frags++;
0772         t_num_frags = num_frags;
0773         if (qlcnic_sriov_alloc_bc_msg(&trans->req_hdr, num_frags))
0774             return -ENOMEM;
0775         remainder = (trans->rsp_pay_size) % (bc_pay_sz);
0776         num_frags = (trans->rsp_pay_size) / (bc_pay_sz);
0777         if (remainder)
0778             num_frags++;
0779         if (qlcnic_sriov_alloc_bc_msg(&trans->rsp_hdr, num_frags))
0780             return -ENOMEM;
0781         num_frags  = t_num_frags;
0782         hdr = trans->req_hdr;
0783     }  else {
0784         cmd->req.arg = (u32 *)trans->req_pay;
0785         cmd->rsp.arg = (u32 *)trans->rsp_pay;
0786         cmd_op = cmd->req.arg[0] & 0xff;
0787         cmd->cmd_op = cmd_op;
0788         remainder = (trans->rsp_pay_size) % (bc_pay_sz);
0789         num_frags = (trans->rsp_pay_size) / (bc_pay_sz);
0790         if (remainder)
0791             num_frags++;
0792         cmd->req.num = trans->req_pay_size / 4;
0793         cmd->rsp.num = trans->rsp_pay_size / 4;
0794         hdr = trans->rsp_hdr;
0795         cmd->op_type = trans->req_hdr->op_type;
0796     }
0797 
0798     trans->trans_id = seq;
0799     trans->cmd_id = cmd_op;
0800     for (i = 0; i < num_frags; i++) {
0801         hdr[i].version = 2;
0802         hdr[i].msg_type = msg_type;
0803         hdr[i].op_type = cmd->op_type;
0804         hdr[i].num_cmds = 1;
0805         hdr[i].num_frags = num_frags;
0806         hdr[i].frag_num = i + 1;
0807         hdr[i].cmd_op = cmd_op;
0808         hdr[i].seq_id = seq;
0809     }
0810     return 0;
0811 }
0812 
0813 static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *trans)
0814 {
0815     if (!trans)
0816         return;
0817     kfree(trans->req_hdr);
0818     kfree(trans->rsp_hdr);
0819     kfree(trans);
0820 }
0821 
0822 static int qlcnic_sriov_clear_trans(struct qlcnic_vf_info *vf,
0823                     struct qlcnic_bc_trans *trans, u8 type)
0824 {
0825     struct qlcnic_trans_list *t_list;
0826     unsigned long flags;
0827     int ret = 0;
0828 
0829     if (type == QLC_BC_RESPONSE) {
0830         t_list = &vf->rcv_act;
0831         spin_lock_irqsave(&t_list->lock, flags);
0832         t_list->count--;
0833         list_del(&trans->list);
0834         if (t_list->count > 0)
0835             ret = 1;
0836         spin_unlock_irqrestore(&t_list->lock, flags);
0837     }
0838     if (type == QLC_BC_COMMAND) {
0839         while (test_and_set_bit(QLC_BC_VF_SEND, &vf->state))
0840             msleep(100);
0841         vf->send_cmd = NULL;
0842         clear_bit(QLC_BC_VF_SEND, &vf->state);
0843     }
0844     return ret;
0845 }
0846 
0847 static void qlcnic_sriov_schedule_bc_cmd(struct qlcnic_sriov *sriov,
0848                      struct qlcnic_vf_info *vf,
0849                      work_func_t func)
0850 {
0851     if (test_bit(QLC_BC_VF_FLR, &vf->state) ||
0852         vf->adapter->need_fw_reset)
0853         return;
0854 
0855     queue_work(sriov->bc.bc_trans_wq, &vf->trans_work);
0856 }
0857 
0858 static inline void qlcnic_sriov_wait_for_resp(struct qlcnic_bc_trans *trans)
0859 {
0860     struct completion *cmpl = &trans->resp_cmpl;
0861 
0862     if (wait_for_completion_timeout(cmpl, QLC_MBOX_RESP_TIMEOUT))
0863         trans->trans_state = QLC_END;
0864     else
0865         trans->trans_state = QLC_ABORT;
0866 
0867     return;
0868 }
0869 
0870 static void qlcnic_sriov_handle_multi_frags(struct qlcnic_bc_trans *trans,
0871                         u8 type)
0872 {
0873     if (type == QLC_BC_RESPONSE) {
0874         trans->curr_rsp_frag++;
0875         if (trans->curr_rsp_frag < trans->rsp_hdr->num_frags)
0876             trans->trans_state = QLC_INIT;
0877         else
0878             trans->trans_state = QLC_END;
0879     } else {
0880         trans->curr_req_frag++;
0881         if (trans->curr_req_frag < trans->req_hdr->num_frags)
0882             trans->trans_state = QLC_INIT;
0883         else
0884             trans->trans_state = QLC_WAIT_FOR_RESP;
0885     }
0886 }
0887 
0888 static void qlcnic_sriov_wait_for_channel_free(struct qlcnic_bc_trans *trans,
0889                            u8 type)
0890 {
0891     struct qlcnic_vf_info *vf = trans->vf;
0892     struct completion *cmpl = &vf->ch_free_cmpl;
0893 
0894     if (!wait_for_completion_timeout(cmpl, QLC_MBOX_CH_FREE_TIMEOUT)) {
0895         trans->trans_state = QLC_ABORT;
0896         return;
0897     }
0898 
0899     clear_bit(QLC_BC_VF_CHANNEL, &vf->state);
0900     qlcnic_sriov_handle_multi_frags(trans, type);
0901 }
0902 
0903 static void qlcnic_sriov_pull_bc_msg(struct qlcnic_adapter *adapter,
0904                      u32 *hdr, u32 *pay, u32 size)
0905 {
0906     struct qlcnic_hardware_context *ahw = adapter->ahw;
0907     u8 i, max = 2, hdr_size, j;
0908 
0909     hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
0910     max = (size / sizeof(u32)) + hdr_size;
0911 
0912     for (i = 2, j = 0; j < hdr_size; i++, j++)
0913         *(hdr++) = readl(QLCNIC_MBX_FW(ahw, i));
0914     for (; j < max; i++, j++)
0915         *(pay++) = readl(QLCNIC_MBX_FW(ahw, i));
0916 }
0917 
0918 static int __qlcnic_sriov_issue_bc_post(struct qlcnic_vf_info *vf)
0919 {
0920     int ret = -EBUSY;
0921     u32 timeout = 10000;
0922 
0923     do {
0924         if (!test_and_set_bit(QLC_BC_VF_CHANNEL, &vf->state)) {
0925             ret = 0;
0926             break;
0927         }
0928         mdelay(1);
0929     } while (--timeout);
0930 
0931     return ret;
0932 }
0933 
0934 static int qlcnic_sriov_issue_bc_post(struct qlcnic_bc_trans *trans, u8 type)
0935 {
0936     struct qlcnic_vf_info *vf = trans->vf;
0937     u32 pay_size;
0938     u32 *hdr, *pay;
0939     int ret;
0940     u8 pci_func = trans->func_id;
0941 
0942     if (__qlcnic_sriov_issue_bc_post(vf))
0943         return -EBUSY;
0944 
0945     if (type == QLC_BC_COMMAND) {
0946         hdr = (u32 *)(trans->req_hdr + trans->curr_req_frag);
0947         pay = (u32 *)(trans->req_pay + trans->curr_req_frag);
0948         pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
0949                                trans->curr_req_frag);
0950         pay_size = (pay_size / sizeof(u32));
0951     } else {
0952         hdr = (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag);
0953         pay = (u32 *)(trans->rsp_pay + trans->curr_rsp_frag);
0954         pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size,
0955                                trans->curr_rsp_frag);
0956         pay_size = (pay_size / sizeof(u32));
0957     }
0958 
0959     ret = qlcnic_sriov_post_bc_msg(vf->adapter, hdr, pay,
0960                        pci_func, pay_size);
0961     return ret;
0962 }
0963 
0964 static int __qlcnic_sriov_send_bc_msg(struct qlcnic_bc_trans *trans,
0965                       struct qlcnic_vf_info *vf, u8 type)
0966 {
0967     bool flag = true;
0968     int err = -EIO;
0969 
0970     while (flag) {
0971         if (test_bit(QLC_BC_VF_FLR, &vf->state) ||
0972             vf->adapter->need_fw_reset)
0973             trans->trans_state = QLC_ABORT;
0974 
0975         switch (trans->trans_state) {
0976         case QLC_INIT:
0977             trans->trans_state = QLC_WAIT_FOR_CHANNEL_FREE;
0978             if (qlcnic_sriov_issue_bc_post(trans, type))
0979                 trans->trans_state = QLC_ABORT;
0980             break;
0981         case QLC_WAIT_FOR_CHANNEL_FREE:
0982             qlcnic_sriov_wait_for_channel_free(trans, type);
0983             break;
0984         case QLC_WAIT_FOR_RESP:
0985             qlcnic_sriov_wait_for_resp(trans);
0986             break;
0987         case QLC_END:
0988             err = 0;
0989             flag = false;
0990             break;
0991         case QLC_ABORT:
0992             err = -EIO;
0993             flag = false;
0994             clear_bit(QLC_BC_VF_CHANNEL, &vf->state);
0995             break;
0996         default:
0997             err = -EIO;
0998             flag = false;
0999         }
1000     }
1001     return err;
1002 }
1003 
1004 static int qlcnic_sriov_send_bc_cmd(struct qlcnic_adapter *adapter,
1005                     struct qlcnic_bc_trans *trans, int pci_func)
1006 {
1007     struct qlcnic_vf_info *vf;
1008     int err, index = qlcnic_sriov_func_to_index(adapter, pci_func);
1009 
1010     if (index < 0)
1011         return -EIO;
1012 
1013     vf = &adapter->ahw->sriov->vf_info[index];
1014     trans->vf = vf;
1015     trans->func_id = pci_func;
1016 
1017     if (!test_bit(QLC_BC_VF_STATE, &vf->state)) {
1018         if (qlcnic_sriov_pf_check(adapter))
1019             return -EIO;
1020         if (qlcnic_sriov_vf_check(adapter) &&
1021             trans->cmd_id != QLCNIC_BC_CMD_CHANNEL_INIT)
1022             return -EIO;
1023     }
1024 
1025     mutex_lock(&vf->send_cmd_lock);
1026     vf->send_cmd = trans;
1027     err = __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_COMMAND);
1028     qlcnic_sriov_clear_trans(vf, trans, QLC_BC_COMMAND);
1029     mutex_unlock(&vf->send_cmd_lock);
1030     return err;
1031 }
1032 
1033 static void __qlcnic_sriov_process_bc_cmd(struct qlcnic_adapter *adapter,
1034                       struct qlcnic_bc_trans *trans,
1035                       struct qlcnic_cmd_args *cmd)
1036 {
1037 #ifdef CONFIG_QLCNIC_SRIOV
1038     if (qlcnic_sriov_pf_check(adapter)) {
1039         qlcnic_sriov_pf_process_bc_cmd(adapter, trans, cmd);
1040         return;
1041     }
1042 #endif
1043     cmd->rsp.arg[0] |= (0x9 << 25);
1044     return;
1045 }
1046 
1047 static void qlcnic_sriov_process_bc_cmd(struct work_struct *work)
1048 {
1049     struct qlcnic_vf_info *vf = container_of(work, struct qlcnic_vf_info,
1050                          trans_work);
1051     struct qlcnic_bc_trans *trans = NULL;
1052     struct qlcnic_adapter *adapter  = vf->adapter;
1053     struct qlcnic_cmd_args cmd;
1054     u8 req;
1055 
1056     if (adapter->need_fw_reset)
1057         return;
1058 
1059     if (test_bit(QLC_BC_VF_FLR, &vf->state))
1060         return;
1061 
1062     memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
1063     trans = list_first_entry(&vf->rcv_act.wait_list,
1064                  struct qlcnic_bc_trans, list);
1065     adapter = vf->adapter;
1066 
1067     if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, trans->req_hdr->seq_id,
1068                     QLC_BC_RESPONSE))
1069         goto cleanup_trans;
1070 
1071     __qlcnic_sriov_process_bc_cmd(adapter, trans, &cmd);
1072     trans->trans_state = QLC_INIT;
1073     __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_RESPONSE);
1074 
1075 cleanup_trans:
1076     qlcnic_free_mbx_args(&cmd);
1077     req = qlcnic_sriov_clear_trans(vf, trans, QLC_BC_RESPONSE);
1078     qlcnic_sriov_cleanup_transaction(trans);
1079     if (req)
1080         qlcnic_sriov_schedule_bc_cmd(adapter->ahw->sriov, vf,
1081                          qlcnic_sriov_process_bc_cmd);
1082 }
1083 
1084 static void qlcnic_sriov_handle_bc_resp(struct qlcnic_bc_hdr *hdr,
1085                     struct qlcnic_vf_info *vf)
1086 {
1087     struct qlcnic_bc_trans *trans;
1088     u32 pay_size;
1089 
1090     if (test_and_set_bit(QLC_BC_VF_SEND, &vf->state))
1091         return;
1092 
1093     trans = vf->send_cmd;
1094 
1095     if (trans == NULL)
1096         goto clear_send;
1097 
1098     if (trans->trans_id != hdr->seq_id)
1099         goto clear_send;
1100 
1101     pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size,
1102                            trans->curr_rsp_frag);
1103     qlcnic_sriov_pull_bc_msg(vf->adapter,
1104                  (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag),
1105                  (u32 *)(trans->rsp_pay + trans->curr_rsp_frag),
1106                  pay_size);
1107     if (++trans->curr_rsp_frag < trans->rsp_hdr->num_frags)
1108         goto clear_send;
1109 
1110     complete(&trans->resp_cmpl);
1111 
1112 clear_send:
1113     clear_bit(QLC_BC_VF_SEND, &vf->state);
1114 }
1115 
1116 int __qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov,
1117                 struct qlcnic_vf_info *vf,
1118                 struct qlcnic_bc_trans *trans)
1119 {
1120     struct qlcnic_trans_list *t_list = &vf->rcv_act;
1121 
1122     t_list->count++;
1123     list_add_tail(&trans->list, &t_list->wait_list);
1124     if (t_list->count == 1)
1125         qlcnic_sriov_schedule_bc_cmd(sriov, vf,
1126                          qlcnic_sriov_process_bc_cmd);
1127     return 0;
1128 }
1129 
1130 static int qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov,
1131                      struct qlcnic_vf_info *vf,
1132                      struct qlcnic_bc_trans *trans)
1133 {
1134     struct qlcnic_trans_list *t_list = &vf->rcv_act;
1135 
1136     spin_lock(&t_list->lock);
1137 
1138     __qlcnic_sriov_add_act_list(sriov, vf, trans);
1139 
1140     spin_unlock(&t_list->lock);
1141     return 0;
1142 }
1143 
1144 static void qlcnic_sriov_handle_pending_trans(struct qlcnic_sriov *sriov,
1145                           struct qlcnic_vf_info *vf,
1146                           struct qlcnic_bc_hdr *hdr)
1147 {
1148     struct qlcnic_bc_trans *trans = NULL;
1149     struct list_head *node;
1150     u32 pay_size, curr_frag;
1151     u8 found = 0, active = 0;
1152 
1153     spin_lock(&vf->rcv_pend.lock);
1154     if (vf->rcv_pend.count > 0) {
1155         list_for_each(node, &vf->rcv_pend.wait_list) {
1156             trans = list_entry(node, struct qlcnic_bc_trans, list);
1157             if (trans->trans_id == hdr->seq_id) {
1158                 found = 1;
1159                 break;
1160             }
1161         }
1162     }
1163 
1164     if (found) {
1165         curr_frag = trans->curr_req_frag;
1166         pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
1167                                curr_frag);
1168         qlcnic_sriov_pull_bc_msg(vf->adapter,
1169                      (u32 *)(trans->req_hdr + curr_frag),
1170                      (u32 *)(trans->req_pay + curr_frag),
1171                      pay_size);
1172         trans->curr_req_frag++;
1173         if (trans->curr_req_frag >= hdr->num_frags) {
1174             vf->rcv_pend.count--;
1175             list_del(&trans->list);
1176             active = 1;
1177         }
1178     }
1179     spin_unlock(&vf->rcv_pend.lock);
1180 
1181     if (active)
1182         if (qlcnic_sriov_add_act_list(sriov, vf, trans))
1183             qlcnic_sriov_cleanup_transaction(trans);
1184 
1185     return;
1186 }
1187 
1188 static void qlcnic_sriov_handle_bc_cmd(struct qlcnic_sriov *sriov,
1189                        struct qlcnic_bc_hdr *hdr,
1190                        struct qlcnic_vf_info *vf)
1191 {
1192     struct qlcnic_bc_trans *trans;
1193     struct qlcnic_adapter *adapter = vf->adapter;
1194     struct qlcnic_cmd_args cmd;
1195     u32 pay_size;
1196     int err;
1197     u8 cmd_op;
1198 
1199     if (adapter->need_fw_reset)
1200         return;
1201 
1202     if (!test_bit(QLC_BC_VF_STATE, &vf->state) &&
1203         hdr->op_type != QLC_BC_CMD &&
1204         hdr->cmd_op != QLCNIC_BC_CMD_CHANNEL_INIT)
1205         return;
1206 
1207     if (hdr->frag_num > 1) {
1208         qlcnic_sriov_handle_pending_trans(sriov, vf, hdr);
1209         return;
1210     }
1211 
1212     memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
1213     cmd_op = hdr->cmd_op;
1214     if (qlcnic_sriov_alloc_bc_trans(&trans))
1215         return;
1216 
1217     if (hdr->op_type == QLC_BC_CMD)
1218         err = qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op);
1219     else
1220         err = qlcnic_alloc_mbx_args(&cmd, adapter, cmd_op);
1221 
1222     if (err) {
1223         qlcnic_sriov_cleanup_transaction(trans);
1224         return;
1225     }
1226 
1227     cmd.op_type = hdr->op_type;
1228     if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, hdr->seq_id,
1229                     QLC_BC_COMMAND)) {
1230         qlcnic_free_mbx_args(&cmd);
1231         qlcnic_sriov_cleanup_transaction(trans);
1232         return;
1233     }
1234 
1235     pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
1236                      trans->curr_req_frag);
1237     qlcnic_sriov_pull_bc_msg(vf->adapter,
1238                  (u32 *)(trans->req_hdr + trans->curr_req_frag),
1239                  (u32 *)(trans->req_pay + trans->curr_req_frag),
1240                  pay_size);
1241     trans->func_id = vf->pci_func;
1242     trans->vf = vf;
1243     trans->trans_id = hdr->seq_id;
1244     trans->curr_req_frag++;
1245 
1246     if (qlcnic_sriov_soft_flr_check(adapter, trans, vf))
1247         return;
1248 
1249     if (trans->curr_req_frag == trans->req_hdr->num_frags) {
1250         if (qlcnic_sriov_add_act_list(sriov, vf, trans)) {
1251             qlcnic_free_mbx_args(&cmd);
1252             qlcnic_sriov_cleanup_transaction(trans);
1253         }
1254     } else {
1255         spin_lock(&vf->rcv_pend.lock);
1256         list_add_tail(&trans->list, &vf->rcv_pend.wait_list);
1257         vf->rcv_pend.count++;
1258         spin_unlock(&vf->rcv_pend.lock);
1259     }
1260 }
1261 
1262 static void qlcnic_sriov_handle_msg_event(struct qlcnic_sriov *sriov,
1263                       struct qlcnic_vf_info *vf)
1264 {
1265     struct qlcnic_bc_hdr hdr;
1266     u32 *ptr = (u32 *)&hdr;
1267     u8 msg_type, i;
1268 
1269     for (i = 2; i < 6; i++)
1270         ptr[i - 2] = readl(QLCNIC_MBX_FW(vf->adapter->ahw, i));
1271     msg_type = hdr.msg_type;
1272 
1273     switch (msg_type) {
1274     case QLC_BC_COMMAND:
1275         qlcnic_sriov_handle_bc_cmd(sriov, &hdr, vf);
1276         break;
1277     case QLC_BC_RESPONSE:
1278         qlcnic_sriov_handle_bc_resp(&hdr, vf);
1279         break;
1280     }
1281 }
1282 
1283 static void qlcnic_sriov_handle_flr_event(struct qlcnic_sriov *sriov,
1284                       struct qlcnic_vf_info *vf)
1285 {
1286     struct qlcnic_adapter *adapter = vf->adapter;
1287 
1288     if (qlcnic_sriov_pf_check(adapter))
1289         qlcnic_sriov_pf_handle_flr(sriov, vf);
1290     else
1291         dev_err(&adapter->pdev->dev,
1292             "Invalid event to VF. VF should not get FLR event\n");
1293 }
1294 
1295 void qlcnic_sriov_handle_bc_event(struct qlcnic_adapter *adapter, u32 event)
1296 {
1297     struct qlcnic_vf_info *vf;
1298     struct qlcnic_sriov *sriov;
1299     int index;
1300     u8 pci_func;
1301 
1302     sriov = adapter->ahw->sriov;
1303     pci_func = qlcnic_sriov_target_func_id(event);
1304     index = qlcnic_sriov_func_to_index(adapter, pci_func);
1305 
1306     if (index < 0)
1307         return;
1308 
1309     vf = &sriov->vf_info[index];
1310     vf->pci_func = pci_func;
1311 
1312     if (qlcnic_sriov_channel_free_check(event))
1313         complete(&vf->ch_free_cmpl);
1314 
1315     if (qlcnic_sriov_flr_check(event)) {
1316         qlcnic_sriov_handle_flr_event(sriov, vf);
1317         return;
1318     }
1319 
1320     if (qlcnic_sriov_bc_msg_check(event))
1321         qlcnic_sriov_handle_msg_event(sriov, vf);
1322 }
1323 
1324 int qlcnic_sriov_cfg_bc_intr(struct qlcnic_adapter *adapter, u8 enable)
1325 {
1326     struct qlcnic_cmd_args cmd;
1327     int err;
1328 
1329     if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state))
1330         return 0;
1331 
1332     if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_BC_EVENT_SETUP))
1333         return -ENOMEM;
1334 
1335     if (enable)
1336         cmd.req.arg[1] = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7);
1337 
1338     err = qlcnic_83xx_issue_cmd(adapter, &cmd);
1339 
1340     if (err != QLCNIC_RCODE_SUCCESS) {
1341         dev_err(&adapter->pdev->dev,
1342             "Failed to %s bc events, err=%d\n",
1343             (enable ? "enable" : "disable"), err);
1344     }
1345 
1346     qlcnic_free_mbx_args(&cmd);
1347     return err;
1348 }
1349 
1350 static int qlcnic_sriov_retry_bc_cmd(struct qlcnic_adapter *adapter,
1351                      struct qlcnic_bc_trans *trans)
1352 {
1353     u8 max = QLC_BC_CMD_MAX_RETRY_CNT;
1354     u32 state;
1355 
1356     state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1357     if (state == QLC_83XX_IDC_DEV_READY) {
1358         msleep(20);
1359         clear_bit(QLC_BC_VF_CHANNEL, &trans->vf->state);
1360         trans->trans_state = QLC_INIT;
1361         if (++adapter->fw_fail_cnt > max)
1362             return -EIO;
1363         else
1364             return 0;
1365     }
1366 
1367     return -EIO;
1368 }
1369 
1370 static int __qlcnic_sriov_issue_cmd(struct qlcnic_adapter *adapter,
1371                   struct qlcnic_cmd_args *cmd)
1372 {
1373     struct qlcnic_hardware_context *ahw = adapter->ahw;
1374     struct qlcnic_mailbox *mbx = ahw->mailbox;
1375     struct device *dev = &adapter->pdev->dev;
1376     struct qlcnic_bc_trans *trans;
1377     int err;
1378     u32 rsp_data, opcode, mbx_err_code, rsp;
1379     u16 seq = ++adapter->ahw->sriov->bc.trans_counter;
1380     u8 func = ahw->pci_func;
1381 
1382     rsp = qlcnic_sriov_alloc_bc_trans(&trans);
1383     if (rsp)
1384         goto free_cmd;
1385 
1386     rsp = qlcnic_sriov_prepare_bc_hdr(trans, cmd, seq, QLC_BC_COMMAND);
1387     if (rsp)
1388         goto cleanup_transaction;
1389 
1390 retry:
1391     if (!test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
1392         rsp = -EIO;
1393         QLCDB(adapter, DRV, "MBX not Ready!(cmd 0x%x) for VF 0x%x\n",
1394               QLCNIC_MBX_RSP(cmd->req.arg[0]), func);
1395         goto err_out;
1396     }
1397 
1398     err = qlcnic_sriov_send_bc_cmd(adapter, trans, func);
1399     if (err) {
1400         dev_err(dev, "MBX command 0x%x timed out for VF %d\n",
1401             (cmd->req.arg[0] & 0xffff), func);
1402         rsp = QLCNIC_RCODE_TIMEOUT;
1403 
1404         /* After adapter reset PF driver may take some time to
1405          * respond to VF's request. Retry request till maximum retries.
1406          */
1407         if ((trans->req_hdr->cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT) &&
1408             !qlcnic_sriov_retry_bc_cmd(adapter, trans))
1409             goto retry;
1410 
1411         goto err_out;
1412     }
1413 
1414     rsp_data = cmd->rsp.arg[0];
1415     mbx_err_code = QLCNIC_MBX_STATUS(rsp_data);
1416     opcode = QLCNIC_MBX_RSP(cmd->req.arg[0]);
1417 
1418     if ((mbx_err_code == QLCNIC_MBX_RSP_OK) ||
1419         (mbx_err_code == QLCNIC_MBX_PORT_RSP_OK)) {
1420         rsp = QLCNIC_RCODE_SUCCESS;
1421     } else {
1422         if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
1423             rsp = QLCNIC_RCODE_SUCCESS;
1424         } else {
1425             rsp = mbx_err_code;
1426             if (!rsp)
1427                 rsp = 1;
1428 
1429             dev_err(dev,
1430                 "MBX command 0x%x failed with err:0x%x for VF %d\n",
1431                 opcode, mbx_err_code, func);
1432         }
1433     }
1434 
1435 err_out:
1436     if (rsp == QLCNIC_RCODE_TIMEOUT) {
1437         ahw->reset_context = 1;
1438         adapter->need_fw_reset = 1;
1439         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1440     }
1441 
1442 cleanup_transaction:
1443     qlcnic_sriov_cleanup_transaction(trans);
1444 
1445 free_cmd:
1446     if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
1447         qlcnic_free_mbx_args(cmd);
1448         kfree(cmd);
1449     }
1450 
1451     return rsp;
1452 }
1453 
1454 
1455 static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter *adapter,
1456                   struct qlcnic_cmd_args *cmd)
1457 {
1458     if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT)
1459         return qlcnic_sriov_async_issue_cmd(adapter, cmd);
1460     else
1461         return __qlcnic_sriov_issue_cmd(adapter, cmd);
1462 }
1463 
1464 static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *adapter, u8 cmd_op)
1465 {
1466     struct qlcnic_cmd_args cmd;
1467     struct qlcnic_vf_info *vf = &adapter->ahw->sriov->vf_info[0];
1468     int ret;
1469 
1470     memset(&cmd, 0, sizeof(cmd));
1471     if (qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op))
1472         return -ENOMEM;
1473 
1474     ret = qlcnic_issue_cmd(adapter, &cmd);
1475     if (ret) {
1476         dev_err(&adapter->pdev->dev,
1477             "Failed bc channel %s %d\n", cmd_op ? "term" : "init",
1478             ret);
1479         goto out;
1480     }
1481 
1482     cmd_op = (cmd.rsp.arg[0] & 0xff);
1483     if (cmd.rsp.arg[0] >> 25 == 2)
1484         return 2;
1485     if (cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT)
1486         set_bit(QLC_BC_VF_STATE, &vf->state);
1487     else
1488         clear_bit(QLC_BC_VF_STATE, &vf->state);
1489 
1490 out:
1491     qlcnic_free_mbx_args(&cmd);
1492     return ret;
1493 }
1494 
1495 static void qlcnic_vf_add_mc_list(struct net_device *netdev, const u8 *mac,
1496                   enum qlcnic_mac_type mac_type)
1497 {
1498     struct qlcnic_adapter *adapter = netdev_priv(netdev);
1499     struct qlcnic_sriov *sriov = adapter->ahw->sriov;
1500     struct qlcnic_vf_info *vf;
1501     u16 vlan_id;
1502     int i;
1503 
1504     vf = &adapter->ahw->sriov->vf_info[0];
1505 
1506     if (!qlcnic_sriov_check_any_vlan(vf)) {
1507         qlcnic_nic_add_mac(adapter, mac, 0, mac_type);
1508     } else {
1509         spin_lock(&vf->vlan_list_lock);
1510         for (i = 0; i < sriov->num_allowed_vlans; i++) {
1511             vlan_id = vf->sriov_vlans[i];
1512             if (vlan_id)
1513                 qlcnic_nic_add_mac(adapter, mac, vlan_id,
1514                            mac_type);
1515         }
1516         spin_unlock(&vf->vlan_list_lock);
1517         if (qlcnic_84xx_check(adapter))
1518             qlcnic_nic_add_mac(adapter, mac, 0, mac_type);
1519     }
1520 }
1521 
1522 void qlcnic_sriov_cleanup_async_list(struct qlcnic_back_channel *bc)
1523 {
1524     struct list_head *head = &bc->async_cmd_list;
1525     struct qlcnic_async_cmd *entry;
1526 
1527     flush_workqueue(bc->bc_async_wq);
1528     cancel_work_sync(&bc->vf_async_work);
1529 
1530     spin_lock(&bc->queue_lock);
1531     while (!list_empty(head)) {
1532         entry = list_entry(head->next, struct qlcnic_async_cmd,
1533                    list);
1534         list_del(&entry->list);
1535         kfree(entry->cmd);
1536         kfree(entry);
1537     }
1538     spin_unlock(&bc->queue_lock);
1539 }
1540 
1541 void qlcnic_sriov_vf_set_multi(struct net_device *netdev)
1542 {
1543     struct qlcnic_adapter *adapter = netdev_priv(netdev);
1544     struct qlcnic_hardware_context *ahw = adapter->ahw;
1545     static const u8 bcast_addr[ETH_ALEN] = {
1546         0xff, 0xff, 0xff, 0xff, 0xff, 0xff
1547     };
1548     struct netdev_hw_addr *ha;
1549     u32 mode = VPORT_MISS_MODE_DROP;
1550 
1551     if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
1552         return;
1553 
1554     if (netdev->flags & IFF_PROMISC) {
1555         if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
1556             mode = VPORT_MISS_MODE_ACCEPT_ALL;
1557     } else if ((netdev->flags & IFF_ALLMULTI) ||
1558            (netdev_mc_count(netdev) > ahw->max_mc_count)) {
1559         mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1560     } else {
1561         qlcnic_vf_add_mc_list(netdev, bcast_addr, QLCNIC_BROADCAST_MAC);
1562         if (!netdev_mc_empty(netdev)) {
1563             qlcnic_flush_mcast_mac(adapter);
1564             netdev_for_each_mc_addr(ha, netdev)
1565                 qlcnic_vf_add_mc_list(netdev, ha->addr,
1566                               QLCNIC_MULTICAST_MAC);
1567         }
1568     }
1569 
1570     /* configure unicast MAC address, if there is not sufficient space
1571      * to store all the unicast addresses then enable promiscuous mode
1572      */
1573     if (netdev_uc_count(netdev) > ahw->max_uc_count) {
1574         mode = VPORT_MISS_MODE_ACCEPT_ALL;
1575     } else if (!netdev_uc_empty(netdev)) {
1576         netdev_for_each_uc_addr(ha, netdev)
1577             qlcnic_vf_add_mc_list(netdev, ha->addr,
1578                           QLCNIC_UNICAST_MAC);
1579     }
1580 
1581     if (adapter->pdev->is_virtfn) {
1582         if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
1583             !adapter->fdb_mac_learn) {
1584             qlcnic_alloc_lb_filters_mem(adapter);
1585             adapter->drv_mac_learn = true;
1586             adapter->rx_mac_learn = true;
1587         } else {
1588             adapter->drv_mac_learn = false;
1589             adapter->rx_mac_learn = false;
1590         }
1591     }
1592 
1593     qlcnic_nic_set_promisc(adapter, mode);
1594 }
1595 
1596 static void qlcnic_sriov_handle_async_issue_cmd(struct work_struct *work)
1597 {
1598     struct qlcnic_async_cmd *entry, *tmp;
1599     struct qlcnic_back_channel *bc;
1600     struct qlcnic_cmd_args *cmd;
1601     struct list_head *head;
1602     LIST_HEAD(del_list);
1603 
1604     bc = container_of(work, struct qlcnic_back_channel, vf_async_work);
1605     head = &bc->async_cmd_list;
1606 
1607     spin_lock(&bc->queue_lock);
1608     list_splice_init(head, &del_list);
1609     spin_unlock(&bc->queue_lock);
1610 
1611     list_for_each_entry_safe(entry, tmp, &del_list, list) {
1612         list_del(&entry->list);
1613         cmd = entry->cmd;
1614         __qlcnic_sriov_issue_cmd(bc->adapter, cmd);
1615         kfree(entry);
1616     }
1617 
1618     if (!list_empty(head))
1619         queue_work(bc->bc_async_wq, &bc->vf_async_work);
1620 
1621     return;
1622 }
1623 
1624 static struct qlcnic_async_cmd *
1625 qlcnic_sriov_alloc_async_cmd(struct qlcnic_back_channel *bc,
1626                  struct qlcnic_cmd_args *cmd)
1627 {
1628     struct qlcnic_async_cmd *entry = NULL;
1629 
1630     entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
1631     if (!entry)
1632         return NULL;
1633 
1634     entry->cmd = cmd;
1635 
1636     spin_lock(&bc->queue_lock);
1637     list_add_tail(&entry->list, &bc->async_cmd_list);
1638     spin_unlock(&bc->queue_lock);
1639 
1640     return entry;
1641 }
1642 
1643 static void qlcnic_sriov_schedule_async_cmd(struct qlcnic_back_channel *bc,
1644                         struct qlcnic_cmd_args *cmd)
1645 {
1646     struct qlcnic_async_cmd *entry = NULL;
1647 
1648     entry = qlcnic_sriov_alloc_async_cmd(bc, cmd);
1649     if (!entry) {
1650         qlcnic_free_mbx_args(cmd);
1651         kfree(cmd);
1652         return;
1653     }
1654 
1655     queue_work(bc->bc_async_wq, &bc->vf_async_work);
1656 }
1657 
1658 static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter *adapter,
1659                     struct qlcnic_cmd_args *cmd)
1660 {
1661 
1662     struct qlcnic_back_channel *bc = &adapter->ahw->sriov->bc;
1663 
1664     if (adapter->need_fw_reset)
1665         return -EIO;
1666 
1667     qlcnic_sriov_schedule_async_cmd(bc, cmd);
1668 
1669     return 0;
1670 }
1671 
1672 static int qlcnic_sriov_vf_reinit_driver(struct qlcnic_adapter *adapter)
1673 {
1674     int err;
1675 
1676     adapter->need_fw_reset = 0;
1677     qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
1678     qlcnic_83xx_enable_mbx_interrupt(adapter);
1679 
1680     err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
1681     if (err)
1682         return err;
1683 
1684     err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
1685     if (err)
1686         goto err_out_cleanup_bc_intr;
1687 
1688     err = qlcnic_sriov_vf_init_driver(adapter);
1689     if (err)
1690         goto err_out_term_channel;
1691 
1692     return 0;
1693 
1694 err_out_term_channel:
1695     qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
1696 
1697 err_out_cleanup_bc_intr:
1698     qlcnic_sriov_cfg_bc_intr(adapter, 0);
1699     return err;
1700 }
1701 
1702 static void qlcnic_sriov_vf_attach(struct qlcnic_adapter *adapter)
1703 {
1704     struct net_device *netdev = adapter->netdev;
1705 
1706     if (netif_running(netdev)) {
1707         if (!qlcnic_up(adapter, netdev))
1708             qlcnic_restore_indev_addr(netdev, NETDEV_UP);
1709     }
1710 
1711     netif_device_attach(netdev);
1712 }
1713 
1714 static void qlcnic_sriov_vf_detach(struct qlcnic_adapter *adapter)
1715 {
1716     struct qlcnic_hardware_context *ahw = adapter->ahw;
1717     struct qlcnic_intrpt_config *intr_tbl = ahw->intr_tbl;
1718     struct net_device *netdev = adapter->netdev;
1719     u8 i, max_ints = ahw->num_msix - 1;
1720 
1721     netif_device_detach(netdev);
1722     qlcnic_83xx_detach_mailbox_work(adapter);
1723     qlcnic_83xx_disable_mbx_intr(adapter);
1724 
1725     if (netif_running(netdev))
1726         qlcnic_down(adapter, netdev);
1727 
1728     for (i = 0; i < max_ints; i++) {
1729         intr_tbl[i].id = i;
1730         intr_tbl[i].enabled = 0;
1731         intr_tbl[i].src = 0;
1732     }
1733     ahw->reset_context = 0;
1734 }
1735 
1736 static int qlcnic_sriov_vf_handle_dev_ready(struct qlcnic_adapter *adapter)
1737 {
1738     struct qlcnic_hardware_context *ahw = adapter->ahw;
1739     struct device *dev = &adapter->pdev->dev;
1740     struct qlc_83xx_idc *idc = &ahw->idc;
1741     u8 func = ahw->pci_func;
1742     u32 state;
1743 
1744     if ((idc->prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
1745         (idc->prev_state == QLC_83XX_IDC_DEV_INIT)) {
1746         if (!qlcnic_sriov_vf_reinit_driver(adapter)) {
1747             qlcnic_sriov_vf_attach(adapter);
1748             adapter->fw_fail_cnt = 0;
1749             dev_info(dev,
1750                  "%s: Reinitialization of VF 0x%x done after FW reset\n",
1751                  __func__, func);
1752         } else {
1753             dev_err(dev,
1754                 "%s: Reinitialization of VF 0x%x failed after FW reset\n",
1755                 __func__, func);
1756             state = QLCRDX(ahw, QLC_83XX_IDC_DEV_STATE);
1757             dev_info(dev, "Current state 0x%x after FW reset\n",
1758                  state);
1759         }
1760     }
1761 
1762     return 0;
1763 }
1764 
1765 static int qlcnic_sriov_vf_handle_context_reset(struct qlcnic_adapter *adapter)
1766 {
1767     struct qlcnic_hardware_context *ahw = adapter->ahw;
1768     struct qlcnic_mailbox *mbx = ahw->mailbox;
1769     struct device *dev = &adapter->pdev->dev;
1770     struct qlc_83xx_idc *idc = &ahw->idc;
1771     u8 func = ahw->pci_func;
1772     u32 state;
1773 
1774     adapter->reset_ctx_cnt++;
1775 
1776     /* Skip the context reset and check if FW is hung */
1777     if (adapter->reset_ctx_cnt < 3) {
1778         adapter->need_fw_reset = 1;
1779         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1780         dev_info(dev,
1781              "Resetting context, wait here to check if FW is in failed state\n");
1782         return 0;
1783     }
1784 
1785     /* Check if number of resets exceed the threshold.
1786      * If it exceeds the threshold just fail the VF.
1787      */
1788     if (adapter->reset_ctx_cnt > QLC_83XX_VF_RESET_FAIL_THRESH) {
1789         clear_bit(QLC_83XX_MODULE_LOADED, &idc->status);
1790         adapter->tx_timeo_cnt = 0;
1791         adapter->fw_fail_cnt = 0;
1792         adapter->reset_ctx_cnt = 0;
1793         qlcnic_sriov_vf_detach(adapter);
1794         dev_err(dev,
1795             "Device context resets have exceeded the threshold, device interface will be shutdown\n");
1796         return -EIO;
1797     }
1798 
1799     dev_info(dev, "Resetting context of VF 0x%x\n", func);
1800     dev_info(dev, "%s: Context reset count %d for VF 0x%x\n",
1801          __func__, adapter->reset_ctx_cnt, func);
1802     set_bit(__QLCNIC_RESETTING, &adapter->state);
1803     adapter->need_fw_reset = 1;
1804     clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1805     qlcnic_sriov_vf_detach(adapter);
1806     adapter->need_fw_reset = 0;
1807 
1808     if (!qlcnic_sriov_vf_reinit_driver(adapter)) {
1809         qlcnic_sriov_vf_attach(adapter);
1810         adapter->tx_timeo_cnt = 0;
1811         adapter->reset_ctx_cnt = 0;
1812         adapter->fw_fail_cnt = 0;
1813         dev_info(dev, "Done resetting context for VF 0x%x\n", func);
1814     } else {
1815         dev_err(dev, "%s: Reinitialization of VF 0x%x failed\n",
1816             __func__, func);
1817         state = QLCRDX(ahw, QLC_83XX_IDC_DEV_STATE);
1818         dev_info(dev, "%s: Current state 0x%x\n", __func__, state);
1819     }
1820 
1821     return 0;
1822 }
1823 
1824 static int qlcnic_sriov_vf_idc_ready_state(struct qlcnic_adapter *adapter)
1825 {
1826     struct qlcnic_hardware_context *ahw = adapter->ahw;
1827     int ret = 0;
1828 
1829     if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY)
1830         ret = qlcnic_sriov_vf_handle_dev_ready(adapter);
1831     else if (ahw->reset_context)
1832         ret = qlcnic_sriov_vf_handle_context_reset(adapter);
1833 
1834     clear_bit(__QLCNIC_RESETTING, &adapter->state);
1835     return ret;
1836 }
1837 
1838 static int qlcnic_sriov_vf_idc_failed_state(struct qlcnic_adapter *adapter)
1839 {
1840     struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1841 
1842     dev_err(&adapter->pdev->dev, "Device is in failed state\n");
1843     if (idc->prev_state == QLC_83XX_IDC_DEV_READY)
1844         qlcnic_sriov_vf_detach(adapter);
1845 
1846     clear_bit(QLC_83XX_MODULE_LOADED, &idc->status);
1847     clear_bit(__QLCNIC_RESETTING, &adapter->state);
1848     return -EIO;
1849 }
1850 
1851 static int
1852 qlcnic_sriov_vf_idc_need_quiescent_state(struct qlcnic_adapter *adapter)
1853 {
1854     struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
1855     struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1856 
1857     dev_info(&adapter->pdev->dev, "Device is in quiescent state\n");
1858     if (idc->prev_state == QLC_83XX_IDC_DEV_READY) {
1859         set_bit(__QLCNIC_RESETTING, &adapter->state);
1860         adapter->tx_timeo_cnt = 0;
1861         adapter->reset_ctx_cnt = 0;
1862         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1863         qlcnic_sriov_vf_detach(adapter);
1864     }
1865 
1866     return 0;
1867 }
1868 
1869 static int qlcnic_sriov_vf_idc_init_reset_state(struct qlcnic_adapter *adapter)
1870 {
1871     struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
1872     struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1873     u8 func = adapter->ahw->pci_func;
1874 
1875     if (idc->prev_state == QLC_83XX_IDC_DEV_READY) {
1876         dev_err(&adapter->pdev->dev,
1877             "Firmware hang detected by VF 0x%x\n", func);
1878         set_bit(__QLCNIC_RESETTING, &adapter->state);
1879         adapter->tx_timeo_cnt = 0;
1880         adapter->reset_ctx_cnt = 0;
1881         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1882         qlcnic_sriov_vf_detach(adapter);
1883     }
1884     return 0;
1885 }
1886 
1887 static int qlcnic_sriov_vf_idc_unknown_state(struct qlcnic_adapter *adapter)
1888 {
1889     dev_err(&adapter->pdev->dev, "%s: Device in unknown state\n", __func__);
1890     return 0;
1891 }
1892 
1893 static void qlcnic_sriov_vf_periodic_tasks(struct qlcnic_adapter *adapter)
1894 {
1895     if (adapter->fhash.fnum)
1896         qlcnic_prune_lb_filters(adapter);
1897 }
1898 
1899 static void qlcnic_sriov_vf_poll_dev_state(struct work_struct *work)
1900 {
1901     struct qlcnic_adapter *adapter;
1902     struct qlc_83xx_idc *idc;
1903     int ret = 0;
1904 
1905     adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1906     idc = &adapter->ahw->idc;
1907     idc->curr_state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1908 
1909     switch (idc->curr_state) {
1910     case QLC_83XX_IDC_DEV_READY:
1911         ret = qlcnic_sriov_vf_idc_ready_state(adapter);
1912         break;
1913     case QLC_83XX_IDC_DEV_NEED_RESET:
1914     case QLC_83XX_IDC_DEV_INIT:
1915         ret = qlcnic_sriov_vf_idc_init_reset_state(adapter);
1916         break;
1917     case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1918         ret = qlcnic_sriov_vf_idc_need_quiescent_state(adapter);
1919         break;
1920     case QLC_83XX_IDC_DEV_FAILED:
1921         ret = qlcnic_sriov_vf_idc_failed_state(adapter);
1922         break;
1923     case QLC_83XX_IDC_DEV_QUISCENT:
1924         break;
1925     default:
1926         ret = qlcnic_sriov_vf_idc_unknown_state(adapter);
1927     }
1928 
1929     idc->prev_state = idc->curr_state;
1930     qlcnic_sriov_vf_periodic_tasks(adapter);
1931 
1932     if (!ret && test_bit(QLC_83XX_MODULE_LOADED, &idc->status))
1933         qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
1934                      idc->delay);
1935 }
1936 
1937 static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter *adapter)
1938 {
1939     while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1940         msleep(20);
1941 
1942     clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1943     clear_bit(__QLCNIC_RESETTING, &adapter->state);
1944     cancel_delayed_work_sync(&adapter->fw_work);
1945 }
1946 
1947 static int qlcnic_sriov_check_vlan_id(struct qlcnic_sriov *sriov,
1948                       struct qlcnic_vf_info *vf, u16 vlan_id)
1949 {
1950     int i, err = -EINVAL;
1951 
1952     if (!vf->sriov_vlans)
1953         return err;
1954 
1955     spin_lock_bh(&vf->vlan_list_lock);
1956 
1957     for (i = 0; i < sriov->num_allowed_vlans; i++) {
1958         if (vf->sriov_vlans[i] == vlan_id) {
1959             err = 0;
1960             break;
1961         }
1962     }
1963 
1964     spin_unlock_bh(&vf->vlan_list_lock);
1965     return err;
1966 }
1967 
1968 static int qlcnic_sriov_validate_num_vlans(struct qlcnic_sriov *sriov,
1969                        struct qlcnic_vf_info *vf)
1970 {
1971     int err = 0;
1972 
1973     spin_lock_bh(&vf->vlan_list_lock);
1974 
1975     if (vf->num_vlan >= sriov->num_allowed_vlans)
1976         err = -EINVAL;
1977 
1978     spin_unlock_bh(&vf->vlan_list_lock);
1979     return err;
1980 }
1981 
1982 static int qlcnic_sriov_validate_vlan_cfg(struct qlcnic_adapter *adapter,
1983                       u16 vid, u8 enable)
1984 {
1985     struct qlcnic_sriov *sriov = adapter->ahw->sriov;
1986     struct qlcnic_vf_info *vf;
1987     bool vlan_exist;
1988     u8 allowed = 0;
1989     int i;
1990 
1991     vf = &adapter->ahw->sriov->vf_info[0];
1992     vlan_exist = qlcnic_sriov_check_any_vlan(vf);
1993     if (sriov->vlan_mode != QLC_GUEST_VLAN_MODE)
1994         return -EINVAL;
1995 
1996     if (enable) {
1997         if (qlcnic_83xx_vf_check(adapter) && vlan_exist)
1998             return -EINVAL;
1999 
2000         if (qlcnic_sriov_validate_num_vlans(sriov, vf))
2001             return -EINVAL;
2002 
2003         if (sriov->any_vlan) {
2004             for (i = 0; i < sriov->num_allowed_vlans; i++) {
2005                 if (sriov->allowed_vlans[i] == vid)
2006                     allowed = 1;
2007             }
2008 
2009             if (!allowed)
2010                 return -EINVAL;
2011         }
2012     } else {
2013         if (!vlan_exist || qlcnic_sriov_check_vlan_id(sriov, vf, vid))
2014             return -EINVAL;
2015     }
2016 
2017     return 0;
2018 }
2019 
2020 static void qlcnic_sriov_vlan_operation(struct qlcnic_vf_info *vf, u16 vlan_id,
2021                     enum qlcnic_vlan_operations opcode)
2022 {
2023     struct qlcnic_adapter *adapter = vf->adapter;
2024     struct qlcnic_sriov *sriov;
2025 
2026     sriov = adapter->ahw->sriov;
2027 
2028     if (!vf->sriov_vlans)
2029         return;
2030 
2031     spin_lock_bh(&vf->vlan_list_lock);
2032 
2033     switch (opcode) {
2034     case QLC_VLAN_ADD:
2035         qlcnic_sriov_add_vlan_id(sriov, vf, vlan_id);
2036         break;
2037     case QLC_VLAN_DELETE:
2038         qlcnic_sriov_del_vlan_id(sriov, vf, vlan_id);
2039         break;
2040     default:
2041         netdev_err(adapter->netdev, "Invalid VLAN operation\n");
2042     }
2043 
2044     spin_unlock_bh(&vf->vlan_list_lock);
2045     return;
2046 }
2047 
2048 int qlcnic_sriov_cfg_vf_guest_vlan(struct qlcnic_adapter *adapter,
2049                    u16 vid, u8 enable)
2050 {
2051     struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2052     struct net_device *netdev = adapter->netdev;
2053     struct qlcnic_vf_info *vf;
2054     struct qlcnic_cmd_args cmd;
2055     int ret;
2056 
2057     memset(&cmd, 0, sizeof(cmd));
2058     if (vid == 0)
2059         return 0;
2060 
2061     vf = &adapter->ahw->sriov->vf_info[0];
2062     ret = qlcnic_sriov_validate_vlan_cfg(adapter, vid, enable);
2063     if (ret)
2064         return ret;
2065 
2066     ret = qlcnic_sriov_alloc_bc_mbx_args(&cmd,
2067                          QLCNIC_BC_CMD_CFG_GUEST_VLAN);
2068     if (ret)
2069         return ret;
2070 
2071     cmd.req.arg[1] = (enable & 1) | vid << 16;
2072 
2073     qlcnic_sriov_cleanup_async_list(&sriov->bc);
2074     ret = qlcnic_issue_cmd(adapter, &cmd);
2075     if (ret) {
2076         dev_err(&adapter->pdev->dev,
2077             "Failed to configure guest VLAN, err=%d\n", ret);
2078     } else {
2079         netif_addr_lock_bh(netdev);
2080         qlcnic_free_mac_list(adapter);
2081         netif_addr_unlock_bh(netdev);
2082 
2083         if (enable)
2084             qlcnic_sriov_vlan_operation(vf, vid, QLC_VLAN_ADD);
2085         else
2086             qlcnic_sriov_vlan_operation(vf, vid, QLC_VLAN_DELETE);
2087 
2088         netif_addr_lock_bh(netdev);
2089         qlcnic_set_multi(netdev);
2090         netif_addr_unlock_bh(netdev);
2091     }
2092 
2093     qlcnic_free_mbx_args(&cmd);
2094     return ret;
2095 }
2096 
2097 static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter *adapter)
2098 {
2099     struct list_head *head = &adapter->mac_list;
2100     struct qlcnic_mac_vlan_list *cur;
2101 
2102     while (!list_empty(head)) {
2103         cur = list_entry(head->next, struct qlcnic_mac_vlan_list, list);
2104         qlcnic_sre_macaddr_change(adapter, cur->mac_addr, cur->vlan_id,
2105                       QLCNIC_MAC_DEL);
2106         list_del(&cur->list);
2107         kfree(cur);
2108     }
2109 }
2110 
2111 
2112 static int qlcnic_sriov_vf_shutdown(struct pci_dev *pdev)
2113 {
2114     struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
2115     struct net_device *netdev = adapter->netdev;
2116 
2117     netif_device_detach(netdev);
2118     qlcnic_cancel_idc_work(adapter);
2119 
2120     if (netif_running(netdev))
2121         qlcnic_down(adapter, netdev);
2122 
2123     qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
2124     qlcnic_sriov_cfg_bc_intr(adapter, 0);
2125     qlcnic_83xx_disable_mbx_intr(adapter);
2126     cancel_delayed_work_sync(&adapter->idc_aen_work);
2127 
2128     return pci_save_state(pdev);
2129 }
2130 
2131 static int qlcnic_sriov_vf_resume(struct qlcnic_adapter *adapter)
2132 {
2133     struct qlc_83xx_idc *idc = &adapter->ahw->idc;
2134     struct net_device *netdev = adapter->netdev;
2135     int err;
2136 
2137     set_bit(QLC_83XX_MODULE_LOADED, &idc->status);
2138     qlcnic_83xx_enable_mbx_interrupt(adapter);
2139     err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
2140     if (err)
2141         return err;
2142 
2143     err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
2144     if (!err) {
2145         if (netif_running(netdev)) {
2146             err = qlcnic_up(adapter, netdev);
2147             if (!err)
2148                 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
2149         }
2150     }
2151 
2152     netif_device_attach(netdev);
2153     qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
2154                  idc->delay);
2155     return err;
2156 }
2157 
2158 int qlcnic_sriov_alloc_vlans(struct qlcnic_adapter *adapter)
2159 {
2160     struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2161     struct qlcnic_vf_info *vf;
2162     int i;
2163 
2164     for (i = 0; i < sriov->num_vfs; i++) {
2165         vf = &sriov->vf_info[i];
2166         vf->sriov_vlans = kcalloc(sriov->num_allowed_vlans,
2167                       sizeof(*vf->sriov_vlans), GFP_KERNEL);
2168         if (!vf->sriov_vlans)
2169             return -ENOMEM;
2170     }
2171 
2172     return 0;
2173 }
2174 
2175 void qlcnic_sriov_free_vlans(struct qlcnic_adapter *adapter)
2176 {
2177     struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2178     struct qlcnic_vf_info *vf;
2179     int i;
2180 
2181     for (i = 0; i < sriov->num_vfs; i++) {
2182         vf = &sriov->vf_info[i];
2183         kfree(vf->sriov_vlans);
2184         vf->sriov_vlans = NULL;
2185     }
2186 }
2187 
2188 void qlcnic_sriov_add_vlan_id(struct qlcnic_sriov *sriov,
2189                   struct qlcnic_vf_info *vf, u16 vlan_id)
2190 {
2191     int i;
2192 
2193     for (i = 0; i < sriov->num_allowed_vlans; i++) {
2194         if (!vf->sriov_vlans[i]) {
2195             vf->sriov_vlans[i] = vlan_id;
2196             vf->num_vlan++;
2197             return;
2198         }
2199     }
2200 }
2201 
2202 void qlcnic_sriov_del_vlan_id(struct qlcnic_sriov *sriov,
2203                   struct qlcnic_vf_info *vf, u16 vlan_id)
2204 {
2205     int i;
2206 
2207     for (i = 0; i < sriov->num_allowed_vlans; i++) {
2208         if (vf->sriov_vlans[i] == vlan_id) {
2209             vf->sriov_vlans[i] = 0;
2210             vf->num_vlan--;
2211             return;
2212         }
2213     }
2214 }
2215 
2216 bool qlcnic_sriov_check_any_vlan(struct qlcnic_vf_info *vf)
2217 {
2218     bool err = false;
2219 
2220     spin_lock_bh(&vf->vlan_list_lock);
2221 
2222     if (vf->num_vlan)
2223         err = true;
2224 
2225     spin_unlock_bh(&vf->vlan_list_lock);
2226     return err;
2227 }
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