qlogic/qlcnic/qlcnic_hw.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * QLogic qlcnic NIC Driver
0004  * Copyright (c) 2009-2013 QLogic Corporation
0005  */
0006
0007 #ifndef __QLCNIC_HW_H
0008 #define __QLCNIC_HW_H
0009
0010 /* Common registers in 83xx and 82xx */
0011 enum qlcnic_regs {
0012     QLCNIC_PEG_HALT_STATUS1 = 0,
0013     QLCNIC_PEG_HALT_STATUS2,
0014     QLCNIC_PEG_ALIVE_COUNTER,
0015     QLCNIC_FLASH_LOCK_OWNER,
0016     QLCNIC_FW_CAPABILITIES,
0017     QLCNIC_CRB_DRV_ACTIVE,
0018     QLCNIC_CRB_DEV_STATE,
0019     QLCNIC_CRB_DRV_STATE,
0020     QLCNIC_CRB_DRV_SCRATCH,
0021     QLCNIC_CRB_DEV_PARTITION_INFO,
0022     QLCNIC_CRB_DRV_IDC_VER,
0023     QLCNIC_FW_VERSION_MAJOR,
0024     QLCNIC_FW_VERSION_MINOR,
0025     QLCNIC_FW_VERSION_SUB,
0026     QLCNIC_CRB_DEV_NPAR_STATE,
0027     QLCNIC_FW_IMG_VALID,
0028     QLCNIC_CMDPEG_STATE,
0029     QLCNIC_RCVPEG_STATE,
0030     QLCNIC_ASIC_TEMP,
0031     QLCNIC_FW_API,
0032     QLCNIC_DRV_OP_MODE,
0033     QLCNIC_FLASH_LOCK,
0034     QLCNIC_FLASH_UNLOCK,
0035 };
0036
0037 /* Read from an address offset from BAR0, existing registers */
0038 #define QLC_SHARED_REG_RD32(a, addr)            \
0039     readl(((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
0040
0041 /* Write to an address offset from BAR0, existing registers */
0042 #define QLC_SHARED_REG_WR32(a, addr, value)     \
0043     writel(value, ((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
0044
0045 /* Read from a direct address offset from BAR0, additional registers */
0046 #define QLCRDX(ahw, addr)   \
0047     readl(((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr]))
0048
0049 /* Write to a direct address offset from BAR0, additional registers */
0050 #define QLCWRX(ahw, addr, value)    \
0051     writel(value, (((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr])))
0052
0053 #define QLCNIC_CMD_CONFIGURE_IP_ADDR        0x1
0054 #define QLCNIC_CMD_CONFIG_INTRPT        0x2
0055 #define QLCNIC_CMD_CREATE_RX_CTX        0x7
0056 #define QLCNIC_CMD_DESTROY_RX_CTX       0x8
0057 #define QLCNIC_CMD_CREATE_TX_CTX        0x9
0058 #define QLCNIC_CMD_DESTROY_TX_CTX       0xa
0059 #define QLCNIC_CMD_CONFIGURE_LRO        0xC
0060 #define QLCNIC_CMD_CONFIGURE_MAC_LEARNING   0xD
0061 #define QLCNIC_CMD_GET_STATISTICS       0xF
0062 #define QLCNIC_CMD_INTRPT_TEST          0x11
0063 #define QLCNIC_CMD_SET_MTU          0x12
0064 #define QLCNIC_CMD_READ_PHY         0x13
0065 #define QLCNIC_CMD_WRITE_PHY            0x14
0066 #define QLCNIC_CMD_READ_HW_REG          0x15
0067 #define QLCNIC_CMD_GET_FLOW_CTL         0x16
0068 #define QLCNIC_CMD_SET_FLOW_CTL         0x17
0069 #define QLCNIC_CMD_READ_MAX_MTU         0x18
0070 #define QLCNIC_CMD_READ_MAX_LRO         0x19
0071 #define QLCNIC_CMD_MAC_ADDRESS          0x1f
0072 #define QLCNIC_CMD_GET_PCI_INFO         0x20
0073 #define QLCNIC_CMD_GET_NIC_INFO         0x21
0074 #define QLCNIC_CMD_SET_NIC_INFO         0x22
0075 #define QLCNIC_CMD_GET_ESWITCH_CAPABILITY   0x24
0076 #define QLCNIC_CMD_TOGGLE_ESWITCH       0x25
0077 #define QLCNIC_CMD_GET_ESWITCH_STATUS       0x26
0078 #define QLCNIC_CMD_SET_PORTMIRRORING        0x27
0079 #define QLCNIC_CMD_CONFIGURE_ESWITCH        0x28
0080 #define QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG  0x29
0081 #define QLCNIC_CMD_GET_ESWITCH_STATS        0x2a
0082 #define QLCNIC_CMD_CONFIG_PORT          0x2e
0083 #define QLCNIC_CMD_TEMP_SIZE            0x2f
0084 #define QLCNIC_CMD_GET_TEMP_HDR         0x30
0085 #define QLCNIC_CMD_BC_EVENT_SETUP       0x31
0086 #define QLCNIC_CMD_CONFIG_VPORT         0x32
0087 #define QLCNIC_CMD_DCB_QUERY_CAP        0x34
0088 #define QLCNIC_CMD_DCB_QUERY_PARAM      0x35
0089 #define QLCNIC_CMD_GET_MAC_STATS        0x37
0090 #define QLCNIC_CMD_82XX_SET_DRV_VER     0x38
0091 #define QLCNIC_CMD_MQ_TX_CONFIG_INTR        0x39
0092 #define QLCNIC_CMD_GET_LED_STATUS       0x3C
0093 #define QLCNIC_CMD_CONFIGURE_RSS        0x41
0094 #define QLCNIC_CMD_CONFIG_INTR_COAL     0x43
0095 #define QLCNIC_CMD_CONFIGURE_LED        0x44
0096 #define QLCNIC_CMD_CONFIG_MAC_VLAN      0x45
0097 #define QLCNIC_CMD_GET_LINK_EVENT       0x48
0098 #define QLCNIC_CMD_CONFIGURE_MAC_RX_MODE    0x49
0099 #define QLCNIC_CMD_CONFIGURE_HW_LRO     0x4A
0100 #define QLCNIC_CMD_SET_INGRESS_ENCAP        0x4E
0101 #define QLCNIC_CMD_INIT_NIC_FUNC        0x60
0102 #define QLCNIC_CMD_STOP_NIC_FUNC        0x61
0103 #define QLCNIC_CMD_IDC_ACK          0x63
0104 #define QLCNIC_CMD_SET_PORT_CONFIG      0x66
0105 #define QLCNIC_CMD_GET_PORT_CONFIG      0x67
0106 #define QLCNIC_CMD_GET_LINK_STATUS      0x68
0107 #define QLCNIC_CMD_SET_LED_CONFIG       0x69
0108 #define QLCNIC_CMD_GET_LED_CONFIG       0x6A
0109 #define QLCNIC_CMD_83XX_SET_DRV_VER     0x6F
0110 #define QLCNIC_CMD_ADD_RCV_RINGS        0x0B
0111 #define QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP   0x37
0112
0113 #define QLCNIC_INTRPT_INTX          1
0114 #define QLCNIC_INTRPT_MSIX          3
0115 #define QLCNIC_INTRPT_ADD           1
0116 #define QLCNIC_INTRPT_DEL           2
0117
0118 #define QLCNIC_GET_CURRENT_MAC          1
0119 #define QLCNIC_SET_STATION_MAC          2
0120 #define QLCNIC_GET_DEFAULT_MAC          3
0121 #define QLCNIC_GET_FAC_DEF_MAC          4
0122 #define QLCNIC_SET_FAC_DEF_MAC          5
0123
0124 #define QLCNIC_MBX_LINK_EVENT       0x8001
0125 #define QLCNIC_MBX_BC_EVENT     0x8002
0126 #define QLCNIC_MBX_COMP_EVENT       0x8100
0127 #define QLCNIC_MBX_REQUEST_EVENT    0x8101
0128 #define QLCNIC_MBX_TIME_EXTEND_EVENT    0x8102
0129 #define QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT 0x8110
0130 #define QLCNIC_MBX_SFP_INSERT_EVENT 0x8130
0131 #define QLCNIC_MBX_SFP_REMOVE_EVENT 0x8131
0132
0133 struct qlcnic_mailbox_metadata {
0134     u32 cmd;
0135     u32 in_args;
0136     u32 out_args;
0137 };
0138
0139 /* Mailbox ownership */
0140 #define QLCNIC_GET_OWNER(val)   ((val) & (BIT_0 | BIT_1))
0141
0142 #define QLCNIC_SET_OWNER        1
0143 #define QLCNIC_CLR_OWNER        0
0144 #define QLCNIC_MBX_TIMEOUT      5000
0145
0146 #define QLCNIC_MBX_RSP_OK   1
0147 #define QLCNIC_MBX_PORT_RSP_OK  0x1a
0148 #define QLCNIC_MBX_ASYNC_EVENT  BIT_15
0149
0150 /* Set HW Tx ring limit for 82xx adapter. */
0151 #define QLCNIC_MAX_HW_TX_RINGS      8
0152 #define QLCNIC_MAX_HW_VNIC_TX_RINGS 4
0153 #define QLCNIC_MAX_TX_RINGS     8
0154 #define QLCNIC_MAX_SDS_RINGS        8
0155
0156 struct qlcnic_pci_info;
0157 struct qlcnic_info;
0158 struct qlcnic_cmd_args;
0159 struct ethtool_stats;
0160 struct pci_device_id;
0161 struct qlcnic_host_sds_ring;
0162 struct qlcnic_host_tx_ring;
0163 struct qlcnic_hardware_context;
0164 struct qlcnic_adapter;
0165 struct qlcnic_fw_dump;
0166
0167 int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong, int *);
0168 int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *, ulong, u32);
0169 int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int);
0170 int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
0171 int qlcnic_82xx_napi_add(struct qlcnic_adapter *adapter,
0172              struct net_device *netdev);
0173 void qlcnic_82xx_get_beacon_state(struct qlcnic_adapter *);
0174 void qlcnic_82xx_change_filter(struct qlcnic_adapter *adapter,
0175                    u64 *uaddr, u16 vlan_id,
0176                    struct qlcnic_host_tx_ring *tx_ring);
0177 int qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *,
0178                      struct ethtool_coalesce *);
0179 int qlcnic_82xx_set_rx_coalesce(struct qlcnic_adapter *);
0180 int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int);
0181 void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
0182                    __be32, int);
0183 int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int);
0184 void qlcnic_82xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
0185 int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8);
0186 int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *, u8);
0187 void qlcnic_82xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
0188 void qlcnic_82xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
0189 int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
0190               struct qlcnic_cmd_args *);
0191 int qlcnic_82xx_mq_intrpt(struct qlcnic_adapter *, int);
0192 int qlcnic_82xx_config_intrpt(struct qlcnic_adapter *, u8);
0193 int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *);
0194 int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *,
0195                      struct qlcnic_host_tx_ring *tx_ring, int);
0196 void qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter *);
0197 void qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter *,
0198                    struct qlcnic_host_tx_ring *);
0199 int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, u16, u8);
0200 int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *, u8*, u8);
0201 int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
0202 int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
0203 int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
0204 int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *,
0205                    struct qlcnic_adapter *, u32);
0206 int qlcnic_82xx_get_board_info(struct qlcnic_adapter *);
0207 int qlcnic_82xx_config_led(struct qlcnic_adapter *, u32, u32);
0208 void qlcnic_82xx_get_func_no(struct qlcnic_adapter *);
0209 int qlcnic_82xx_api_lock(struct qlcnic_adapter *);
0210 void qlcnic_82xx_api_unlock(struct qlcnic_adapter *);
0211 void qlcnic_82xx_napi_enable(struct qlcnic_adapter *);
0212 void qlcnic_82xx_napi_disable(struct qlcnic_adapter *);
0213 void qlcnic_82xx_napi_del(struct qlcnic_adapter *);
0214 int qlcnic_82xx_shutdown(struct pci_dev *);
0215 int qlcnic_82xx_resume(struct qlcnic_adapter *);
0216 void qlcnic_clr_all_drv_state(struct qlcnic_adapter *adapter, u8 failed);
0217 void qlcnic_fw_poll_work(struct work_struct *work);
0218
0219 u32 qlcnic_82xx_get_saved_state(void *, u32);
0220 void qlcnic_82xx_set_saved_state(void *, u32, u32);
0221 void qlcnic_82xx_cache_tmpl_hdr_values(struct qlcnic_fw_dump *);
0222 u32 qlcnic_82xx_get_cap_size(void *, int);
0223 void qlcnic_82xx_set_sys_info(void *, int, u32);
0224 void qlcnic_82xx_store_cap_mask(void *, u32);
0225 #endif              /* __QLCNIC_HW_H_ */