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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * QLogic qlcnic NIC Driver
0004  * Copyright (c) 2009-2013 QLogic Corporation
0005  */
0006 
0007 #include <linux/slab.h>
0008 #include <net/ip.h>
0009 #include <linux/bitops.h>
0010 
0011 #include "qlcnic.h"
0012 #include "qlcnic_hdr.h"
0013 
0014 #define MASK(n) ((1ULL<<(n))-1)
0015 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
0016 
0017 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
0018 
0019 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
0020 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
0021 #define CRB_WINDOW_2M   (0x130060)
0022 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
0023 #define CRB_INDIRECT_2M (0x1e0000UL)
0024 
0025 struct qlcnic_ms_reg_ctrl {
0026     u32 ocm_window;
0027     u32 control;
0028     u32 hi;
0029     u32 low;
0030     u32 rd[4];
0031     u32 wd[4];
0032     u64 off;
0033 };
0034 
0035 #ifndef readq
0036 static inline u64 readq(void __iomem *addr)
0037 {
0038     return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
0039 }
0040 #endif
0041 
0042 #ifndef writeq
0043 static inline void writeq(u64 val, void __iomem *addr)
0044 {
0045     writel(((u32) (val)), (addr));
0046     writel(((u32) (val >> 32)), (addr + 4));
0047 }
0048 #endif
0049 
0050 static struct crb_128M_2M_block_map
0051 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
0052     {{{0, 0,         0,         0} } },     /* 0: PCI */
0053     {{{1, 0x0100000, 0x0102000, 0x120000},  /* 1: PCIE */
0054       {1, 0x0110000, 0x0120000, 0x130000},
0055       {1, 0x0120000, 0x0122000, 0x124000},
0056       {1, 0x0130000, 0x0132000, 0x126000},
0057       {1, 0x0140000, 0x0142000, 0x128000},
0058       {1, 0x0150000, 0x0152000, 0x12a000},
0059       {1, 0x0160000, 0x0170000, 0x110000},
0060       {1, 0x0170000, 0x0172000, 0x12e000},
0061       {0, 0x0000000, 0x0000000, 0x000000},
0062       {0, 0x0000000, 0x0000000, 0x000000},
0063       {0, 0x0000000, 0x0000000, 0x000000},
0064       {0, 0x0000000, 0x0000000, 0x000000},
0065       {0, 0x0000000, 0x0000000, 0x000000},
0066       {0, 0x0000000, 0x0000000, 0x000000},
0067       {1, 0x01e0000, 0x01e0800, 0x122000},
0068       {0, 0x0000000, 0x0000000, 0x000000} } },
0069     {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
0070     {{{0, 0,         0,         0} } },     /* 3: */
0071     {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
0072     {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
0073     {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
0074     {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
0075     {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
0076       {0, 0x0000000, 0x0000000, 0x000000},
0077       {0, 0x0000000, 0x0000000, 0x000000},
0078       {0, 0x0000000, 0x0000000, 0x000000},
0079       {0, 0x0000000, 0x0000000, 0x000000},
0080       {0, 0x0000000, 0x0000000, 0x000000},
0081       {0, 0x0000000, 0x0000000, 0x000000},
0082       {0, 0x0000000, 0x0000000, 0x000000},
0083       {0, 0x0000000, 0x0000000, 0x000000},
0084       {0, 0x0000000, 0x0000000, 0x000000},
0085       {0, 0x0000000, 0x0000000, 0x000000},
0086       {0, 0x0000000, 0x0000000, 0x000000},
0087       {0, 0x0000000, 0x0000000, 0x000000},
0088       {0, 0x0000000, 0x0000000, 0x000000},
0089       {0, 0x0000000, 0x0000000, 0x000000},
0090       {1, 0x08f0000, 0x08f2000, 0x172000} } },
0091     {{{1, 0x0900000, 0x0902000, 0x174000},  /* 9: SQM1*/
0092       {0, 0x0000000, 0x0000000, 0x000000},
0093       {0, 0x0000000, 0x0000000, 0x000000},
0094       {0, 0x0000000, 0x0000000, 0x000000},
0095       {0, 0x0000000, 0x0000000, 0x000000},
0096       {0, 0x0000000, 0x0000000, 0x000000},
0097       {0, 0x0000000, 0x0000000, 0x000000},
0098       {0, 0x0000000, 0x0000000, 0x000000},
0099       {0, 0x0000000, 0x0000000, 0x000000},
0100       {0, 0x0000000, 0x0000000, 0x000000},
0101       {0, 0x0000000, 0x0000000, 0x000000},
0102       {0, 0x0000000, 0x0000000, 0x000000},
0103       {0, 0x0000000, 0x0000000, 0x000000},
0104       {0, 0x0000000, 0x0000000, 0x000000},
0105       {0, 0x0000000, 0x0000000, 0x000000},
0106       {1, 0x09f0000, 0x09f2000, 0x176000} } },
0107     {{{0, 0x0a00000, 0x0a02000, 0x178000},  /* 10: SQM2*/
0108       {0, 0x0000000, 0x0000000, 0x000000},
0109       {0, 0x0000000, 0x0000000, 0x000000},
0110       {0, 0x0000000, 0x0000000, 0x000000},
0111       {0, 0x0000000, 0x0000000, 0x000000},
0112       {0, 0x0000000, 0x0000000, 0x000000},
0113       {0, 0x0000000, 0x0000000, 0x000000},
0114       {0, 0x0000000, 0x0000000, 0x000000},
0115       {0, 0x0000000, 0x0000000, 0x000000},
0116       {0, 0x0000000, 0x0000000, 0x000000},
0117       {0, 0x0000000, 0x0000000, 0x000000},
0118       {0, 0x0000000, 0x0000000, 0x000000},
0119       {0, 0x0000000, 0x0000000, 0x000000},
0120       {0, 0x0000000, 0x0000000, 0x000000},
0121       {0, 0x0000000, 0x0000000, 0x000000},
0122       {1, 0x0af0000, 0x0af2000, 0x17a000} } },
0123     {{{0, 0x0b00000, 0x0b02000, 0x17c000},  /* 11: SQM3*/
0124       {0, 0x0000000, 0x0000000, 0x000000},
0125       {0, 0x0000000, 0x0000000, 0x000000},
0126       {0, 0x0000000, 0x0000000, 0x000000},
0127       {0, 0x0000000, 0x0000000, 0x000000},
0128       {0, 0x0000000, 0x0000000, 0x000000},
0129       {0, 0x0000000, 0x0000000, 0x000000},
0130       {0, 0x0000000, 0x0000000, 0x000000},
0131       {0, 0x0000000, 0x0000000, 0x000000},
0132       {0, 0x0000000, 0x0000000, 0x000000},
0133       {0, 0x0000000, 0x0000000, 0x000000},
0134       {0, 0x0000000, 0x0000000, 0x000000},
0135       {0, 0x0000000, 0x0000000, 0x000000},
0136       {0, 0x0000000, 0x0000000, 0x000000},
0137       {0, 0x0000000, 0x0000000, 0x000000},
0138       {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
0139     {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
0140     {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
0141     {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
0142     {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
0143     {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
0144     {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
0145     {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
0146     {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
0147     {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
0148     {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
0149     {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
0150     {{{0, 0,         0,         0} } }, /* 23: */
0151     {{{0, 0,         0,         0} } }, /* 24: */
0152     {{{0, 0,         0,         0} } }, /* 25: */
0153     {{{0, 0,         0,         0} } }, /* 26: */
0154     {{{0, 0,         0,         0} } }, /* 27: */
0155     {{{0, 0,         0,         0} } }, /* 28: */
0156     {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
0157     {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
0158     {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
0159     {{{0} } },              /* 32: PCI */
0160     {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
0161       {1, 0x2110000, 0x2120000, 0x130000},
0162       {1, 0x2120000, 0x2122000, 0x124000},
0163       {1, 0x2130000, 0x2132000, 0x126000},
0164       {1, 0x2140000, 0x2142000, 0x128000},
0165       {1, 0x2150000, 0x2152000, 0x12a000},
0166       {1, 0x2160000, 0x2170000, 0x110000},
0167       {1, 0x2170000, 0x2172000, 0x12e000},
0168       {0, 0x0000000, 0x0000000, 0x000000},
0169       {0, 0x0000000, 0x0000000, 0x000000},
0170       {0, 0x0000000, 0x0000000, 0x000000},
0171       {0, 0x0000000, 0x0000000, 0x000000},
0172       {0, 0x0000000, 0x0000000, 0x000000},
0173       {0, 0x0000000, 0x0000000, 0x000000},
0174       {0, 0x0000000, 0x0000000, 0x000000},
0175       {0, 0x0000000, 0x0000000, 0x000000} } },
0176     {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
0177     {{{0} } },              /* 35: */
0178     {{{0} } },              /* 36: */
0179     {{{0} } },              /* 37: */
0180     {{{0} } },              /* 38: */
0181     {{{0} } },              /* 39: */
0182     {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
0183     {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
0184     {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
0185     {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
0186     {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
0187     {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
0188     {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
0189     {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
0190     {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
0191     {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
0192     {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
0193     {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
0194     {{{0} } },              /* 52: */
0195     {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
0196     {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
0197     {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
0198     {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
0199     {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
0200     {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
0201     {{{0} } },              /* 59: I2C0 */
0202     {{{0} } },              /* 60: I2C1 */
0203     {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
0204     {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
0205     {{{1, 0x3f00000, 0x3f01000, 0x168000} } }   /* 63: P2NR0 */
0206 };
0207 
0208 /*
0209  * top 12 bits of crb internal address (hub, agent)
0210  */
0211 static const unsigned crb_hub_agt[64] = {
0212     0,
0213     QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
0214     QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
0215     QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
0216     0,
0217     QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
0218     QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
0219     QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
0220     QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
0221     QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
0222     QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
0223     QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
0224     QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
0225     QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
0226     QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
0227     QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
0228     QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
0229     QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
0230     QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
0231     QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
0232     QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
0233     QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
0234     QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
0235     QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
0236     QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
0237     QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
0238     QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
0239     0,
0240     QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
0241     QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
0242     0,
0243     QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
0244     0,
0245     QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
0246     QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
0247     0,
0248     0,
0249     0,
0250     0,
0251     0,
0252     QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
0253     0,
0254     QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
0255     QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
0256     QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
0257     QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
0258     QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
0259     QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
0260     QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
0261     QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
0262     QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
0263     QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
0264     0,
0265     QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
0266     QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
0267     QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
0268     QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
0269     0,
0270     QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
0271     QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
0272     QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
0273     0,
0274     QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
0275     0,
0276 };
0277 
0278 /*  PCI Windowing for DDR regions.  */
0279 
0280 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
0281 
0282 static void qlcnic_read_window_reg(u32 addr, void __iomem *bar0, u32 *data)
0283 {
0284     u32 dest;
0285     void __iomem *val;
0286 
0287     dest = addr & 0xFFFF0000;
0288     val = bar0 + QLCNIC_FW_DUMP_REG1;
0289     writel(dest, val);
0290     readl(val);
0291     val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
0292     *data = readl(val);
0293 }
0294 
0295 static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data)
0296 {
0297     u32 dest;
0298     void __iomem *val;
0299 
0300     dest = addr & 0xFFFF0000;
0301     val = bar0 + QLCNIC_FW_DUMP_REG1;
0302     writel(dest, val);
0303     readl(val);
0304     val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
0305     writel(data, val);
0306     readl(val);
0307 }
0308 
0309 int
0310 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
0311 {
0312     int timeout = 0, err = 0, done = 0;
0313 
0314     while (!done) {
0315         done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)),
0316                    &err);
0317         if (done == 1)
0318             break;
0319         if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
0320             if (id_reg) {
0321                 done = QLCRD32(adapter, id_reg, &err);
0322                 if (done != -1)
0323                     dev_err(&adapter->pdev->dev,
0324                         "Failed to acquire sem=%d lock held by=%d\n",
0325                         sem, done);
0326                 else
0327                     dev_err(&adapter->pdev->dev,
0328                         "Failed to acquire sem=%d lock",
0329                         sem);
0330             } else {
0331                 dev_err(&adapter->pdev->dev,
0332                     "Failed to acquire sem=%d lock", sem);
0333             }
0334             return -EIO;
0335         }
0336         udelay(1200);
0337     }
0338 
0339     if (id_reg)
0340         QLCWR32(adapter, id_reg, adapter->portnum);
0341 
0342     return 0;
0343 }
0344 
0345 void
0346 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
0347 {
0348     int err = 0;
0349 
0350     QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)), &err);
0351 }
0352 
0353 int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr)
0354 {
0355     int err = 0;
0356     u32 data;
0357 
0358     if (qlcnic_82xx_check(adapter))
0359         qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data);
0360     else {
0361         data = QLCRD32(adapter, addr, &err);
0362         if (err == -EIO)
0363             return err;
0364     }
0365     return data;
0366 }
0367 
0368 int qlcnic_ind_wr(struct qlcnic_adapter *adapter, u32 addr, u32 data)
0369 {
0370     int ret = 0;
0371 
0372     if (qlcnic_82xx_check(adapter))
0373         qlcnic_write_window_reg(addr, adapter->ahw->pci_base0, data);
0374     else
0375         ret = qlcnic_83xx_wrt_reg_indirect(adapter, addr, data);
0376 
0377     return ret;
0378 }
0379 
0380 static int
0381 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
0382         struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
0383 {
0384     u32 i, producer;
0385     struct qlcnic_cmd_buffer *pbuf;
0386     struct cmd_desc_type0 *cmd_desc;
0387     struct qlcnic_host_tx_ring *tx_ring;
0388 
0389     i = 0;
0390 
0391     if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
0392         return -EIO;
0393 
0394     tx_ring = &adapter->tx_ring[0];
0395     __netif_tx_lock_bh(tx_ring->txq);
0396 
0397     producer = tx_ring->producer;
0398 
0399     if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
0400         netif_tx_stop_queue(tx_ring->txq);
0401         smp_mb();
0402         if (qlcnic_tx_avail(tx_ring) > nr_desc) {
0403             if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
0404                 netif_tx_wake_queue(tx_ring->txq);
0405         } else {
0406             adapter->stats.xmit_off++;
0407             __netif_tx_unlock_bh(tx_ring->txq);
0408             return -EBUSY;
0409         }
0410     }
0411 
0412     do {
0413         cmd_desc = &cmd_desc_arr[i];
0414 
0415         pbuf = &tx_ring->cmd_buf_arr[producer];
0416         pbuf->skb = NULL;
0417         pbuf->frag_count = 0;
0418 
0419         memcpy(&tx_ring->desc_head[producer],
0420                cmd_desc, sizeof(struct cmd_desc_type0));
0421 
0422         producer = get_next_index(producer, tx_ring->num_desc);
0423         i++;
0424 
0425     } while (i != nr_desc);
0426 
0427     tx_ring->producer = producer;
0428 
0429     qlcnic_update_cmd_producer(tx_ring);
0430 
0431     __netif_tx_unlock_bh(tx_ring->txq);
0432 
0433     return 0;
0434 }
0435 
0436 int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
0437                    u16 vlan_id, u8 op)
0438 {
0439     struct qlcnic_nic_req req;
0440     struct qlcnic_mac_req *mac_req;
0441     struct qlcnic_vlan_req *vlan_req;
0442     u64 word;
0443 
0444     memset(&req, 0, sizeof(struct qlcnic_nic_req));
0445     req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
0446 
0447     word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
0448     req.req_hdr = cpu_to_le64(word);
0449 
0450     mac_req = (struct qlcnic_mac_req *)&req.words[0];
0451     mac_req->op = op;
0452     memcpy(mac_req->mac_addr, addr, ETH_ALEN);
0453 
0454     vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
0455     vlan_req->vlan_id = cpu_to_le16(vlan_id);
0456 
0457     return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
0458 }
0459 
0460 int qlcnic_nic_del_mac(struct qlcnic_adapter *adapter, const u8 *addr)
0461 {
0462     struct qlcnic_mac_vlan_list *cur;
0463     int err = -EINVAL;
0464 
0465     /* Delete MAC from the existing list */
0466     list_for_each_entry(cur, &adapter->mac_list, list) {
0467         if (ether_addr_equal(addr, cur->mac_addr)) {
0468             err = qlcnic_sre_macaddr_change(adapter, cur->mac_addr,
0469                             0, QLCNIC_MAC_DEL);
0470             if (err)
0471                 return err;
0472             list_del(&cur->list);
0473             kfree(cur);
0474             return err;
0475         }
0476     }
0477     return err;
0478 }
0479 
0480 int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr, u16 vlan,
0481                enum qlcnic_mac_type mac_type)
0482 {
0483     struct qlcnic_mac_vlan_list *cur;
0484 
0485     /* look up if already exists */
0486     list_for_each_entry(cur, &adapter->mac_list, list) {
0487         if (ether_addr_equal(addr, cur->mac_addr) &&
0488             cur->vlan_id == vlan)
0489             return 0;
0490     }
0491 
0492     cur = kzalloc(sizeof(*cur), GFP_ATOMIC);
0493     if (cur == NULL)
0494         return -ENOMEM;
0495 
0496     memcpy(cur->mac_addr, addr, ETH_ALEN);
0497 
0498     if (qlcnic_sre_macaddr_change(adapter,
0499                 cur->mac_addr, vlan, QLCNIC_MAC_ADD)) {
0500         kfree(cur);
0501         return -EIO;
0502     }
0503 
0504     cur->vlan_id = vlan;
0505     cur->mac_type = mac_type;
0506 
0507     list_add_tail(&cur->list, &adapter->mac_list);
0508     return 0;
0509 }
0510 
0511 void qlcnic_flush_mcast_mac(struct qlcnic_adapter *adapter)
0512 {
0513     struct qlcnic_mac_vlan_list *cur;
0514     struct list_head *head, *tmp;
0515 
0516     list_for_each_safe(head, tmp, &adapter->mac_list) {
0517         cur = list_entry(head, struct qlcnic_mac_vlan_list, list);
0518         if (cur->mac_type != QLCNIC_MULTICAST_MAC)
0519             continue;
0520 
0521         qlcnic_sre_macaddr_change(adapter, cur->mac_addr,
0522                       cur->vlan_id, QLCNIC_MAC_DEL);
0523         list_del(&cur->list);
0524         kfree(cur);
0525     }
0526 }
0527 
0528 static void __qlcnic_set_multi(struct net_device *netdev, u16 vlan)
0529 {
0530     struct qlcnic_adapter *adapter = netdev_priv(netdev);
0531     struct qlcnic_hardware_context *ahw = adapter->ahw;
0532     struct netdev_hw_addr *ha;
0533     static const u8 bcast_addr[ETH_ALEN] = {
0534         0xff, 0xff, 0xff, 0xff, 0xff, 0xff
0535     };
0536     u32 mode = VPORT_MISS_MODE_DROP;
0537 
0538     if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
0539         return;
0540 
0541     qlcnic_nic_add_mac(adapter, adapter->mac_addr, vlan,
0542                QLCNIC_UNICAST_MAC);
0543     qlcnic_nic_add_mac(adapter, bcast_addr, vlan, QLCNIC_BROADCAST_MAC);
0544 
0545     if (netdev->flags & IFF_PROMISC) {
0546         if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
0547             mode = VPORT_MISS_MODE_ACCEPT_ALL;
0548     } else if ((netdev->flags & IFF_ALLMULTI) ||
0549            (netdev_mc_count(netdev) > ahw->max_mc_count)) {
0550         mode = VPORT_MISS_MODE_ACCEPT_MULTI;
0551     } else if (!netdev_mc_empty(netdev)) {
0552         qlcnic_flush_mcast_mac(adapter);
0553         netdev_for_each_mc_addr(ha, netdev)
0554             qlcnic_nic_add_mac(adapter, ha->addr, vlan,
0555                        QLCNIC_MULTICAST_MAC);
0556     }
0557 
0558     /* configure unicast MAC address, if there is not sufficient space
0559      * to store all the unicast addresses then enable promiscuous mode
0560      */
0561     if (netdev_uc_count(netdev) > ahw->max_uc_count) {
0562         mode = VPORT_MISS_MODE_ACCEPT_ALL;
0563     } else if (!netdev_uc_empty(netdev)) {
0564         netdev_for_each_uc_addr(ha, netdev)
0565             qlcnic_nic_add_mac(adapter, ha->addr, vlan,
0566                        QLCNIC_UNICAST_MAC);
0567     }
0568 
0569     if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
0570         !adapter->fdb_mac_learn) {
0571         qlcnic_alloc_lb_filters_mem(adapter);
0572         adapter->drv_mac_learn = 1;
0573         if (adapter->flags & QLCNIC_ESWITCH_ENABLED)
0574             adapter->rx_mac_learn = true;
0575     } else {
0576         adapter->drv_mac_learn = 0;
0577         adapter->rx_mac_learn = false;
0578     }
0579 
0580     qlcnic_nic_set_promisc(adapter, mode);
0581 }
0582 
0583 void qlcnic_set_multi(struct net_device *netdev)
0584 {
0585     struct qlcnic_adapter *adapter = netdev_priv(netdev);
0586 
0587     if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
0588         return;
0589 
0590     if (qlcnic_sriov_vf_check(adapter))
0591         qlcnic_sriov_vf_set_multi(netdev);
0592     else
0593         __qlcnic_set_multi(netdev, 0);
0594 }
0595 
0596 int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
0597 {
0598     struct qlcnic_nic_req req;
0599     u64 word;
0600 
0601     memset(&req, 0, sizeof(struct qlcnic_nic_req));
0602 
0603     req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
0604 
0605     word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE |
0606             ((u64)adapter->portnum << 16);
0607     req.req_hdr = cpu_to_le64(word);
0608 
0609     req.words[0] = cpu_to_le64(mode);
0610 
0611     return qlcnic_send_cmd_descs(adapter,
0612                 (struct cmd_desc_type0 *)&req, 1);
0613 }
0614 
0615 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter)
0616 {
0617     struct list_head *head = &adapter->mac_list;
0618     struct qlcnic_mac_vlan_list *cur;
0619 
0620     while (!list_empty(head)) {
0621         cur = list_entry(head->next, struct qlcnic_mac_vlan_list, list);
0622         qlcnic_sre_macaddr_change(adapter,
0623                 cur->mac_addr, 0, QLCNIC_MAC_DEL);
0624         list_del(&cur->list);
0625         kfree(cur);
0626     }
0627 }
0628 
0629 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
0630 {
0631     struct qlcnic_filter *tmp_fil;
0632     struct hlist_node *n;
0633     struct hlist_head *head;
0634     int i;
0635     unsigned long expires;
0636     u8 cmd;
0637 
0638     for (i = 0; i < adapter->fhash.fbucket_size; i++) {
0639         head = &(adapter->fhash.fhead[i]);
0640         hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
0641             cmd =  tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
0642                           QLCNIC_MAC_DEL;
0643             expires = tmp_fil->ftime + QLCNIC_FILTER_AGE * HZ;
0644             if (time_before(expires, jiffies)) {
0645                 qlcnic_sre_macaddr_change(adapter,
0646                               tmp_fil->faddr,
0647                               tmp_fil->vlan_id,
0648                               cmd);
0649                 spin_lock_bh(&adapter->mac_learn_lock);
0650                 adapter->fhash.fnum--;
0651                 hlist_del(&tmp_fil->fnode);
0652                 spin_unlock_bh(&adapter->mac_learn_lock);
0653                 kfree(tmp_fil);
0654             }
0655         }
0656     }
0657     for (i = 0; i < adapter->rx_fhash.fbucket_size; i++) {
0658         head = &(adapter->rx_fhash.fhead[i]);
0659 
0660         hlist_for_each_entry_safe(tmp_fil, n, head, fnode)
0661         {
0662             expires = tmp_fil->ftime + QLCNIC_FILTER_AGE * HZ;
0663             if (time_before(expires, jiffies)) {
0664                 spin_lock_bh(&adapter->rx_mac_learn_lock);
0665                 adapter->rx_fhash.fnum--;
0666                 hlist_del(&tmp_fil->fnode);
0667                 spin_unlock_bh(&adapter->rx_mac_learn_lock);
0668                 kfree(tmp_fil);
0669             }
0670         }
0671     }
0672 }
0673 
0674 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
0675 {
0676     struct qlcnic_filter *tmp_fil;
0677     struct hlist_node *n;
0678     struct hlist_head *head;
0679     int i;
0680     u8 cmd;
0681 
0682     for (i = 0; i < adapter->fhash.fbucket_size; i++) {
0683         head = &(adapter->fhash.fhead[i]);
0684         hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
0685             cmd =  tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
0686                           QLCNIC_MAC_DEL;
0687             qlcnic_sre_macaddr_change(adapter,
0688                           tmp_fil->faddr,
0689                           tmp_fil->vlan_id,
0690                           cmd);
0691             spin_lock_bh(&adapter->mac_learn_lock);
0692             adapter->fhash.fnum--;
0693             hlist_del(&tmp_fil->fnode);
0694             spin_unlock_bh(&adapter->mac_learn_lock);
0695             kfree(tmp_fil);
0696         }
0697     }
0698 }
0699 
0700 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
0701 {
0702     struct qlcnic_nic_req req;
0703     int rv;
0704 
0705     memset(&req, 0, sizeof(struct qlcnic_nic_req));
0706 
0707     req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
0708     req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
0709         ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32));
0710 
0711     req.words[0] = cpu_to_le64(flag);
0712 
0713     rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
0714     if (rv != 0)
0715         dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n",
0716                 flag ? "Set" : "Reset");
0717     return rv;
0718 }
0719 
0720 int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
0721 {
0722     if (qlcnic_set_fw_loopback(adapter, mode))
0723         return -EIO;
0724 
0725     if (qlcnic_nic_set_promisc(adapter,
0726                    VPORT_MISS_MODE_ACCEPT_ALL)) {
0727         qlcnic_set_fw_loopback(adapter, 0);
0728         return -EIO;
0729     }
0730 
0731     msleep(1000);
0732     return 0;
0733 }
0734 
0735 int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
0736 {
0737     struct net_device *netdev = adapter->netdev;
0738 
0739     mode = VPORT_MISS_MODE_DROP;
0740     qlcnic_set_fw_loopback(adapter, 0);
0741 
0742     if (netdev->flags & IFF_PROMISC)
0743         mode = VPORT_MISS_MODE_ACCEPT_ALL;
0744     else if (netdev->flags & IFF_ALLMULTI)
0745         mode = VPORT_MISS_MODE_ACCEPT_MULTI;
0746 
0747     qlcnic_nic_set_promisc(adapter, mode);
0748     msleep(1000);
0749     return 0;
0750 }
0751 
0752 int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *adapter)
0753 {
0754     u8 mac[ETH_ALEN];
0755     int ret;
0756 
0757     ret = qlcnic_get_mac_address(adapter, mac,
0758                      adapter->ahw->physical_port);
0759     if (ret)
0760         return ret;
0761 
0762     memcpy(adapter->ahw->phys_port_id, mac, ETH_ALEN);
0763     adapter->flags |= QLCNIC_HAS_PHYS_PORT_ID;
0764 
0765     return 0;
0766 }
0767 
0768 int qlcnic_82xx_set_rx_coalesce(struct qlcnic_adapter *adapter)
0769 {
0770     struct qlcnic_nic_req req;
0771     int rv;
0772 
0773     memset(&req, 0, sizeof(struct qlcnic_nic_req));
0774 
0775     req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
0776 
0777     req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE |
0778         ((u64) adapter->portnum << 16));
0779 
0780     req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32);
0781     req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets |
0782             ((u64) adapter->ahw->coal.rx_time_us) << 16);
0783     req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out |
0784             ((u64) adapter->ahw->coal.type) << 32 |
0785             ((u64) adapter->ahw->coal.sts_ring_mask) << 40);
0786     rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
0787     if (rv != 0)
0788         dev_err(&adapter->netdev->dev,
0789             "Could not send interrupt coalescing parameters\n");
0790 
0791     return rv;
0792 }
0793 
0794 /* Send the interrupt coalescing parameter set by ethtool to the card. */
0795 int qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *adapter,
0796                      struct ethtool_coalesce *ethcoal)
0797 {
0798     struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
0799     int rv;
0800 
0801     coal->flag = QLCNIC_INTR_DEFAULT;
0802     coal->rx_time_us = ethcoal->rx_coalesce_usecs;
0803     coal->rx_packets = ethcoal->rx_max_coalesced_frames;
0804 
0805     rv = qlcnic_82xx_set_rx_coalesce(adapter);
0806 
0807     if (rv)
0808         netdev_err(adapter->netdev,
0809                "Failed to set Rx coalescing parameters\n");
0810 
0811     return rv;
0812 }
0813 
0814 #define QLCNIC_ENABLE_IPV4_LRO      BIT_0
0815 #define QLCNIC_ENABLE_IPV6_LRO      (BIT_1 | BIT_9)
0816 
0817 int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
0818 {
0819     struct qlcnic_nic_req req;
0820     u64 word;
0821     int rv;
0822 
0823     if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
0824         return 0;
0825 
0826     memset(&req, 0, sizeof(struct qlcnic_nic_req));
0827 
0828     req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
0829 
0830     word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
0831     req.req_hdr = cpu_to_le64(word);
0832 
0833     word = 0;
0834     if (enable) {
0835         word = QLCNIC_ENABLE_IPV4_LRO;
0836         if (adapter->ahw->extra_capability[0] &
0837             QLCNIC_FW_CAP2_HW_LRO_IPV6)
0838             word |= QLCNIC_ENABLE_IPV6_LRO;
0839     }
0840 
0841     req.words[0] = cpu_to_le64(word);
0842 
0843     rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
0844     if (rv != 0)
0845         dev_err(&adapter->netdev->dev,
0846             "Could not send configure hw lro request\n");
0847 
0848     return rv;
0849 }
0850 
0851 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
0852 {
0853     struct qlcnic_nic_req req;
0854     u64 word;
0855     int rv;
0856 
0857     if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
0858         return 0;
0859 
0860     memset(&req, 0, sizeof(struct qlcnic_nic_req));
0861 
0862     req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
0863 
0864     word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
0865         ((u64)adapter->portnum << 16);
0866     req.req_hdr = cpu_to_le64(word);
0867 
0868     req.words[0] = cpu_to_le64(enable);
0869 
0870     rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
0871     if (rv != 0)
0872         dev_err(&adapter->netdev->dev,
0873             "Could not send configure bridge mode request\n");
0874 
0875     adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
0876 
0877     return rv;
0878 }
0879 
0880 
0881 #define QLCNIC_RSS_HASHTYPE_IP_TCP  0x3
0882 #define QLCNIC_ENABLE_TYPE_C_RSS    BIT_10
0883 #define QLCNIC_RSS_FEATURE_FLAG (1ULL << 63)
0884 #define QLCNIC_RSS_IND_TABLE_MASK   0x7ULL
0885 
0886 int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int enable)
0887 {
0888     struct qlcnic_nic_req req;
0889     u64 word;
0890     int i, rv;
0891 
0892     static const u64 key[] = {
0893         0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
0894         0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
0895         0x255b0ec26d5a56daULL
0896     };
0897 
0898     memset(&req, 0, sizeof(struct qlcnic_nic_req));
0899     req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
0900 
0901     word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
0902     req.req_hdr = cpu_to_le64(word);
0903 
0904     /*
0905      * RSS request:
0906      * bits 3-0: hash_method
0907      *      5-4: hash_type_ipv4
0908      *  7-6: hash_type_ipv6
0909      *    8: enable
0910      *        9: use indirection table
0911      *       10: type-c rss
0912      *   11: udp rss
0913      *    47-12: reserved
0914      *    62-48: indirection table mask
0915      *   63: feature flag
0916      */
0917     word =  ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
0918         ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
0919         ((u64)(enable & 0x1) << 8) |
0920         ((u64)QLCNIC_RSS_IND_TABLE_MASK << 48) |
0921         (u64)QLCNIC_ENABLE_TYPE_C_RSS |
0922         (u64)QLCNIC_RSS_FEATURE_FLAG;
0923 
0924     req.words[0] = cpu_to_le64(word);
0925     for (i = 0; i < 5; i++)
0926         req.words[i+1] = cpu_to_le64(key[i]);
0927 
0928     rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
0929     if (rv != 0)
0930         dev_err(&adapter->netdev->dev, "could not configure RSS\n");
0931 
0932     return rv;
0933 }
0934 
0935 void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
0936                    __be32 ip, int cmd)
0937 {
0938     struct qlcnic_nic_req req;
0939     struct qlcnic_ipaddr *ipa;
0940     u64 word;
0941     int rv;
0942 
0943     memset(&req, 0, sizeof(struct qlcnic_nic_req));
0944     req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
0945 
0946     word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
0947     req.req_hdr = cpu_to_le64(word);
0948 
0949     req.words[0] = cpu_to_le64(cmd);
0950     ipa = (struct qlcnic_ipaddr *)&req.words[1];
0951     ipa->ipv4 = ip;
0952 
0953     rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
0954     if (rv != 0)
0955         dev_err(&adapter->netdev->dev,
0956                 "could not notify %s IP 0x%x request\n",
0957                 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
0958 }
0959 
0960 int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int enable)
0961 {
0962     struct qlcnic_nic_req req;
0963     u64 word;
0964     int rv;
0965     memset(&req, 0, sizeof(struct qlcnic_nic_req));
0966     req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
0967 
0968     word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
0969     req.req_hdr = cpu_to_le64(word);
0970     req.words[0] = cpu_to_le64(enable | (enable << 8));
0971     rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
0972     if (rv != 0)
0973         dev_err(&adapter->netdev->dev,
0974                 "could not configure link notification\n");
0975 
0976     return rv;
0977 }
0978 
0979 static int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
0980 {
0981     struct qlcnic_nic_req req;
0982     u64 word;
0983     int rv;
0984 
0985     if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
0986         return 0;
0987 
0988     memset(&req, 0, sizeof(struct qlcnic_nic_req));
0989     req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
0990 
0991     word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
0992         ((u64)adapter->portnum << 16) |
0993         ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
0994 
0995     req.req_hdr = cpu_to_le64(word);
0996 
0997     rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
0998     if (rv != 0)
0999         dev_err(&adapter->netdev->dev,
1000                  "could not cleanup lro flows\n");
1001 
1002     return rv;
1003 }
1004 
1005 /*
1006  * qlcnic_change_mtu - Change the Maximum Transfer Unit
1007  * @returns 0 on success, negative on failure
1008  */
1009 
1010 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
1011 {
1012     struct qlcnic_adapter *adapter = netdev_priv(netdev);
1013     int rc = 0;
1014 
1015     rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
1016 
1017     if (!rc)
1018         netdev->mtu = mtu;
1019 
1020     return rc;
1021 }
1022 
1023 static netdev_features_t qlcnic_process_flags(struct qlcnic_adapter *adapter,
1024                           netdev_features_t features)
1025 {
1026     u32 offload_flags = adapter->offload_flags;
1027 
1028     if (offload_flags & BIT_0) {
1029         features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
1030                 NETIF_F_IPV6_CSUM;
1031         adapter->rx_csum = 1;
1032         if (QLCNIC_IS_TSO_CAPABLE(adapter)) {
1033             if (!(offload_flags & BIT_1))
1034                 features &= ~NETIF_F_TSO;
1035             else
1036                 features |= NETIF_F_TSO;
1037 
1038             if (!(offload_flags & BIT_2))
1039                 features &= ~NETIF_F_TSO6;
1040             else
1041                 features |= NETIF_F_TSO6;
1042         }
1043     } else {
1044         features &= ~(NETIF_F_RXCSUM |
1045                   NETIF_F_IP_CSUM |
1046                   NETIF_F_IPV6_CSUM);
1047 
1048         if (QLCNIC_IS_TSO_CAPABLE(adapter))
1049             features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
1050         adapter->rx_csum = 0;
1051     }
1052 
1053     return features;
1054 }
1055 
1056 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1057     netdev_features_t features)
1058 {
1059     struct qlcnic_adapter *adapter = netdev_priv(netdev);
1060     netdev_features_t changed;
1061 
1062     if (qlcnic_82xx_check(adapter) &&
1063         (adapter->flags & QLCNIC_ESWITCH_ENABLED)) {
1064         if (adapter->flags & QLCNIC_APP_CHANGED_FLAGS) {
1065             features = qlcnic_process_flags(adapter, features);
1066         } else {
1067             changed = features ^ netdev->features;
1068             features ^= changed & (NETIF_F_RXCSUM |
1069                            NETIF_F_IP_CSUM |
1070                            NETIF_F_IPV6_CSUM |
1071                            NETIF_F_TSO |
1072                            NETIF_F_TSO6);
1073         }
1074     }
1075 
1076     if (!(features & NETIF_F_RXCSUM))
1077         features &= ~NETIF_F_LRO;
1078 
1079     return features;
1080 }
1081 
1082 
1083 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features)
1084 {
1085     struct qlcnic_adapter *adapter = netdev_priv(netdev);
1086     netdev_features_t changed = netdev->features ^ features;
1087     int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0;
1088 
1089     if (!(changed & NETIF_F_LRO))
1090         return 0;
1091 
1092     netdev->features ^= NETIF_F_LRO;
1093 
1094     if (qlcnic_config_hw_lro(adapter, hw_lro))
1095         return -EIO;
1096 
1097     if (!hw_lro && qlcnic_82xx_check(adapter)) {
1098         if (qlcnic_send_lro_cleanup(adapter))
1099             return -EIO;
1100     }
1101 
1102     return 0;
1103 }
1104 
1105 /*
1106  * Changes the CRB window to the specified window.
1107  */
1108  /* Returns < 0 if off is not valid,
1109  *   1 if window access is needed. 'off' is set to offset from
1110  *     CRB space in 128M pci map
1111  *   0 if no window access is needed. 'off' is set to 2M addr
1112  * In: 'off' is offset from base in 128M pci map
1113  */
1114 static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context *ahw,
1115                       ulong off, void __iomem **addr)
1116 {
1117     const struct crb_128M_2M_sub_block_map *m;
1118 
1119     if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
1120         return -EINVAL;
1121 
1122     off -= QLCNIC_PCI_CRBSPACE;
1123 
1124     /*
1125      * Try direct map
1126      */
1127     m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
1128 
1129     if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1130         *addr = ahw->pci_base0 + m->start_2M +
1131             (off - m->start_128M);
1132         return 0;
1133     }
1134 
1135     /*
1136      * Not in direct map, use crb window
1137      */
1138     *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
1139     return 1;
1140 }
1141 
1142 /*
1143  * In: 'off' is offset from CRB space in 128M pci map
1144  * Out: 'off' is 2M pci map addr
1145  * side effect: lock crb window
1146  */
1147 static int
1148 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
1149 {
1150     u32 window;
1151     void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M;
1152 
1153     off -= QLCNIC_PCI_CRBSPACE;
1154 
1155     window = CRB_HI(off);
1156     if (window == 0) {
1157         dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
1158         return -EIO;
1159     }
1160 
1161     writel(window, addr);
1162     if (readl(addr) != window) {
1163         if (printk_ratelimit())
1164             dev_warn(&adapter->pdev->dev,
1165                 "failed to set CRB window to %d off 0x%lx\n",
1166                 window, off);
1167         return -EIO;
1168     }
1169     return 0;
1170 }
1171 
1172 int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1173                    u32 data)
1174 {
1175     unsigned long flags;
1176     int rv;
1177     void __iomem *addr = NULL;
1178 
1179     rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1180 
1181     if (rv == 0) {
1182         writel(data, addr);
1183         return 0;
1184     }
1185 
1186     if (rv > 0) {
1187         /* indirect access */
1188         write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1189         crb_win_lock(adapter);
1190         rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
1191         if (!rv)
1192             writel(data, addr);
1193         crb_win_unlock(adapter);
1194         write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1195         return rv;
1196     }
1197 
1198     dev_err(&adapter->pdev->dev,
1199             "%s: invalid offset: 0x%016lx\n", __func__, off);
1200     dump_stack();
1201     return -EIO;
1202 }
1203 
1204 int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1205                   int *err)
1206 {
1207     unsigned long flags;
1208     int rv;
1209     u32 data = -1;
1210     void __iomem *addr = NULL;
1211 
1212     rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1213 
1214     if (rv == 0)
1215         return readl(addr);
1216 
1217     if (rv > 0) {
1218         /* indirect access */
1219         write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1220         crb_win_lock(adapter);
1221         if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
1222             data = readl(addr);
1223         crb_win_unlock(adapter);
1224         write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1225         return data;
1226     }
1227 
1228     dev_err(&adapter->pdev->dev,
1229             "%s: invalid offset: 0x%016lx\n", __func__, off);
1230     dump_stack();
1231     return -1;
1232 }
1233 
1234 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *ahw,
1235                 u32 offset)
1236 {
1237     void __iomem *addr = NULL;
1238 
1239     WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw, offset, &addr));
1240 
1241     return addr;
1242 }
1243 
1244 static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter,
1245                     u32 window, u64 off, u64 *data, int op)
1246 {
1247     void __iomem *addr;
1248     u32 start;
1249 
1250     mutex_lock(&adapter->ahw->mem_lock);
1251 
1252     writel(window, adapter->ahw->ocm_win_crb);
1253     /* read back to flush */
1254     readl(adapter->ahw->ocm_win_crb);
1255     start = QLCNIC_PCI_OCM0_2M + off;
1256 
1257     addr = adapter->ahw->pci_base0 + start;
1258 
1259     if (op == 0)    /* read */
1260         *data = readq(addr);
1261     else        /* write */
1262         writeq(*data, addr);
1263 
1264     /* Set window to 0 */
1265     writel(0, adapter->ahw->ocm_win_crb);
1266     readl(adapter->ahw->ocm_win_crb);
1267 
1268     mutex_unlock(&adapter->ahw->mem_lock);
1269     return 0;
1270 }
1271 
1272 static void
1273 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1274 {
1275     void __iomem *addr = adapter->ahw->pci_base0 +
1276         QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1277 
1278     mutex_lock(&adapter->ahw->mem_lock);
1279     *data = readq(addr);
1280     mutex_unlock(&adapter->ahw->mem_lock);
1281 }
1282 
1283 static void
1284 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1285 {
1286     void __iomem *addr = adapter->ahw->pci_base0 +
1287         QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1288 
1289     mutex_lock(&adapter->ahw->mem_lock);
1290     writeq(data, addr);
1291     mutex_unlock(&adapter->ahw->mem_lock);
1292 }
1293 
1294 
1295 
1296 /* Set MS memory control data for different adapters */
1297 static void qlcnic_set_ms_controls(struct qlcnic_adapter *adapter, u64 off,
1298                    struct qlcnic_ms_reg_ctrl *ms)
1299 {
1300     ms->control = QLCNIC_MS_CTRL;
1301     ms->low = QLCNIC_MS_ADDR_LO;
1302     ms->hi = QLCNIC_MS_ADDR_HI;
1303     if (off & 0xf) {
1304         ms->wd[0] = QLCNIC_MS_WRTDATA_LO;
1305         ms->rd[0] = QLCNIC_MS_RDDATA_LO;
1306         ms->wd[1] = QLCNIC_MS_WRTDATA_HI;
1307         ms->rd[1] = QLCNIC_MS_RDDATA_HI;
1308         ms->wd[2] = QLCNIC_MS_WRTDATA_ULO;
1309         ms->wd[3] = QLCNIC_MS_WRTDATA_UHI;
1310         ms->rd[2] = QLCNIC_MS_RDDATA_ULO;
1311         ms->rd[3] = QLCNIC_MS_RDDATA_UHI;
1312     } else {
1313         ms->wd[0] = QLCNIC_MS_WRTDATA_ULO;
1314         ms->rd[0] = QLCNIC_MS_RDDATA_ULO;
1315         ms->wd[1] = QLCNIC_MS_WRTDATA_UHI;
1316         ms->rd[1] = QLCNIC_MS_RDDATA_UHI;
1317         ms->wd[2] = QLCNIC_MS_WRTDATA_LO;
1318         ms->wd[3] = QLCNIC_MS_WRTDATA_HI;
1319         ms->rd[2] = QLCNIC_MS_RDDATA_LO;
1320         ms->rd[3] = QLCNIC_MS_RDDATA_HI;
1321     }
1322 
1323     ms->ocm_window = OCM_WIN_P3P(off);
1324     ms->off = GET_MEM_OFFS_2M(off);
1325 }
1326 
1327 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1328 {
1329     int j, ret = 0;
1330     u32 temp, off8;
1331     struct qlcnic_ms_reg_ctrl ms;
1332 
1333     /* Only 64-bit aligned access */
1334     if (off & 7)
1335         return -EIO;
1336 
1337     memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1338     if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1339                 QLCNIC_ADDR_QDR_NET_MAX) ||
1340           ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1341                 QLCNIC_ADDR_DDR_NET_MAX)))
1342         return -EIO;
1343 
1344     qlcnic_set_ms_controls(adapter, off, &ms);
1345 
1346     if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1347         return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1348                             ms.off, &data, 1);
1349 
1350     off8 = off & ~0xf;
1351 
1352     mutex_lock(&adapter->ahw->mem_lock);
1353 
1354     qlcnic_ind_wr(adapter, ms.low, off8);
1355     qlcnic_ind_wr(adapter, ms.hi, 0);
1356 
1357     qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1358     qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1359 
1360     for (j = 0; j < MAX_CTL_CHECK; j++) {
1361         temp = qlcnic_ind_rd(adapter, ms.control);
1362         if ((temp & TA_CTL_BUSY) == 0)
1363             break;
1364     }
1365 
1366     if (j >= MAX_CTL_CHECK) {
1367         ret = -EIO;
1368         goto done;
1369     }
1370 
1371     /* This is the modify part of read-modify-write */
1372     qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0]));
1373     qlcnic_ind_wr(adapter, ms.wd[1], qlcnic_ind_rd(adapter, ms.rd[1]));
1374     /* This is the write part of read-modify-write */
1375     qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff);
1376     qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff);
1377 
1378     qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_ENABLE);
1379     qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_START);
1380 
1381     for (j = 0; j < MAX_CTL_CHECK; j++) {
1382         temp = qlcnic_ind_rd(adapter, ms.control);
1383         if ((temp & TA_CTL_BUSY) == 0)
1384             break;
1385     }
1386 
1387     if (j >= MAX_CTL_CHECK) {
1388         if (printk_ratelimit())
1389             dev_err(&adapter->pdev->dev,
1390                     "failed to write through agent\n");
1391         ret = -EIO;
1392     } else
1393         ret = 0;
1394 
1395 done:
1396     mutex_unlock(&adapter->ahw->mem_lock);
1397 
1398     return ret;
1399 }
1400 
1401 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1402 {
1403     int j, ret;
1404     u32 temp, off8;
1405     u64 val;
1406     struct qlcnic_ms_reg_ctrl ms;
1407 
1408     /* Only 64-bit aligned access */
1409     if (off & 7)
1410         return -EIO;
1411     if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1412                 QLCNIC_ADDR_QDR_NET_MAX) ||
1413           ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1414                 QLCNIC_ADDR_DDR_NET_MAX)))
1415         return -EIO;
1416 
1417     memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1418     qlcnic_set_ms_controls(adapter, off, &ms);
1419 
1420     if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1421         return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1422                             ms.off, data, 0);
1423 
1424     mutex_lock(&adapter->ahw->mem_lock);
1425 
1426     off8 = off & ~0xf;
1427 
1428     qlcnic_ind_wr(adapter, ms.low, off8);
1429     qlcnic_ind_wr(adapter, ms.hi, 0);
1430 
1431     qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1432     qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1433 
1434     for (j = 0; j < MAX_CTL_CHECK; j++) {
1435         temp = qlcnic_ind_rd(adapter, ms.control);
1436         if ((temp & TA_CTL_BUSY) == 0)
1437             break;
1438     }
1439 
1440     if (j >= MAX_CTL_CHECK) {
1441         if (printk_ratelimit())
1442             dev_err(&adapter->pdev->dev,
1443                     "failed to read through agent\n");
1444         ret = -EIO;
1445     } else {
1446 
1447         temp = qlcnic_ind_rd(adapter, ms.rd[3]);
1448         val = (u64)temp << 32;
1449         val |= qlcnic_ind_rd(adapter, ms.rd[2]);
1450         *data = val;
1451         ret = 0;
1452     }
1453 
1454     mutex_unlock(&adapter->ahw->mem_lock);
1455 
1456     return ret;
1457 }
1458 
1459 int qlcnic_82xx_get_board_info(struct qlcnic_adapter *adapter)
1460 {
1461     int offset, board_type, magic, err = 0;
1462     struct pci_dev *pdev = adapter->pdev;
1463 
1464     offset = QLCNIC_FW_MAGIC_OFFSET;
1465     if (qlcnic_rom_fast_read(adapter, offset, &magic))
1466         return -EIO;
1467 
1468     if (magic != QLCNIC_BDINFO_MAGIC) {
1469         dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1470             magic);
1471         return -EIO;
1472     }
1473 
1474     offset = QLCNIC_BRDTYPE_OFFSET;
1475     if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1476         return -EIO;
1477 
1478     adapter->ahw->board_type = board_type;
1479 
1480     if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
1481         u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I, &err);
1482         if (err == -EIO)
1483             return err;
1484         if ((gpio & 0x8000) == 0)
1485             board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
1486     }
1487 
1488     switch (board_type) {
1489     case QLCNIC_BRDTYPE_P3P_HMEZ:
1490     case QLCNIC_BRDTYPE_P3P_XG_LOM:
1491     case QLCNIC_BRDTYPE_P3P_10G_CX4:
1492     case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
1493     case QLCNIC_BRDTYPE_P3P_IMEZ:
1494     case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
1495     case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
1496     case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
1497     case QLCNIC_BRDTYPE_P3P_10G_XFP:
1498     case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
1499         adapter->ahw->port_type = QLCNIC_XGBE;
1500         break;
1501     case QLCNIC_BRDTYPE_P3P_REF_QG:
1502     case QLCNIC_BRDTYPE_P3P_4_GB:
1503     case QLCNIC_BRDTYPE_P3P_4_GB_MM:
1504         adapter->ahw->port_type = QLCNIC_GBE;
1505         break;
1506     case QLCNIC_BRDTYPE_P3P_10G_TP:
1507         adapter->ahw->port_type = (adapter->portnum < 2) ?
1508             QLCNIC_XGBE : QLCNIC_GBE;
1509         break;
1510     default:
1511         dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1512         adapter->ahw->port_type = QLCNIC_XGBE;
1513         break;
1514     }
1515 
1516     return 0;
1517 }
1518 
1519 static int
1520 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1521 {
1522     u32 wol_cfg;
1523     int err = 0;
1524 
1525     wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV, &err);
1526     if (wol_cfg & (1UL << adapter->portnum)) {
1527         wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG, &err);
1528         if (err == -EIO)
1529             return err;
1530         if (wol_cfg & (1 << adapter->portnum))
1531             return 1;
1532     }
1533 
1534     return 0;
1535 }
1536 
1537 int qlcnic_82xx_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1538 {
1539     struct qlcnic_nic_req   req;
1540     int rv;
1541     u64 word;
1542 
1543     memset(&req, 0, sizeof(struct qlcnic_nic_req));
1544     req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1545 
1546     word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1547     req.req_hdr = cpu_to_le64(word);
1548 
1549     req.words[0] = cpu_to_le64(((u64)rate << 32) | adapter->portnum);
1550     req.words[1] = cpu_to_le64(state);
1551 
1552     rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1553     if (rv)
1554         dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1555 
1556     return rv;
1557 }
1558 
1559 void qlcnic_82xx_get_beacon_state(struct qlcnic_adapter *adapter)
1560 {
1561     struct qlcnic_hardware_context *ahw = adapter->ahw;
1562     struct qlcnic_cmd_args cmd;
1563     u8 beacon_state;
1564     int err = 0;
1565 
1566     if (ahw->extra_capability[0] & QLCNIC_FW_CAPABILITY_2_BEACON) {
1567         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1568                         QLCNIC_CMD_GET_LED_STATUS);
1569         if (!err) {
1570             err = qlcnic_issue_cmd(adapter, &cmd);
1571             if (err) {
1572                 netdev_err(adapter->netdev,
1573                        "Failed to get current beacon state, err=%d\n",
1574                        err);
1575             } else {
1576                 beacon_state = cmd.rsp.arg[1];
1577                 if (beacon_state == QLCNIC_BEACON_DISABLE)
1578                     ahw->beacon_state = QLCNIC_BEACON_OFF;
1579                 else if (beacon_state == QLCNIC_BEACON_EANBLE)
1580                     ahw->beacon_state = QLCNIC_BEACON_ON;
1581             }
1582         }
1583         qlcnic_free_mbx_args(&cmd);
1584     }
1585 
1586     return;
1587 }
1588 
1589 void qlcnic_82xx_get_func_no(struct qlcnic_adapter *adapter)
1590 {
1591     void __iomem *msix_base_addr;
1592     u32 func;
1593     u32 msix_base;
1594 
1595     pci_read_config_dword(adapter->pdev, QLCNIC_MSIX_TABLE_OFFSET, &func);
1596     msix_base_addr = adapter->ahw->pci_base0 + QLCNIC_MSIX_BASE;
1597     msix_base = readl(msix_base_addr);
1598     func = (func - msix_base) / QLCNIC_MSIX_TBL_PGSIZE;
1599     adapter->ahw->pci_func = func;
1600 }
1601 
1602 void qlcnic_82xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
1603               loff_t offset, size_t size)
1604 {
1605     int err = 0;
1606     u32 data;
1607     u64 qmdata;
1608 
1609     if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1610         qlcnic_pci_camqm_read_2M(adapter, offset, &qmdata);
1611         memcpy(buf, &qmdata, size);
1612     } else {
1613         data = QLCRD32(adapter, offset, &err);
1614         memcpy(buf, &data, size);
1615     }
1616 }
1617 
1618 void qlcnic_82xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
1619                loff_t offset, size_t size)
1620 {
1621     u32 data;
1622     u64 qmdata;
1623 
1624     if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1625         memcpy(&qmdata, buf, size);
1626         qlcnic_pci_camqm_write_2M(adapter, offset, qmdata);
1627     } else {
1628         memcpy(&data, buf, size);
1629         QLCWR32(adapter, offset, data);
1630     }
1631 }
1632 
1633 int qlcnic_82xx_api_lock(struct qlcnic_adapter *adapter)
1634 {
1635     return qlcnic_pcie_sem_lock(adapter, 5, 0);
1636 }
1637 
1638 void qlcnic_82xx_api_unlock(struct qlcnic_adapter *adapter)
1639 {
1640     qlcnic_pcie_sem_unlock(adapter, 5);
1641 }
1642 
1643 int qlcnic_82xx_shutdown(struct pci_dev *pdev)
1644 {
1645     struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
1646     struct net_device *netdev = adapter->netdev;
1647 
1648     netif_device_detach(netdev);
1649 
1650     qlcnic_cancel_idc_work(adapter);
1651 
1652     if (netif_running(netdev))
1653         qlcnic_down(adapter, netdev);
1654 
1655     qlcnic_clr_all_drv_state(adapter, 0);
1656 
1657     clear_bit(__QLCNIC_RESETTING, &adapter->state);
1658 
1659     if (qlcnic_wol_supported(adapter))
1660         device_wakeup_enable(&pdev->dev);
1661 
1662     return 0;
1663 }
1664 
1665 int qlcnic_82xx_resume(struct qlcnic_adapter *adapter)
1666 {
1667     struct net_device *netdev = adapter->netdev;
1668     int err;
1669 
1670     err = qlcnic_start_firmware(adapter);
1671     if (err) {
1672         dev_err(&adapter->pdev->dev, "failed to start firmware\n");
1673         return err;
1674     }
1675 
1676     if (netif_running(netdev)) {
1677         err = qlcnic_up(adapter, netdev);
1678         if (!err)
1679             qlcnic_restore_indev_addr(netdev, NETDEV_UP);
1680     }
1681 
1682     netif_device_attach(netdev);
1683     qlcnic_schedule_work(adapter, qlcnic_fw_poll_work, FW_POLL_DELAY);
1684     return err;
1685 }
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