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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * QLogic qlcnic NIC Driver
0004  * Copyright (c)  2009-2013 QLogic Corporation
0005  */
0006 
0007 #include <linux/types.h>
0008 #include "qlcnic.h"
0009 
0010 #define QLC_DCB_NUM_PARAM       3
0011 #define QLC_DCB_LOCAL_IDX       0
0012 #define QLC_DCB_OPER_IDX        1
0013 #define QLC_DCB_PEER_IDX        2
0014 
0015 #define QLC_DCB_GET_MAP(V)      (1 << V)
0016 
0017 #define QLC_DCB_FW_VER          0x2
0018 #define QLC_DCB_MAX_TC          0x8
0019 #define QLC_DCB_MAX_APP         0x8
0020 #define QLC_DCB_MAX_PRIO        QLC_DCB_MAX_TC
0021 #define QLC_DCB_MAX_PG          QLC_DCB_MAX_TC
0022 
0023 #define QLC_DCB_TSA_SUPPORT(V)      (V & 0x1)
0024 #define QLC_DCB_ETS_SUPPORT(V)      ((V >> 1) & 0x1)
0025 #define QLC_DCB_VERSION_SUPPORT(V)  ((V >> 2) & 0xf)
0026 #define QLC_DCB_MAX_NUM_TC(V)       ((V >> 20) & 0xf)
0027 #define QLC_DCB_MAX_NUM_ETS_TC(V)   ((V >> 24) & 0xf)
0028 #define QLC_DCB_MAX_NUM_PFC_TC(V)   ((V >> 28) & 0xf)
0029 #define QLC_DCB_GET_TC_PRIO(X, P)   ((X >> (P * 3)) & 0x7)
0030 #define QLC_DCB_GET_PGID_PRIO(X, P) ((X >> (P * 8)) & 0xff)
0031 #define QLC_DCB_GET_BWPER_PG(X, P)  ((X >> (P * 8)) & 0xff)
0032 #define QLC_DCB_GET_TSA_PG(X, P)    ((X >> (P * 8)) & 0xff)
0033 #define QLC_DCB_GET_PFC_PRIO(X, P)  (((X >> 24) >> P) & 0x1)
0034 #define QLC_DCB_GET_PROTO_ID_APP(X) ((X >> 8) & 0xffff)
0035 #define QLC_DCB_GET_SELECTOR_APP(X) (X & 0xff)
0036 
0037 #define QLC_DCB_LOCAL_PARAM_FWID    0x3
0038 #define QLC_DCB_OPER_PARAM_FWID     0x1
0039 #define QLC_DCB_PEER_PARAM_FWID     0x2
0040 
0041 #define QLC_83XX_DCB_GET_NUMAPP(X)  ((X >> 2) & 0xf)
0042 #define QLC_83XX_DCB_TSA_VALID(X)   (X & 0x1)
0043 #define QLC_83XX_DCB_PFC_VALID(X)   ((X >> 1) & 0x1)
0044 #define QLC_83XX_DCB_GET_PRIOMAP_APP(X) (X >> 24)
0045 
0046 #define QLC_82XX_DCB_GET_NUMAPP(X)  ((X >> 12) & 0xf)
0047 #define QLC_82XX_DCB_TSA_VALID(X)   ((X >> 4) & 0x1)
0048 #define QLC_82XX_DCB_PFC_VALID(X)   ((X >> 5) & 0x1)
0049 #define QLC_82XX_DCB_GET_PRIOVAL_APP(X) ((X >> 24) & 0x7)
0050 #define QLC_82XX_DCB_GET_PRIOMAP_APP(X) (1 << X)
0051 #define QLC_82XX_DCB_PRIO_TC_MAP    (0x76543210)
0052 
0053 static const struct dcbnl_rtnl_ops qlcnic_dcbnl_ops;
0054 
0055 static void qlcnic_dcb_aen_work(struct work_struct *);
0056 static void qlcnic_dcb_data_cee_param_map(struct qlcnic_adapter *);
0057 
0058 static inline void __qlcnic_init_dcbnl_ops(struct qlcnic_dcb *);
0059 static void __qlcnic_dcb_free(struct qlcnic_dcb *);
0060 static int __qlcnic_dcb_attach(struct qlcnic_dcb *);
0061 static int __qlcnic_dcb_query_hw_capability(struct qlcnic_dcb *, char *);
0062 static void __qlcnic_dcb_get_info(struct qlcnic_dcb *);
0063 
0064 static int qlcnic_82xx_dcb_get_hw_capability(struct qlcnic_dcb *);
0065 static int qlcnic_82xx_dcb_query_cee_param(struct qlcnic_dcb *, char *, u8);
0066 static int qlcnic_82xx_dcb_get_cee_cfg(struct qlcnic_dcb *);
0067 static void qlcnic_82xx_dcb_aen_handler(struct qlcnic_dcb *, void *);
0068 
0069 static int qlcnic_83xx_dcb_get_hw_capability(struct qlcnic_dcb *);
0070 static int qlcnic_83xx_dcb_query_cee_param(struct qlcnic_dcb *, char *, u8);
0071 static int qlcnic_83xx_dcb_get_cee_cfg(struct qlcnic_dcb *);
0072 static void qlcnic_83xx_dcb_aen_handler(struct qlcnic_dcb *, void *);
0073 
0074 struct qlcnic_dcb_capability {
0075     bool    tsa_capability;
0076     bool    ets_capability;
0077     u8  max_num_tc;
0078     u8  max_ets_tc;
0079     u8  max_pfc_tc;
0080     u8  dcb_capability;
0081 };
0082 
0083 struct qlcnic_dcb_param {
0084     u32 hdr_prio_pfc_map[2];
0085     u32 prio_pg_map[2];
0086     u32 pg_bw_map[2];
0087     u32 pg_tsa_map[2];
0088     u32 app[QLC_DCB_MAX_APP];
0089 };
0090 
0091 struct qlcnic_dcb_mbx_params {
0092     /* 1st local, 2nd operational 3rd remote */
0093     struct qlcnic_dcb_param type[3];
0094     u32 prio_tc_map;
0095 };
0096 
0097 struct qlcnic_82xx_dcb_param_mbx_le {
0098     __le32 hdr_prio_pfc_map[2];
0099     __le32 prio_pg_map[2];
0100     __le32 pg_bw_map[2];
0101     __le32 pg_tsa_map[2];
0102     __le32 app[QLC_DCB_MAX_APP];
0103 };
0104 
0105 enum qlcnic_dcb_selector {
0106     QLC_SELECTOR_DEF = 0x0,
0107     QLC_SELECTOR_ETHER,
0108     QLC_SELECTOR_TCP,
0109     QLC_SELECTOR_UDP,
0110 };
0111 
0112 enum qlcnic_dcb_prio_type {
0113     QLC_PRIO_NONE = 0,
0114     QLC_PRIO_GROUP,
0115     QLC_PRIO_LINK,
0116 };
0117 
0118 enum qlcnic_dcb_pfc_type {
0119     QLC_PFC_DISABLED = 0,
0120     QLC_PFC_FULL,
0121     QLC_PFC_TX,
0122     QLC_PFC_RX
0123 };
0124 
0125 struct qlcnic_dcb_prio_cfg {
0126     bool valid;
0127     enum qlcnic_dcb_pfc_type pfc_type;
0128 };
0129 
0130 struct qlcnic_dcb_pg_cfg {
0131     bool valid;
0132     u8 total_bw_percent;        /* of Link/ port BW */
0133     u8 prio_count;
0134     u8 tsa_type;
0135 };
0136 
0137 struct qlcnic_dcb_tc_cfg {
0138     bool valid;
0139     struct qlcnic_dcb_prio_cfg prio_cfg[QLC_DCB_MAX_PRIO];
0140     enum qlcnic_dcb_prio_type prio_type;    /* always prio_link */
0141     u8 link_percent;            /* % of link bandwidth */
0142     u8 bwg_percent;             /* % of BWG's bandwidth */
0143     u8 up_tc_map;
0144     u8 pgid;
0145 };
0146 
0147 struct qlcnic_dcb_app {
0148     bool valid;
0149     enum qlcnic_dcb_selector selector;
0150     u16 protocol;
0151     u8 priority;
0152 };
0153 
0154 struct qlcnic_dcb_cee {
0155     struct qlcnic_dcb_tc_cfg tc_cfg[QLC_DCB_MAX_TC];
0156     struct qlcnic_dcb_pg_cfg pg_cfg[QLC_DCB_MAX_PG];
0157     struct qlcnic_dcb_app app[QLC_DCB_MAX_APP];
0158     bool tc_param_valid;
0159     bool pfc_mode_enable;
0160 };
0161 
0162 struct qlcnic_dcb_cfg {
0163     /* 0 - local, 1 - operational, 2 - remote */
0164     struct qlcnic_dcb_cee type[QLC_DCB_NUM_PARAM];
0165     struct qlcnic_dcb_capability capability;
0166     u32 version;
0167 };
0168 
0169 static const struct qlcnic_dcb_ops qlcnic_83xx_dcb_ops = {
0170     .init_dcbnl_ops     = __qlcnic_init_dcbnl_ops,
0171     .free           = __qlcnic_dcb_free,
0172     .attach         = __qlcnic_dcb_attach,
0173     .query_hw_capability    = __qlcnic_dcb_query_hw_capability,
0174     .get_info       = __qlcnic_dcb_get_info,
0175 
0176     .get_hw_capability  = qlcnic_83xx_dcb_get_hw_capability,
0177     .query_cee_param    = qlcnic_83xx_dcb_query_cee_param,
0178     .get_cee_cfg        = qlcnic_83xx_dcb_get_cee_cfg,
0179     .aen_handler        = qlcnic_83xx_dcb_aen_handler,
0180 };
0181 
0182 static const struct qlcnic_dcb_ops qlcnic_82xx_dcb_ops = {
0183     .init_dcbnl_ops     = __qlcnic_init_dcbnl_ops,
0184     .free           = __qlcnic_dcb_free,
0185     .attach         = __qlcnic_dcb_attach,
0186     .query_hw_capability    = __qlcnic_dcb_query_hw_capability,
0187     .get_info       = __qlcnic_dcb_get_info,
0188 
0189     .get_hw_capability  = qlcnic_82xx_dcb_get_hw_capability,
0190     .query_cee_param    = qlcnic_82xx_dcb_query_cee_param,
0191     .get_cee_cfg        = qlcnic_82xx_dcb_get_cee_cfg,
0192     .aen_handler        = qlcnic_82xx_dcb_aen_handler,
0193 };
0194 
0195 static u8 qlcnic_dcb_get_num_app(struct qlcnic_adapter *adapter, u32 val)
0196 {
0197     if (qlcnic_82xx_check(adapter))
0198         return QLC_82XX_DCB_GET_NUMAPP(val);
0199     else
0200         return QLC_83XX_DCB_GET_NUMAPP(val);
0201 }
0202 
0203 static inline u8 qlcnic_dcb_pfc_hdr_valid(struct qlcnic_adapter *adapter,
0204                       u32 val)
0205 {
0206     if (qlcnic_82xx_check(adapter))
0207         return QLC_82XX_DCB_PFC_VALID(val);
0208     else
0209         return QLC_83XX_DCB_PFC_VALID(val);
0210 }
0211 
0212 static inline u8 qlcnic_dcb_tsa_hdr_valid(struct qlcnic_adapter *adapter,
0213                       u32 val)
0214 {
0215     if (qlcnic_82xx_check(adapter))
0216         return QLC_82XX_DCB_TSA_VALID(val);
0217     else
0218         return QLC_83XX_DCB_TSA_VALID(val);
0219 }
0220 
0221 static inline u8 qlcnic_dcb_get_prio_map_app(struct qlcnic_adapter *adapter,
0222                          u32 val)
0223 {
0224     if (qlcnic_82xx_check(adapter))
0225         return QLC_82XX_DCB_GET_PRIOMAP_APP(val);
0226     else
0227         return QLC_83XX_DCB_GET_PRIOMAP_APP(val);
0228 }
0229 
0230 static int qlcnic_dcb_prio_count(u8 up_tc_map)
0231 {
0232     int j;
0233 
0234     for (j = 0; j < QLC_DCB_MAX_TC; j++)
0235         if (up_tc_map & QLC_DCB_GET_MAP(j))
0236             break;
0237 
0238     return j;
0239 }
0240 
0241 static inline void __qlcnic_init_dcbnl_ops(struct qlcnic_dcb *dcb)
0242 {
0243     if (test_bit(QLCNIC_DCB_STATE, &dcb->state))
0244         dcb->adapter->netdev->dcbnl_ops = &qlcnic_dcbnl_ops;
0245 }
0246 
0247 static void qlcnic_set_dcb_ops(struct qlcnic_adapter *adapter)
0248 {
0249     if (qlcnic_82xx_check(adapter))
0250         adapter->dcb->ops = &qlcnic_82xx_dcb_ops;
0251     else if (qlcnic_83xx_check(adapter))
0252         adapter->dcb->ops = &qlcnic_83xx_dcb_ops;
0253 }
0254 
0255 int qlcnic_register_dcb(struct qlcnic_adapter *adapter)
0256 {
0257     struct qlcnic_dcb *dcb;
0258 
0259     if (qlcnic_sriov_vf_check(adapter))
0260         return 0;
0261 
0262     dcb = kzalloc(sizeof(struct qlcnic_dcb), GFP_ATOMIC);
0263     if (!dcb)
0264         return -ENOMEM;
0265 
0266     adapter->dcb = dcb;
0267     dcb->adapter = adapter;
0268     qlcnic_set_dcb_ops(adapter);
0269     dcb->state = 0;
0270 
0271     return 0;
0272 }
0273 
0274 static void __qlcnic_dcb_free(struct qlcnic_dcb *dcb)
0275 {
0276     struct qlcnic_adapter *adapter;
0277 
0278     if (!dcb)
0279         return;
0280 
0281     adapter = dcb->adapter;
0282 
0283     while (test_bit(QLCNIC_DCB_AEN_MODE, &dcb->state))
0284         usleep_range(10000, 11000);
0285 
0286     cancel_delayed_work_sync(&dcb->aen_work);
0287 
0288     if (dcb->wq) {
0289         destroy_workqueue(dcb->wq);
0290         dcb->wq = NULL;
0291     }
0292 
0293     kfree(dcb->cfg);
0294     dcb->cfg = NULL;
0295     kfree(dcb->param);
0296     dcb->param = NULL;
0297     kfree(dcb);
0298     adapter->dcb = NULL;
0299 }
0300 
0301 static void __qlcnic_dcb_get_info(struct qlcnic_dcb *dcb)
0302 {
0303     qlcnic_dcb_get_hw_capability(dcb);
0304     qlcnic_dcb_get_cee_cfg(dcb);
0305 }
0306 
0307 static int __qlcnic_dcb_attach(struct qlcnic_dcb *dcb)
0308 {
0309     int err = 0;
0310 
0311     INIT_DELAYED_WORK(&dcb->aen_work, qlcnic_dcb_aen_work);
0312 
0313     dcb->wq = create_singlethread_workqueue("qlcnic-dcb");
0314     if (!dcb->wq) {
0315         dev_err(&dcb->adapter->pdev->dev,
0316             "DCB workqueue allocation failed. DCB will be disabled\n");
0317         return -1;
0318     }
0319 
0320     dcb->cfg = kzalloc(sizeof(struct qlcnic_dcb_cfg), GFP_ATOMIC);
0321     if (!dcb->cfg) {
0322         err = -ENOMEM;
0323         goto out_free_wq;
0324     }
0325 
0326     dcb->param = kzalloc(sizeof(struct qlcnic_dcb_mbx_params), GFP_ATOMIC);
0327     if (!dcb->param) {
0328         err = -ENOMEM;
0329         goto out_free_cfg;
0330     }
0331 
0332     return 0;
0333 out_free_cfg:
0334     kfree(dcb->cfg);
0335     dcb->cfg = NULL;
0336 
0337 out_free_wq:
0338     destroy_workqueue(dcb->wq);
0339     dcb->wq = NULL;
0340 
0341     return err;
0342 }
0343 
0344 static int __qlcnic_dcb_query_hw_capability(struct qlcnic_dcb *dcb, char *buf)
0345 {
0346     struct qlcnic_adapter *adapter = dcb->adapter;
0347     struct qlcnic_cmd_args cmd;
0348     u32 mbx_out;
0349     int err;
0350 
0351     err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DCB_QUERY_CAP);
0352     if (err)
0353         return err;
0354 
0355     err = qlcnic_issue_cmd(adapter, &cmd);
0356     if (err) {
0357         dev_err(&adapter->pdev->dev,
0358             "Failed to query DCBX capability, err %d\n", err);
0359     } else {
0360         mbx_out = cmd.rsp.arg[1];
0361         if (buf)
0362             memcpy(buf, &mbx_out, sizeof(u32));
0363     }
0364 
0365     qlcnic_free_mbx_args(&cmd);
0366 
0367     return err;
0368 }
0369 
0370 static int __qlcnic_dcb_get_capability(struct qlcnic_dcb *dcb, u32 *val)
0371 {
0372     struct qlcnic_dcb_capability *cap = &dcb->cfg->capability;
0373     u32 mbx_out;
0374     int err;
0375 
0376     memset(cap, 0, sizeof(struct qlcnic_dcb_capability));
0377 
0378     err = qlcnic_dcb_query_hw_capability(dcb, (char *)val);
0379     if (err)
0380         return err;
0381 
0382     mbx_out = *val;
0383     if (QLC_DCB_TSA_SUPPORT(mbx_out))
0384         cap->tsa_capability = true;
0385 
0386     if (QLC_DCB_ETS_SUPPORT(mbx_out))
0387         cap->ets_capability = true;
0388 
0389     cap->max_num_tc = QLC_DCB_MAX_NUM_TC(mbx_out);
0390     cap->max_ets_tc = QLC_DCB_MAX_NUM_ETS_TC(mbx_out);
0391     cap->max_pfc_tc = QLC_DCB_MAX_NUM_PFC_TC(mbx_out);
0392 
0393     if (cap->max_num_tc > QLC_DCB_MAX_TC ||
0394         cap->max_ets_tc > cap->max_num_tc ||
0395         cap->max_pfc_tc > cap->max_num_tc) {
0396         dev_err(&dcb->adapter->pdev->dev, "Invalid DCB configuration\n");
0397         return -EINVAL;
0398     }
0399 
0400     return err;
0401 }
0402 
0403 static int qlcnic_82xx_dcb_get_hw_capability(struct qlcnic_dcb *dcb)
0404 {
0405     struct qlcnic_dcb_cfg *cfg = dcb->cfg;
0406     struct qlcnic_dcb_capability *cap;
0407     u32 mbx_out;
0408     int err;
0409 
0410     err = __qlcnic_dcb_get_capability(dcb, &mbx_out);
0411     if (err)
0412         return err;
0413 
0414     cap = &cfg->capability;
0415     cap->dcb_capability = DCB_CAP_DCBX_VER_CEE | DCB_CAP_DCBX_LLD_MANAGED;
0416 
0417     if (cap->dcb_capability && cap->tsa_capability && cap->ets_capability)
0418         set_bit(QLCNIC_DCB_STATE, &dcb->state);
0419 
0420     return err;
0421 }
0422 
0423 static int qlcnic_82xx_dcb_query_cee_param(struct qlcnic_dcb *dcb,
0424                        char *buf, u8 type)
0425 {
0426     u16 size = sizeof(struct qlcnic_82xx_dcb_param_mbx_le);
0427     struct qlcnic_adapter *adapter = dcb->adapter;
0428     struct qlcnic_82xx_dcb_param_mbx_le *prsp_le;
0429     struct device *dev = &adapter->pdev->dev;
0430     dma_addr_t cardrsp_phys_addr;
0431     struct qlcnic_dcb_param rsp;
0432     struct qlcnic_cmd_args cmd;
0433     u64 phys_addr;
0434     void *addr;
0435     int err, i;
0436 
0437     switch (type) {
0438     case QLC_DCB_LOCAL_PARAM_FWID:
0439     case QLC_DCB_OPER_PARAM_FWID:
0440     case QLC_DCB_PEER_PARAM_FWID:
0441         break;
0442     default:
0443         dev_err(dev, "Invalid parameter type %d\n", type);
0444         return -EINVAL;
0445     }
0446 
0447     addr = dma_alloc_coherent(dev, size, &cardrsp_phys_addr, GFP_KERNEL);
0448     if (addr == NULL)
0449         return -ENOMEM;
0450 
0451     prsp_le = addr;
0452 
0453     err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DCB_QUERY_PARAM);
0454     if (err)
0455         goto out_free_rsp;
0456 
0457     phys_addr = cardrsp_phys_addr;
0458     cmd.req.arg[1] = size | (type << 16);
0459     cmd.req.arg[2] = MSD(phys_addr);
0460     cmd.req.arg[3] = LSD(phys_addr);
0461 
0462     err = qlcnic_issue_cmd(adapter, &cmd);
0463     if (err) {
0464         dev_err(dev, "Failed to query DCBX parameter, err %d\n", err);
0465         goto out;
0466     }
0467 
0468     memset(&rsp, 0, sizeof(struct qlcnic_dcb_param));
0469     rsp.hdr_prio_pfc_map[0] = le32_to_cpu(prsp_le->hdr_prio_pfc_map[0]);
0470     rsp.hdr_prio_pfc_map[1] = le32_to_cpu(prsp_le->hdr_prio_pfc_map[1]);
0471     rsp.prio_pg_map[0] = le32_to_cpu(prsp_le->prio_pg_map[0]);
0472     rsp.prio_pg_map[1] = le32_to_cpu(prsp_le->prio_pg_map[1]);
0473     rsp.pg_bw_map[0] = le32_to_cpu(prsp_le->pg_bw_map[0]);
0474     rsp.pg_bw_map[1] = le32_to_cpu(prsp_le->pg_bw_map[1]);
0475     rsp.pg_tsa_map[0] = le32_to_cpu(prsp_le->pg_tsa_map[0]);
0476     rsp.pg_tsa_map[1] = le32_to_cpu(prsp_le->pg_tsa_map[1]);
0477 
0478     for (i = 0; i < QLC_DCB_MAX_APP; i++)
0479         rsp.app[i] = le32_to_cpu(prsp_le->app[i]);
0480 
0481     if (buf)
0482         memcpy(buf, &rsp, size);
0483 out:
0484     qlcnic_free_mbx_args(&cmd);
0485 
0486 out_free_rsp:
0487     dma_free_coherent(dev, size, addr, cardrsp_phys_addr);
0488 
0489     return err;
0490 }
0491 
0492 static int qlcnic_82xx_dcb_get_cee_cfg(struct qlcnic_dcb *dcb)
0493 {
0494     struct qlcnic_dcb_mbx_params *mbx;
0495     int err;
0496 
0497     mbx = dcb->param;
0498     if (!mbx)
0499         return 0;
0500 
0501     err = qlcnic_dcb_query_cee_param(dcb, (char *)&mbx->type[0],
0502                      QLC_DCB_LOCAL_PARAM_FWID);
0503     if (err)
0504         return err;
0505 
0506     err = qlcnic_dcb_query_cee_param(dcb, (char *)&mbx->type[1],
0507                      QLC_DCB_OPER_PARAM_FWID);
0508     if (err)
0509         return err;
0510 
0511     err = qlcnic_dcb_query_cee_param(dcb, (char *)&mbx->type[2],
0512                      QLC_DCB_PEER_PARAM_FWID);
0513     if (err)
0514         return err;
0515 
0516     mbx->prio_tc_map = QLC_82XX_DCB_PRIO_TC_MAP;
0517 
0518     qlcnic_dcb_data_cee_param_map(dcb->adapter);
0519 
0520     return err;
0521 }
0522 
0523 static void qlcnic_dcb_aen_work(struct work_struct *work)
0524 {
0525     struct qlcnic_dcb *dcb;
0526 
0527     dcb = container_of(work, struct qlcnic_dcb, aen_work.work);
0528 
0529     qlcnic_dcb_get_cee_cfg(dcb);
0530     clear_bit(QLCNIC_DCB_AEN_MODE, &dcb->state);
0531 }
0532 
0533 static void qlcnic_82xx_dcb_aen_handler(struct qlcnic_dcb *dcb, void *data)
0534 {
0535     if (test_and_set_bit(QLCNIC_DCB_AEN_MODE, &dcb->state))
0536         return;
0537 
0538     queue_delayed_work(dcb->wq, &dcb->aen_work, 0);
0539 }
0540 
0541 static int qlcnic_83xx_dcb_get_hw_capability(struct qlcnic_dcb *dcb)
0542 {
0543     struct qlcnic_dcb_capability *cap = &dcb->cfg->capability;
0544     u32 mbx_out;
0545     int err;
0546 
0547     err = __qlcnic_dcb_get_capability(dcb, &mbx_out);
0548     if (err)
0549         return err;
0550 
0551     if (mbx_out & BIT_2)
0552         cap->dcb_capability = DCB_CAP_DCBX_VER_CEE;
0553     if (mbx_out & BIT_3)
0554         cap->dcb_capability |= DCB_CAP_DCBX_VER_IEEE;
0555     if (cap->dcb_capability)
0556         cap->dcb_capability |= DCB_CAP_DCBX_LLD_MANAGED;
0557 
0558     if (cap->dcb_capability && cap->tsa_capability && cap->ets_capability)
0559         set_bit(QLCNIC_DCB_STATE, &dcb->state);
0560 
0561     return err;
0562 }
0563 
0564 static int qlcnic_83xx_dcb_query_cee_param(struct qlcnic_dcb *dcb,
0565                        char *buf, u8 idx)
0566 {
0567     struct qlcnic_adapter *adapter = dcb->adapter;
0568     struct qlcnic_dcb_mbx_params mbx_out;
0569     int err, i, j, k, max_app, size;
0570     struct qlcnic_dcb_param *each;
0571     struct qlcnic_cmd_args cmd;
0572     u32 val;
0573     char *p;
0574 
0575     size = 0;
0576     memset(&mbx_out, 0, sizeof(struct qlcnic_dcb_mbx_params));
0577     memset(buf, 0, sizeof(struct qlcnic_dcb_mbx_params));
0578 
0579     err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DCB_QUERY_PARAM);
0580     if (err)
0581         return err;
0582 
0583     cmd.req.arg[0] |= QLC_DCB_FW_VER << 29;
0584     err = qlcnic_issue_cmd(adapter, &cmd);
0585     if (err) {
0586         dev_err(&adapter->pdev->dev,
0587             "Failed to query DCBX param, err %d\n", err);
0588         goto out;
0589     }
0590 
0591     mbx_out.prio_tc_map = cmd.rsp.arg[1];
0592     p = memcpy(buf, &mbx_out, sizeof(u32));
0593     k = 2;
0594     p += sizeof(u32);
0595 
0596     for (j = 0; j < QLC_DCB_NUM_PARAM; j++) {
0597         each = &mbx_out.type[j];
0598 
0599         each->hdr_prio_pfc_map[0] = cmd.rsp.arg[k++];
0600         each->hdr_prio_pfc_map[1] = cmd.rsp.arg[k++];
0601         each->prio_pg_map[0] = cmd.rsp.arg[k++];
0602         each->prio_pg_map[1] = cmd.rsp.arg[k++];
0603         each->pg_bw_map[0] = cmd.rsp.arg[k++];
0604         each->pg_bw_map[1] = cmd.rsp.arg[k++];
0605         each->pg_tsa_map[0] = cmd.rsp.arg[k++];
0606         each->pg_tsa_map[1] = cmd.rsp.arg[k++];
0607         val = each->hdr_prio_pfc_map[0];
0608 
0609         max_app = qlcnic_dcb_get_num_app(adapter, val);
0610         for (i = 0; i < max_app; i++)
0611             each->app[i] = cmd.rsp.arg[i + k];
0612 
0613         size = 16 * sizeof(u32);
0614         memcpy(p, &each->hdr_prio_pfc_map[0], size);
0615         p += size;
0616         if (j == 0)
0617             k = 18;
0618         else
0619             k = 34;
0620     }
0621 out:
0622     qlcnic_free_mbx_args(&cmd);
0623 
0624     return err;
0625 }
0626 
0627 static int qlcnic_83xx_dcb_get_cee_cfg(struct qlcnic_dcb *dcb)
0628 {
0629     int err;
0630 
0631     err = qlcnic_dcb_query_cee_param(dcb, (char *)dcb->param, 0);
0632     if (err)
0633         return err;
0634 
0635     qlcnic_dcb_data_cee_param_map(dcb->adapter);
0636 
0637     return err;
0638 }
0639 
0640 static void qlcnic_83xx_dcb_aen_handler(struct qlcnic_dcb *dcb, void *data)
0641 {
0642     u32 *val = data;
0643 
0644     if (test_and_set_bit(QLCNIC_DCB_AEN_MODE, &dcb->state))
0645         return;
0646 
0647     if (*val & BIT_8)
0648         set_bit(QLCNIC_DCB_STATE, &dcb->state);
0649     else
0650         clear_bit(QLCNIC_DCB_STATE, &dcb->state);
0651 
0652     queue_delayed_work(dcb->wq, &dcb->aen_work, 0);
0653 }
0654 
0655 static void qlcnic_dcb_fill_cee_tc_params(struct qlcnic_dcb_mbx_params *mbx,
0656                       struct qlcnic_dcb_param *each,
0657                       struct qlcnic_dcb_cee *type)
0658 {
0659     struct qlcnic_dcb_tc_cfg *tc_cfg;
0660     u8 i, tc, pgid;
0661 
0662     for (i = 0; i < QLC_DCB_MAX_PRIO; i++) {
0663         tc = QLC_DCB_GET_TC_PRIO(mbx->prio_tc_map, i);
0664         tc_cfg = &type->tc_cfg[tc];
0665         tc_cfg->valid = true;
0666         tc_cfg->up_tc_map |= QLC_DCB_GET_MAP(i);
0667 
0668         if (QLC_DCB_GET_PFC_PRIO(each->hdr_prio_pfc_map[1], i) &&
0669             type->pfc_mode_enable) {
0670             tc_cfg->prio_cfg[i].valid = true;
0671             tc_cfg->prio_cfg[i].pfc_type = QLC_PFC_FULL;
0672         }
0673 
0674         if (i < 4)
0675             pgid = QLC_DCB_GET_PGID_PRIO(each->prio_pg_map[0], i);
0676         else
0677             pgid = QLC_DCB_GET_PGID_PRIO(each->prio_pg_map[1], i);
0678 
0679         tc_cfg->pgid = pgid;
0680 
0681         tc_cfg->prio_type = QLC_PRIO_LINK;
0682         type->pg_cfg[tc_cfg->pgid].prio_count++;
0683     }
0684 }
0685 
0686 static void qlcnic_dcb_fill_cee_pg_params(struct qlcnic_dcb_param *each,
0687                       struct qlcnic_dcb_cee *type)
0688 {
0689     struct qlcnic_dcb_pg_cfg *pg_cfg;
0690     u8 i, tsa, bw_per;
0691 
0692     for (i = 0; i < QLC_DCB_MAX_PG; i++) {
0693         pg_cfg = &type->pg_cfg[i];
0694         pg_cfg->valid = true;
0695 
0696         if (i < 4) {
0697             bw_per = QLC_DCB_GET_BWPER_PG(each->pg_bw_map[0], i);
0698             tsa = QLC_DCB_GET_TSA_PG(each->pg_tsa_map[0], i);
0699         } else {
0700             bw_per = QLC_DCB_GET_BWPER_PG(each->pg_bw_map[1], i);
0701             tsa = QLC_DCB_GET_TSA_PG(each->pg_tsa_map[1], i);
0702         }
0703 
0704         pg_cfg->total_bw_percent = bw_per;
0705         pg_cfg->tsa_type = tsa;
0706     }
0707 }
0708 
0709 static void
0710 qlcnic_dcb_fill_cee_app_params(struct qlcnic_adapter *adapter, u8 idx,
0711                    struct qlcnic_dcb_param *each,
0712                    struct qlcnic_dcb_cee *type)
0713 {
0714     struct qlcnic_dcb_app *app;
0715     u8 i, num_app, map, cnt;
0716     struct dcb_app new_app;
0717 
0718     num_app = qlcnic_dcb_get_num_app(adapter, each->hdr_prio_pfc_map[0]);
0719     for (i = 0; i < num_app; i++) {
0720         app = &type->app[i];
0721         app->valid = true;
0722 
0723         /* Only for CEE (-1) */
0724         app->selector = QLC_DCB_GET_SELECTOR_APP(each->app[i]) - 1;
0725         new_app.selector = app->selector;
0726         app->protocol = QLC_DCB_GET_PROTO_ID_APP(each->app[i]);
0727         new_app.protocol = app->protocol;
0728         map = qlcnic_dcb_get_prio_map_app(adapter, each->app[i]);
0729         cnt = qlcnic_dcb_prio_count(map);
0730 
0731         if (cnt >= QLC_DCB_MAX_TC)
0732             cnt = 0;
0733 
0734         app->priority = cnt;
0735         new_app.priority = cnt;
0736 
0737         if (idx == QLC_DCB_OPER_IDX && adapter->netdev->dcbnl_ops)
0738             dcb_setapp(adapter->netdev, &new_app);
0739     }
0740 }
0741 
0742 static void qlcnic_dcb_map_cee_params(struct qlcnic_adapter *adapter, u8 idx)
0743 {
0744     struct qlcnic_dcb_mbx_params *mbx = adapter->dcb->param;
0745     struct qlcnic_dcb_param *each = &mbx->type[idx];
0746     struct qlcnic_dcb_cfg *cfg = adapter->dcb->cfg;
0747     struct qlcnic_dcb_cee *type = &cfg->type[idx];
0748 
0749     type->tc_param_valid = false;
0750     type->pfc_mode_enable = false;
0751     memset(type->tc_cfg, 0,
0752            sizeof(struct qlcnic_dcb_tc_cfg) * QLC_DCB_MAX_TC);
0753     memset(type->pg_cfg, 0,
0754            sizeof(struct qlcnic_dcb_pg_cfg) * QLC_DCB_MAX_TC);
0755 
0756     if (qlcnic_dcb_pfc_hdr_valid(adapter, each->hdr_prio_pfc_map[0]) &&
0757         cfg->capability.max_pfc_tc)
0758         type->pfc_mode_enable = true;
0759 
0760     if (qlcnic_dcb_tsa_hdr_valid(adapter, each->hdr_prio_pfc_map[0]) &&
0761         cfg->capability.max_ets_tc)
0762         type->tc_param_valid = true;
0763 
0764     qlcnic_dcb_fill_cee_tc_params(mbx, each, type);
0765     qlcnic_dcb_fill_cee_pg_params(each, type);
0766     qlcnic_dcb_fill_cee_app_params(adapter, idx, each, type);
0767 }
0768 
0769 static void qlcnic_dcb_data_cee_param_map(struct qlcnic_adapter *adapter)
0770 {
0771     int i;
0772 
0773     for (i = 0; i < QLC_DCB_NUM_PARAM; i++)
0774         qlcnic_dcb_map_cee_params(adapter, i);
0775 
0776     dcbnl_cee_notify(adapter->netdev, RTM_GETDCB, DCB_CMD_CEE_GET, 0, 0);
0777 }
0778 
0779 static u8 qlcnic_dcb_get_state(struct net_device *netdev)
0780 {
0781     struct qlcnic_adapter *adapter = netdev_priv(netdev);
0782 
0783     return test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state);
0784 }
0785 
0786 static void qlcnic_dcb_get_perm_hw_addr(struct net_device *netdev, u8 *addr)
0787 {
0788     memcpy(addr, netdev->perm_addr, netdev->addr_len);
0789 }
0790 
0791 static void
0792 qlcnic_dcb_get_pg_tc_cfg_tx(struct net_device *netdev, int tc, u8 *prio,
0793                 u8 *pgid, u8 *bw_per, u8 *up_tc_map)
0794 {
0795     struct qlcnic_adapter *adapter = netdev_priv(netdev);
0796     struct qlcnic_dcb_tc_cfg *tc_cfg, *temp;
0797     struct qlcnic_dcb_cee *type;
0798     u8 i, cnt, pg;
0799 
0800     type = &adapter->dcb->cfg->type[QLC_DCB_OPER_IDX];
0801     *prio = *pgid = *bw_per = *up_tc_map = 0;
0802 
0803     if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state) ||
0804         !type->tc_param_valid)
0805         return;
0806 
0807     if (tc < 0 || (tc >= QLC_DCB_MAX_TC))
0808         return;
0809 
0810     tc_cfg = &type->tc_cfg[tc];
0811     if (!tc_cfg->valid)
0812         return;
0813 
0814     *pgid = tc_cfg->pgid;
0815     *prio = tc_cfg->prio_type;
0816     *up_tc_map = tc_cfg->up_tc_map;
0817     pg = *pgid;
0818 
0819     for (i = 0, cnt = 0; i < QLC_DCB_MAX_TC; i++) {
0820         temp = &type->tc_cfg[i];
0821         if (temp->valid && (pg == temp->pgid))
0822             cnt++;
0823     }
0824 
0825     tc_cfg->bwg_percent = (100 / cnt);
0826     *bw_per = tc_cfg->bwg_percent;
0827 }
0828 
0829 static void qlcnic_dcb_get_pg_bwg_cfg_tx(struct net_device *netdev, int pgid,
0830                      u8 *bw_pct)
0831 {
0832     struct qlcnic_adapter *adapter = netdev_priv(netdev);
0833     struct qlcnic_dcb_pg_cfg *pgcfg;
0834     struct qlcnic_dcb_cee *type;
0835 
0836     *bw_pct = 0;
0837     type = &adapter->dcb->cfg->type[QLC_DCB_OPER_IDX];
0838 
0839     if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state) ||
0840         !type->tc_param_valid)
0841         return;
0842 
0843     if (pgid < 0 || pgid >= QLC_DCB_MAX_PG)
0844         return;
0845 
0846     pgcfg = &type->pg_cfg[pgid];
0847     if (!pgcfg->valid)
0848         return;
0849 
0850     *bw_pct = pgcfg->total_bw_percent;
0851 }
0852 
0853 static void qlcnic_dcb_get_pfc_cfg(struct net_device *netdev, int prio,
0854                    u8 *setting)
0855 {
0856     struct qlcnic_adapter *adapter = netdev_priv(netdev);
0857     struct qlcnic_dcb_tc_cfg *tc_cfg;
0858     u8 val = QLC_DCB_GET_MAP(prio);
0859     struct qlcnic_dcb_cee *type;
0860     u8 i;
0861 
0862     *setting = 0;
0863     type = &adapter->dcb->cfg->type[QLC_DCB_OPER_IDX];
0864 
0865     if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state) ||
0866         !type->pfc_mode_enable)
0867         return;
0868 
0869     for (i = 0; i < QLC_DCB_MAX_TC; i++) {
0870         tc_cfg = &type->tc_cfg[i];
0871         if (!tc_cfg->valid)
0872             continue;
0873 
0874         if ((val & tc_cfg->up_tc_map) && (tc_cfg->prio_cfg[prio].valid))
0875             *setting = tc_cfg->prio_cfg[prio].pfc_type;
0876     }
0877 }
0878 
0879 static u8 qlcnic_dcb_get_capability(struct net_device *netdev, int capid,
0880                     u8 *cap)
0881 {
0882     struct qlcnic_adapter *adapter = netdev_priv(netdev);
0883 
0884     if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
0885         return 1;
0886 
0887     switch (capid) {
0888     case DCB_CAP_ATTR_PG:
0889     case DCB_CAP_ATTR_UP2TC:
0890     case DCB_CAP_ATTR_PFC:
0891     case DCB_CAP_ATTR_GSP:
0892         *cap = true;
0893         break;
0894     case DCB_CAP_ATTR_PG_TCS:
0895     case DCB_CAP_ATTR_PFC_TCS:
0896         *cap = 0x80;    /* 8 priorities for PGs */
0897         break;
0898     case DCB_CAP_ATTR_DCBX:
0899         *cap = adapter->dcb->cfg->capability.dcb_capability;
0900         break;
0901     default:
0902         *cap = false;
0903     }
0904 
0905     return 0;
0906 }
0907 
0908 static int qlcnic_dcb_get_num_tcs(struct net_device *netdev, int attr, u8 *num)
0909 {
0910     struct qlcnic_adapter *adapter = netdev_priv(netdev);
0911     struct qlcnic_dcb_cfg *cfg = adapter->dcb->cfg;
0912 
0913     if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
0914         return -EINVAL;
0915 
0916     switch (attr) {
0917     case DCB_NUMTCS_ATTR_PG:
0918         *num = cfg->capability.max_ets_tc;
0919         return 0;
0920     case DCB_NUMTCS_ATTR_PFC:
0921         *num = cfg->capability.max_pfc_tc;
0922         return 0;
0923     default:
0924         return -EINVAL;
0925     }
0926 }
0927 
0928 static int qlcnic_dcb_get_app(struct net_device *netdev, u8 idtype, u16 id)
0929 {
0930     struct qlcnic_adapter *adapter = netdev_priv(netdev);
0931     struct dcb_app app = {
0932                 .selector = idtype,
0933                 .protocol = id,
0934                  };
0935 
0936     if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
0937         return -EINVAL;
0938 
0939     return dcb_getapp(netdev, &app);
0940 }
0941 
0942 static u8 qlcnic_dcb_get_pfc_state(struct net_device *netdev)
0943 {
0944     struct qlcnic_adapter *adapter = netdev_priv(netdev);
0945     struct qlcnic_dcb *dcb = adapter->dcb;
0946 
0947     if (!test_bit(QLCNIC_DCB_STATE, &dcb->state))
0948         return 0;
0949 
0950     return dcb->cfg->type[QLC_DCB_OPER_IDX].pfc_mode_enable;
0951 }
0952 
0953 static u8 qlcnic_dcb_get_dcbx(struct net_device *netdev)
0954 {
0955     struct qlcnic_adapter *adapter = netdev_priv(netdev);
0956     struct qlcnic_dcb_cfg *cfg = adapter->dcb->cfg;
0957 
0958     if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
0959         return 0;
0960 
0961     return cfg->capability.dcb_capability;
0962 }
0963 
0964 static u8 qlcnic_dcb_get_feat_cfg(struct net_device *netdev, int fid, u8 *flag)
0965 {
0966     struct qlcnic_adapter *adapter = netdev_priv(netdev);
0967     struct qlcnic_dcb_cee *type;
0968 
0969     if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
0970         return 1;
0971 
0972     type = &adapter->dcb->cfg->type[QLC_DCB_OPER_IDX];
0973     *flag = 0;
0974 
0975     switch (fid) {
0976     case DCB_FEATCFG_ATTR_PG:
0977         if (type->tc_param_valid)
0978             *flag |= DCB_FEATCFG_ENABLE;
0979         else
0980             *flag |= DCB_FEATCFG_ERROR;
0981         break;
0982     case DCB_FEATCFG_ATTR_PFC:
0983         if (type->pfc_mode_enable) {
0984             if (type->tc_cfg[0].prio_cfg[0].pfc_type)
0985                 *flag |= DCB_FEATCFG_ENABLE;
0986         } else {
0987             *flag |= DCB_FEATCFG_ERROR;
0988         }
0989         break;
0990     case DCB_FEATCFG_ATTR_APP:
0991         *flag |= DCB_FEATCFG_ENABLE;
0992         break;
0993     default:
0994         netdev_err(netdev, "Invalid Feature ID %d\n", fid);
0995         return 1;
0996     }
0997 
0998     return 0;
0999 }
1000 
1001 static inline void
1002 qlcnic_dcb_get_pg_tc_cfg_rx(struct net_device *netdev, int prio, u8 *prio_type,
1003                 u8 *pgid, u8 *bw_pct, u8 *up_map)
1004 {
1005     *prio_type = *pgid = *bw_pct = *up_map = 0;
1006 }
1007 
1008 static inline void
1009 qlcnic_dcb_get_pg_bwg_cfg_rx(struct net_device *netdev, int pgid, u8 *bw_pct)
1010 {
1011     *bw_pct = 0;
1012 }
1013 
1014 static int qlcnic_dcb_peer_app_info(struct net_device *netdev,
1015                     struct dcb_peer_app_info *info,
1016                     u16 *app_count)
1017 {
1018     struct qlcnic_adapter *adapter = netdev_priv(netdev);
1019     struct qlcnic_dcb_cee *peer;
1020     int i;
1021 
1022     memset(info, 0, sizeof(*info));
1023     *app_count = 0;
1024 
1025     if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
1026         return 0;
1027 
1028     peer = &adapter->dcb->cfg->type[QLC_DCB_PEER_IDX];
1029 
1030     for (i = 0; i < QLC_DCB_MAX_APP; i++) {
1031         if (peer->app[i].valid)
1032             (*app_count)++;
1033     }
1034 
1035     return 0;
1036 }
1037 
1038 static int qlcnic_dcb_peer_app_table(struct net_device *netdev,
1039                      struct dcb_app *table)
1040 {
1041     struct qlcnic_adapter *adapter = netdev_priv(netdev);
1042     struct qlcnic_dcb_cee *peer;
1043     struct qlcnic_dcb_app *app;
1044     int i, j;
1045 
1046     if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
1047         return 0;
1048 
1049     peer = &adapter->dcb->cfg->type[QLC_DCB_PEER_IDX];
1050 
1051     for (i = 0, j = 0; i < QLC_DCB_MAX_APP; i++) {
1052         app = &peer->app[i];
1053         if (!app->valid)
1054             continue;
1055 
1056         table[j].selector = app->selector;
1057         table[j].priority = app->priority;
1058         table[j++].protocol = app->protocol;
1059     }
1060 
1061     return 0;
1062 }
1063 
1064 static int qlcnic_dcb_cee_peer_get_pg(struct net_device *netdev,
1065                       struct cee_pg *pg)
1066 {
1067     struct qlcnic_adapter *adapter = netdev_priv(netdev);
1068     struct qlcnic_dcb_cee *peer;
1069     u8 i, j, k, map;
1070 
1071     if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
1072         return 0;
1073 
1074     peer = &adapter->dcb->cfg->type[QLC_DCB_PEER_IDX];
1075 
1076     for (i = 0, j = 0; i < QLC_DCB_MAX_PG; i++) {
1077         if (!peer->pg_cfg[i].valid)
1078             continue;
1079 
1080         pg->pg_bw[j] = peer->pg_cfg[i].total_bw_percent;
1081 
1082         for (k = 0; k < QLC_DCB_MAX_TC; k++) {
1083             if (peer->tc_cfg[i].valid &&
1084                 (peer->tc_cfg[i].pgid == i)) {
1085                 map = peer->tc_cfg[i].up_tc_map;
1086                 pg->prio_pg[j++] = map;
1087                 break;
1088             }
1089         }
1090     }
1091 
1092     return 0;
1093 }
1094 
1095 static int qlcnic_dcb_cee_peer_get_pfc(struct net_device *netdev,
1096                        struct cee_pfc *pfc)
1097 {
1098     struct qlcnic_adapter *adapter = netdev_priv(netdev);
1099     struct qlcnic_dcb_cfg *cfg = adapter->dcb->cfg;
1100     struct qlcnic_dcb_tc_cfg *tc;
1101     struct qlcnic_dcb_cee *peer;
1102     u8 i, setting, prio;
1103 
1104     pfc->pfc_en = 0;
1105 
1106     if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
1107         return 0;
1108 
1109     peer = &cfg->type[QLC_DCB_PEER_IDX];
1110 
1111     for (i = 0; i < QLC_DCB_MAX_TC; i++) {
1112         tc = &peer->tc_cfg[i];
1113         prio = qlcnic_dcb_prio_count(tc->up_tc_map);
1114 
1115         setting = 0;
1116         qlcnic_dcb_get_pfc_cfg(netdev, prio, &setting);
1117         if (setting)
1118             pfc->pfc_en |= QLC_DCB_GET_MAP(i);
1119     }
1120 
1121     pfc->tcs_supported = cfg->capability.max_pfc_tc;
1122 
1123     return 0;
1124 }
1125 
1126 static const struct dcbnl_rtnl_ops qlcnic_dcbnl_ops = {
1127     .getstate       = qlcnic_dcb_get_state,
1128     .getpermhwaddr      = qlcnic_dcb_get_perm_hw_addr,
1129     .getpgtccfgtx       = qlcnic_dcb_get_pg_tc_cfg_tx,
1130     .getpgbwgcfgtx      = qlcnic_dcb_get_pg_bwg_cfg_tx,
1131     .getpfccfg      = qlcnic_dcb_get_pfc_cfg,
1132     .getcap         = qlcnic_dcb_get_capability,
1133     .getnumtcs      = qlcnic_dcb_get_num_tcs,
1134     .getapp         = qlcnic_dcb_get_app,
1135     .getpfcstate        = qlcnic_dcb_get_pfc_state,
1136     .getdcbx        = qlcnic_dcb_get_dcbx,
1137     .getfeatcfg     = qlcnic_dcb_get_feat_cfg,
1138 
1139     .getpgtccfgrx       = qlcnic_dcb_get_pg_tc_cfg_rx,
1140     .getpgbwgcfgrx      = qlcnic_dcb_get_pg_bwg_cfg_rx,
1141 
1142     .peer_getappinfo    = qlcnic_dcb_peer_app_info,
1143     .peer_getapptable   = qlcnic_dcb_peer_app_table,
1144     .cee_peer_getpg     = qlcnic_dcb_cee_peer_get_pg,
1145     .cee_peer_getpfc    = qlcnic_dcb_cee_peer_get_pfc,
1146 };
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