Back to home page

OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * QLogic qlcnic NIC Driver
0004  * Copyright (c) 2009-2013 QLogic Corporation
0005  */
0006 
0007 #ifndef __QLCNIC_83XX_HW_H
0008 #define __QLCNIC_83XX_HW_H
0009 
0010 #include <linux/types.h>
0011 #include <linux/etherdevice.h>
0012 
0013 #include "qlcnic_hw.h"
0014 
0015 #define QLCNIC_83XX_BAR0_LENGTH 0x4000
0016 
0017 /* Directly mapped registers */
0018 #define QLC_83XX_CRB_WIN_BASE       0x3800
0019 #define QLC_83XX_CRB_WIN_FUNC(f)    (QLC_83XX_CRB_WIN_BASE+((f)*4))
0020 #define QLC_83XX_SEM_LOCK_BASE      0x3840
0021 #define QLC_83XX_SEM_UNLOCK_BASE    0x3844
0022 #define QLC_83XX_SEM_LOCK_FUNC(f)   (QLC_83XX_SEM_LOCK_BASE+((f)*8))
0023 #define QLC_83XX_SEM_UNLOCK_FUNC(f) (QLC_83XX_SEM_UNLOCK_BASE+((f)*8))
0024 #define QLC_83XX_LINK_STATE(f)      (0x3698+((f) > 7 ? 4 : 0))
0025 #define QLC_83XX_LINK_SPEED(f)      (0x36E0+(((f) >> 2) * 4))
0026 #define QLC_83XX_LINK_SPEED_FACTOR  10
0027 #define QLC_83xx_FUNC_VAL(v, f) ((v) & (1 << (f * 4)))
0028 #define QLC_83XX_INTX_PTR       0x38C0
0029 #define QLC_83XX_INTX_TRGR      0x38C4
0030 #define QLC_83XX_INTX_MASK      0x38C8
0031 
0032 #define QLC_83XX_DRV_LOCK_WAIT_COUNTER          100
0033 #define QLC_83XX_DRV_LOCK_WAIT_DELAY            20
0034 #define QLC_83XX_NEED_DRV_LOCK_RECOVERY     1
0035 #define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS      2
0036 #define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT      3
0037 #define QLC_83XX_DRV_LOCK_RECOVERY_DELAY        200
0038 #define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK      0x3
0039 #define QLC_83XX_LB_WAIT_COUNT              250
0040 #define QLC_83XX_LB_MSLEEP_COUNT            20
0041 #define QLC_83XX_NO_NIC_RESOURCE    0x5
0042 #define QLC_83XX_MAC_PRESENT        0xC
0043 #define QLC_83XX_MAC_ABSENT     0xD
0044 
0045 
0046 #define QLC_83XX_FLASH_SECTOR_SIZE      (64 * 1024)
0047 
0048 /* PEG status definitions */
0049 #define QLC_83XX_CMDPEG_COMPLETE        0xff01
0050 #define QLC_83XX_VALID_INTX_BIT30(val)      ((val) & BIT_30)
0051 #define QLC_83XX_VALID_INTX_BIT31(val)      ((val) & BIT_31)
0052 #define QLC_83XX_INTX_FUNC(val)     ((val) & 0xFF)
0053 #define QLC_83XX_LEGACY_INTX_MAX_RETRY      100
0054 #define QLC_83XX_LEGACY_INTX_DELAY      4
0055 #define QLC_83XX_REG_DESC           1
0056 #define QLC_83XX_LRO_DESC           2
0057 #define QLC_83XX_CTRL_DESC          3
0058 #define QLC_83XX_FW_CAPABILITY_TSO      BIT_6
0059 #define QLC_83XX_FW_CAP_LRO_MSS     BIT_17
0060 #define QLC_83XX_HOST_RDS_MODE_UNIQUE       0
0061 #define QLC_83XX_HOST_SDS_MBX_IDX       8
0062 
0063 #define QLCNIC_HOST_RDS_MBX_IDX         88
0064 
0065 /* Pause control registers */
0066 #define QLC_83XX_SRE_SHIM_REG       0x0D200284
0067 #define QLC_83XX_PORT0_THRESHOLD    0x0B2003A4
0068 #define QLC_83XX_PORT1_THRESHOLD    0x0B2013A4
0069 #define QLC_83XX_PORT0_TC_MC_REG    0x0B200388
0070 #define QLC_83XX_PORT1_TC_MC_REG    0x0B201388
0071 #define QLC_83XX_PORT0_TC_STATS     0x0B20039C
0072 #define QLC_83XX_PORT1_TC_STATS     0x0B20139C
0073 #define QLC_83XX_PORT2_IFB_THRESHOLD    0x0B200704
0074 #define QLC_83XX_PORT3_IFB_THRESHOLD    0x0B201704
0075 
0076 /* Peg PC status registers */
0077 #define QLC_83XX_CRB_PEG_NET_0      0x3400003c
0078 #define QLC_83XX_CRB_PEG_NET_1      0x3410003c
0079 #define QLC_83XX_CRB_PEG_NET_2      0x3420003c
0080 #define QLC_83XX_CRB_PEG_NET_3      0x3430003c
0081 #define QLC_83XX_CRB_PEG_NET_4      0x34b0003c
0082 
0083 /* Firmware image definitions */
0084 #define QLC_83XX_BOOTLOADER_FLASH_ADDR  0x10000
0085 #define QLC_83XX_FW_FILE_NAME       "83xx_fw.bin"
0086 #define QLC_83XX_POST_FW_FILE_NAME  "83xx_post_fw.bin"
0087 #define QLC_84XX_FW_FILE_NAME       "84xx_fw.bin"
0088 #define QLC_83XX_BOOT_FROM_FLASH    0
0089 #define QLC_83XX_BOOT_FROM_FILE     0x12345678
0090 
0091 #define QLC_FW_FILE_NAME_LEN        20
0092 #define QLC_83XX_MAX_RESET_SEQ_ENTRIES  16
0093 
0094 #define QLC_83XX_MBX_POST_BC_OP     0x1
0095 #define QLC_83XX_MBX_COMPLETION     0x0
0096 #define QLC_83XX_MBX_REQUEST        0x1
0097 
0098 #define QLC_83XX_MBX_TIMEOUT        (5 * HZ)
0099 #define QLC_83XX_MBX_CMD_LOOP       5000000
0100 
0101 /* status descriptor mailbox data
0102  * @phy_addr_{low|high}: physical address of buffer
0103  * @sds_ring_size: buffer size
0104  * @intrpt_id: interrupt id
0105  * @intrpt_val: source of interrupt
0106  */
0107 struct qlcnic_sds_mbx {
0108     u32 phy_addr_low;
0109     u32 phy_addr_high;
0110     u32 rsvd1[4];
0111 #if defined(__LITTLE_ENDIAN)
0112     u16 sds_ring_size;
0113     u16 rsvd2;
0114     u16 rsvd3[2];
0115     u16 intrpt_id;
0116     u8  intrpt_val;
0117     u8  rsvd4;
0118 #elif defined(__BIG_ENDIAN)
0119     u16 rsvd2;
0120     u16 sds_ring_size;
0121     u16 rsvd3[2];
0122     u8  rsvd4;
0123     u8  intrpt_val;
0124     u16 intrpt_id;
0125 #endif
0126     u32 rsvd5;
0127 } __packed;
0128 
0129 /* receive descriptor buffer data
0130  * phy_addr_reg_{low|high}: physical address of regular buffer
0131  * phy_addr_jmb_{low|high}: physical address of jumbo buffer
0132  * reg_ring_sz: size of regular buffer
0133  * reg_ring_len: no. of entries in regular buffer
0134  * jmb_ring_len: no. of entries in jumbo buffer
0135  * jmb_ring_sz: size of jumbo buffer
0136  */
0137 struct qlcnic_rds_mbx {
0138     u32 phy_addr_reg_low;
0139     u32 phy_addr_reg_high;
0140     u32 phy_addr_jmb_low;
0141     u32 phy_addr_jmb_high;
0142 #if defined(__LITTLE_ENDIAN)
0143     u16 reg_ring_sz;
0144     u16 reg_ring_len;
0145     u16 jmb_ring_sz;
0146     u16 jmb_ring_len;
0147 #elif defined(__BIG_ENDIAN)
0148     u16 reg_ring_len;
0149     u16 reg_ring_sz;
0150     u16 jmb_ring_len;
0151     u16 jmb_ring_sz;
0152 #endif
0153 } __packed;
0154 
0155 /* host producers for regular and jumbo rings */
0156 struct __host_producer_mbx {
0157     u32 reg_buf;
0158     u32 jmb_buf;
0159 } __packed;
0160 
0161 /* Receive context mailbox data outbox registers
0162  * @state: state of the context
0163  * @vport_id: virtual port id
0164  * @context_id: receive context id
0165  * @num_pci_func: number of pci functions of the port
0166  * @phy_port: physical port id
0167  */
0168 struct qlcnic_rcv_mbx_out {
0169 #if defined(__LITTLE_ENDIAN)
0170     u8  rcv_num;
0171     u8  sts_num;
0172     u16 ctx_id;
0173     u8  state;
0174     u8  num_pci_func;
0175     u8  phy_port;
0176     u8  vport_id;
0177 #elif defined(__BIG_ENDIAN)
0178     u16 ctx_id;
0179     u8  sts_num;
0180     u8  rcv_num;
0181     u8  vport_id;
0182     u8  phy_port;
0183     u8  num_pci_func;
0184     u8  state;
0185 #endif
0186     u32 host_csmr[QLCNIC_MAX_SDS_RINGS];
0187     struct __host_producer_mbx host_prod[QLCNIC_MAX_SDS_RINGS];
0188 } __packed;
0189 
0190 struct qlcnic_add_rings_mbx_out {
0191 #if defined(__LITTLE_ENDIAN)
0192     u8      rcv_num;
0193     u8      sts_num;
0194     u16 ctx_id;
0195 #elif defined(__BIG_ENDIAN)
0196     u16 ctx_id;
0197     u8  sts_num;
0198     u8  rcv_num;
0199 #endif
0200     u32  host_csmr[QLCNIC_MAX_SDS_RINGS];
0201     struct __host_producer_mbx host_prod[QLCNIC_MAX_SDS_RINGS];
0202 } __packed;
0203 
0204 /* Transmit context mailbox inbox registers
0205  * @phys_addr_{low|high}: DMA address of the transmit buffer
0206  * @cnsmr_index_{low|high}: host consumer index
0207  * @size: legth of transmit buffer ring
0208  * @intr_id: interrupt id
0209  * @src: src of interrupt
0210  */
0211 struct qlcnic_tx_mbx {
0212     u32 phys_addr_low;
0213     u32 phys_addr_high;
0214     u32 cnsmr_index_low;
0215     u32 cnsmr_index_high;
0216 #if defined(__LITTLE_ENDIAN)
0217     u16 size;
0218     u16 intr_id;
0219     u8  src;
0220     u8  rsvd[3];
0221 #elif defined(__BIG_ENDIAN)
0222     u16 intr_id;
0223     u16 size;
0224     u8  rsvd[3];
0225     u8  src;
0226 #endif
0227 } __packed;
0228 
0229 /* Transmit context mailbox outbox registers
0230  * @host_prod: host producer index
0231  * @ctx_id: transmit context id
0232  * @state: state of the transmit context
0233  */
0234 
0235 struct qlcnic_tx_mbx_out {
0236     u32 host_prod;
0237 #if defined(__LITTLE_ENDIAN)
0238     u16 ctx_id;
0239     u8  state;
0240     u8  rsvd;
0241 #elif defined(__BIG_ENDIAN)
0242     u8  rsvd;
0243     u8  state;
0244     u16 ctx_id;
0245 #endif
0246 } __packed;
0247 
0248 struct qlcnic_intrpt_config {
0249     u8  type;
0250     u8  enabled;
0251     u16 id;
0252     u32 src;
0253 };
0254 
0255 struct qlcnic_macvlan_mbx {
0256 #if defined(__LITTLE_ENDIAN)
0257     u8  mac_addr0;
0258     u8  mac_addr1;
0259     u8  mac_addr2;
0260     u8  mac_addr3;
0261     u8  mac_addr4;
0262     u8  mac_addr5;
0263     u16 vlan;
0264 #elif defined(__BIG_ENDIAN)
0265     u8  mac_addr3;
0266     u8  mac_addr2;
0267     u8  mac_addr1;
0268     u8  mac_addr0;
0269     u16 vlan;
0270     u8  mac_addr5;
0271     u8  mac_addr4;
0272 #endif
0273 };
0274 
0275 struct qlc_83xx_fw_info {
0276     const struct firmware   *fw;
0277     char    fw_file_name[QLC_FW_FILE_NAME_LEN];
0278 };
0279 
0280 struct qlc_83xx_reset {
0281     struct qlc_83xx_reset_hdr *hdr;
0282     int seq_index;
0283     int seq_error;
0284     int array_index;
0285     u32 array[QLC_83XX_MAX_RESET_SEQ_ENTRIES];
0286     u8  *buff;
0287     u8  *stop_offset;
0288     u8  *start_offset;
0289     u8  *init_offset;
0290     u8  seq_end;
0291     u8  template_end;
0292 };
0293 
0294 #define QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY      0x1
0295 #define QLC_83XX_IDC_GRACEFULL_RESET            0x2
0296 #define QLC_83XX_IDC_DISABLE_FW_DUMP            0x4
0297 #define QLC_83XX_IDC_TIMESTAMP              0
0298 #define QLC_83XX_IDC_DURATION               1
0299 #define QLC_83XX_IDC_INIT_TIMEOUT_SECS          30
0300 #define QLC_83XX_IDC_RESET_ACK_TIMEOUT_SECS     10
0301 #define QLC_83XX_IDC_RESET_TIMEOUT_SECS     10
0302 #define QLC_83XX_IDC_QUIESCE_ACK_TIMEOUT_SECS       20
0303 #define QLC_83XX_IDC_FW_POLL_DELAY          (1 * HZ)
0304 #define QLC_83XX_IDC_FW_FAIL_THRESH         2
0305 #define QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO    8
0306 #define QLC_83XX_IDC_MAX_CNA_FUNCTIONS          16
0307 #define QLC_83XX_IDC_MAJOR_VERSION          1
0308 #define QLC_83XX_IDC_MINOR_VERSION          0
0309 #define QLC_83XX_IDC_FLASH_PARAM_ADDR           0x3e8020
0310 
0311 struct qlcnic_adapter;
0312 struct qlcnic_fw_dump;
0313 
0314 struct qlc_83xx_idc {
0315     int (*state_entry) (struct qlcnic_adapter *);
0316     u64     sec_counter;
0317     u64     delay;
0318     unsigned long   status;
0319     int     err_code;
0320     int     collect_dump;
0321     u8      curr_state;
0322     u8      prev_state;
0323     u8      vnic_state;
0324     u8      vnic_wait_limit;
0325     u8      quiesce_req;
0326     u8      delay_reset;
0327     char        **name;
0328 };
0329 
0330 enum qlcnic_vlan_operations {
0331     QLC_VLAN_ADD = 0,
0332     QLC_VLAN_DELETE
0333 };
0334 
0335 /* Device States */
0336 enum qlcnic_83xx_states {
0337     QLC_83XX_IDC_DEV_UNKNOWN,
0338     QLC_83XX_IDC_DEV_COLD,
0339     QLC_83XX_IDC_DEV_INIT,
0340     QLC_83XX_IDC_DEV_READY,
0341     QLC_83XX_IDC_DEV_NEED_RESET,
0342     QLC_83XX_IDC_DEV_NEED_QUISCENT,
0343     QLC_83XX_IDC_DEV_FAILED,
0344     QLC_83XX_IDC_DEV_QUISCENT
0345 };
0346 
0347 #define QLCNIC_MBX_RSP(reg)     LSW(reg)
0348 #define QLCNIC_MBX_NUM_REGS(reg)    (MSW(reg) & 0x1FF)
0349 #define QLCNIC_MBX_STATUS(reg)      (((reg) >> 25) & 0x7F)
0350 #define QLCNIC_MBX_HOST(ahw, i) ((ahw)->pci_base0 + ((i) * 4))
0351 #define QLCNIC_MBX_FW(ahw, i)       ((ahw)->pci_base0 + 0x800 + ((i) * 4))
0352 
0353 /* Mailbox process AEN count */
0354 #define QLC_83XX_IDC_COMP_AEN           3
0355 #define QLC_83XX_MBX_AEN_CNT            5
0356 #define QLC_83XX_MODULE_LOADED          1
0357 #define QLC_83XX_MBX_READY          2
0358 #define QLC_83XX_MBX_AEN_ACK            3
0359 #define QLC_83XX_SFP_PRESENT(data)      ((data) & 3)
0360 #define QLC_83XX_SFP_ERR(data)          (((data) >> 2) & 3)
0361 #define QLC_83XX_SFP_MODULE_TYPE(data)      (((data) >> 4) & 0x1F)
0362 #define QLC_83XX_SFP_CU_LENGTH(data)        (LSB((data) >> 16))
0363 #define QLC_83XX_SFP_TX_FAULT(data)     ((data) & BIT_10)
0364 #define QLC_83XX_LINK_STATS(data)       ((data) & BIT_0)
0365 #define QLC_83XX_CURRENT_LINK_SPEED(data)   (((data) >> 3) & 7)
0366 #define QLC_83XX_LINK_PAUSE(data)       (((data) >> 6) & 3)
0367 #define QLC_83XX_LINK_LB(data)          (((data) >> 8) & 7)
0368 #define QLC_83XX_LINK_FEC(data)     ((data) & BIT_12)
0369 #define QLC_83XX_LINK_EEE(data)     ((data) & BIT_13)
0370 #define QLC_83XX_DCBX(data)         (((data) >> 28) & 7)
0371 #define QLC_83XX_AUTONEG(data)          ((data) & BIT_15)
0372 #define QLC_83XX_TX_PAUSE           0x10
0373 #define QLC_83XX_RX_PAUSE           0x20
0374 #define QLC_83XX_TX_RX_PAUSE            0x30
0375 #define QLC_83XX_CFG_STD_PAUSE          (1 << 5)
0376 #define QLC_83XX_CFG_STD_TX_PAUSE       (1 << 20)
0377 #define QLC_83XX_CFG_STD_RX_PAUSE       (2 << 20)
0378 #define QLC_83XX_CFG_STD_TX_RX_PAUSE        (3 << 20)
0379 #define QLC_83XX_ENABLE_AUTONEG     (1 << 15)
0380 #define QLC_83XX_CFG_LOOPBACK_HSS       (2 << 1)
0381 #define QLC_83XX_CFG_LOOPBACK_PHY       (3 << 1)
0382 #define QLC_83XX_CFG_LOOPBACK_EXT       (4 << 1)
0383 
0384 /* LED configuration settings */
0385 #define QLC_83XX_ENABLE_BEACON      0xe
0386 #define QLC_83XX_BEACON_ON      1
0387 #define QLC_83XX_BEACON_OFF     0
0388 #define QLC_83XX_LED_RATE       0xff
0389 #define QLC_83XX_LED_ACT        (1 << 10)
0390 #define QLC_83XX_LED_MOD        (0 << 13)
0391 #define QLC_83XX_LED_CONFIG (QLC_83XX_LED_RATE | QLC_83XX_LED_ACT | \
0392                  QLC_83XX_LED_MOD)
0393 
0394 #define QLC_83XX_10M_LINK   1
0395 #define QLC_83XX_100M_LINK  2
0396 #define QLC_83XX_1G_LINK    3
0397 #define QLC_83XX_10G_LINK   4
0398 #define QLC_83XX_STAT_TX    3
0399 #define QLC_83XX_STAT_RX    2
0400 #define QLC_83XX_STAT_MAC   1
0401 #define QLC_83XX_TX_STAT_REGS   14
0402 #define QLC_83XX_RX_STAT_REGS   40
0403 #define QLC_83XX_MAC_STAT_REGS  94
0404 
0405 #define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN)    (0x3 & ((VAL) >> (FN * 2)))
0406 #define QLC_83XX_SET_FUNC_OPMODE(VAL, FN)   ((VAL) << (FN * 2))
0407 #define QLC_83XX_DEFAULT_OPMODE         0x55555555
0408 #define QLC_83XX_PRIVLEGED_FUNC         0x1
0409 #define QLC_83XX_VIRTUAL_FUNC               0x2
0410 
0411 #define QLC_83XX_LB_MAX_FILTERS         2048
0412 #define QLC_83XX_LB_BUCKET_SIZE         256
0413 #define QLC_83XX_MINIMUM_VECTOR         3
0414 #define QLC_83XX_MAX_MC_COUNT           38
0415 #define QLC_83XX_MAX_UC_COUNT           4096
0416 
0417 #define QLC_83XX_PVID_STRIP_CAPABILITY      BIT_22
0418 #define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val)  (val & 0x80000000)
0419 #define QLC_83XX_GET_LRO_CAPABILITY(val)        (val & 0x20)
0420 #define QLC_83XX_GET_LSO_CAPABILITY(val)        (val & 0x40)
0421 #define QLC_83XX_GET_HW_LRO_CAPABILITY(val)     (val & 0x400)
0422 #define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val) (val & 0x4000)
0423 #define QLC_83XX_GET_FW_LRO_MSS_CAPABILITY(val) (val & 0x20000)
0424 #define QLC_83XX_ESWITCH_CAPABILITY         BIT_23
0425 #define QLC_83XX_SRIOV_MODE             0x1
0426 #define QLCNIC_BRDTYPE_83XX_10G         0x0083
0427 
0428 #define QLC_83XX_FLASH_SPI_STATUS       0x2808E010
0429 #define QLC_83XX_FLASH_SPI_CONTROL      0x2808E014
0430 #define QLC_83XX_FLASH_STATUS           0x42100004
0431 #define QLC_83XX_FLASH_CONTROL          0x42110004
0432 #define QLC_83XX_FLASH_ADDR         0x42110008
0433 #define QLC_83XX_FLASH_WRDATA           0x4211000C
0434 #define QLC_83XX_FLASH_RDDATA           0x42110018
0435 #define QLC_83XX_FLASH_DIRECT_WINDOW        0x42110030
0436 #define QLC_83XX_FLASH_DIRECT_DATA(DATA)    (0x42150000 | (0x0000FFFF&DATA))
0437 #define QLC_83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
0438 #define QLC_83XX_FLASH_WRITE_CMD        0xdacdacda
0439 #define QLC_83XX_FLASH_BULK_WRITE_CMD       0xcadcadca
0440 #define QLC_83XX_FLASH_READ_RETRY_COUNT 5000
0441 #define QLC_83XX_FLASH_STATUS_READY     0x6
0442 #define QLC_83XX_FLASH_WRITE_MIN        2
0443 #define QLC_83XX_FLASH_WRITE_MAX        64
0444 #define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY    1
0445 #define QLC_83XX_ERASE_MODE         1
0446 #define QLC_83XX_WRITE_MODE         2
0447 #define QLC_83XX_BULK_WRITE_MODE        3
0448 #define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG    0xFD0100
0449 #define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG    0xFD0300
0450 #define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL  0xFD009F
0451 #define QLC_83XX_FLASH_OEM_ERASE_SIG        0xFD03D8
0452 #define QLC_83XX_FLASH_OEM_WRITE_SIG        0xFD0101
0453 #define QLC_83XX_FLASH_OEM_READ_SIG     0xFD0005
0454 #define QLC_83XX_FLASH_ADDR_TEMP_VAL        0x00800000
0455 #define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL 0x00800001
0456 #define QLC_83XX_FLASH_WRDATA_DEF       0x0
0457 #define QLC_83XX_FLASH_READ_CTRL        0x3F
0458 #define QLC_83XX_FLASH_SPI_CTRL     0x4
0459 #define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL   0x2
0460 #define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL  0x5
0461 #define QLC_83XX_FLASH_LAST_ERASE_MS_VAL    0x3D
0462 #define QLC_83XX_FLASH_FIRST_MS_PATTERN 0x43
0463 #define QLC_83XX_FLASH_SECOND_MS_PATTERN    0x7F
0464 #define QLC_83XX_FLASH_LAST_MS_PATTERN      0x7D
0465 #define QLC_83xx_FLASH_MAX_WAIT_USEC        100
0466 #define QLC_83XX_FLASH_LOCK_TIMEOUT     10000
0467 
0468 enum qlc_83xx_mbx_cmd_type {
0469     QLC_83XX_MBX_CMD_WAIT = 0,
0470     QLC_83XX_MBX_CMD_NO_WAIT,
0471     QLC_83XX_MBX_CMD_BUSY_WAIT,
0472 };
0473 
0474 enum qlc_83xx_mbx_response_states {
0475     QLC_83XX_MBX_RESPONSE_WAIT = 0,
0476     QLC_83XX_MBX_RESPONSE_ARRIVED,
0477 };
0478 
0479 #define QLC_83XX_MBX_RESPONSE_FAILED    0x2
0480 #define QLC_83XX_MBX_RESPONSE_UNKNOWN   0x3
0481 
0482 /* Additional registers in 83xx */
0483 enum qlc_83xx_ext_regs {
0484     QLCNIC_GLOBAL_RESET = 0,
0485     QLCNIC_WILDCARD,
0486     QLCNIC_INFORMANT,
0487     QLCNIC_HOST_MBX_CTRL,
0488     QLCNIC_FW_MBX_CTRL,
0489     QLCNIC_BOOTLOADER_ADDR,
0490     QLCNIC_BOOTLOADER_SIZE,
0491     QLCNIC_FW_IMAGE_ADDR,
0492     QLCNIC_MBX_INTR_ENBL,
0493     QLCNIC_DEF_INT_MASK,
0494     QLCNIC_DEF_INT_ID,
0495     QLC_83XX_IDC_MAJ_VERSION,
0496     QLC_83XX_IDC_DEV_STATE,
0497     QLC_83XX_IDC_DRV_PRESENCE,
0498     QLC_83XX_IDC_DRV_ACK,
0499     QLC_83XX_IDC_CTRL,
0500     QLC_83XX_IDC_DRV_AUDIT,
0501     QLC_83XX_IDC_MIN_VERSION,
0502     QLC_83XX_RECOVER_DRV_LOCK,
0503     QLC_83XX_IDC_PF_0,
0504     QLC_83XX_IDC_PF_1,
0505     QLC_83XX_IDC_PF_2,
0506     QLC_83XX_IDC_PF_3,
0507     QLC_83XX_IDC_PF_4,
0508     QLC_83XX_IDC_PF_5,
0509     QLC_83XX_IDC_PF_6,
0510     QLC_83XX_IDC_PF_7,
0511     QLC_83XX_IDC_PF_8,
0512     QLC_83XX_IDC_PF_9,
0513     QLC_83XX_IDC_PF_10,
0514     QLC_83XX_IDC_PF_11,
0515     QLC_83XX_IDC_PF_12,
0516     QLC_83XX_IDC_PF_13,
0517     QLC_83XX_IDC_PF_14,
0518     QLC_83XX_IDC_PF_15,
0519     QLC_83XX_IDC_DEV_PARTITION_INFO_1,
0520     QLC_83XX_IDC_DEV_PARTITION_INFO_2,
0521     QLC_83XX_DRV_OP_MODE,
0522     QLC_83XX_VNIC_STATE,
0523     QLC_83XX_DRV_LOCK,
0524     QLC_83XX_DRV_UNLOCK,
0525     QLC_83XX_DRV_LOCK_ID,
0526     QLC_83XX_ASIC_TEMP,
0527 };
0528 
0529 /* Initialize/Stop NIC command bit definitions */
0530 #define QLC_REGISTER_LB_IDC     BIT_0
0531 #define QLC_REGISTER_DCB_AEN        BIT_1
0532 #define QLC_83XX_MULTI_TENANCY_INFO BIT_29
0533 #define QLC_INIT_FW_RESOURCES       BIT_31
0534 
0535 /* 83xx funcitons */
0536 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *);
0537 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *, struct qlcnic_cmd_args *);
0538 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *);
0539 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *);
0540 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *);
0541 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *);
0542 int qlcnic_send_ctrl_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *, u32);
0543 void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *);
0544 void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *);
0545 void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
0546 void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
0547 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong, int *);
0548 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32);
0549 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32);
0550 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int);
0551 int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int);
0552 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
0553                   u16 vlan, struct qlcnic_host_tx_ring *ring);
0554 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *);
0555 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
0556 void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *, int);
0557 
0558 int qlcnic_83xx_napi_add(struct qlcnic_adapter *, struct net_device *);
0559 void qlcnic_83xx_napi_del(struct qlcnic_adapter *);
0560 void qlcnic_83xx_napi_enable(struct qlcnic_adapter *);
0561 void qlcnic_83xx_napi_disable(struct qlcnic_adapter *);
0562 int qlcnic_83xx_config_led(struct qlcnic_adapter *, u32, u32);
0563 int qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32);
0564 int qlcnic_ind_rd(struct qlcnic_adapter *, u32);
0565 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *);
0566 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *,
0567                   struct qlcnic_host_tx_ring *, int);
0568 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *);
0569 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *,
0570                 struct qlcnic_host_tx_ring *);
0571 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
0572 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int);
0573 void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *);
0574 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool);
0575 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, u16, u8);
0576 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *, u8);
0577 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *,
0578                    struct qlcnic_adapter *, u32);
0579 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *);
0580 void qlcnic_set_npar_data(struct qlcnic_adapter *, const struct qlcnic_info *,
0581               struct qlcnic_info *);
0582 int qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *,
0583                  struct ethtool_coalesce *);
0584 int qlcnic_83xx_set_rx_tx_intr_coal(struct qlcnic_adapter *);
0585 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *);
0586 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *);
0587 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *);
0588 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *);
0589 irqreturn_t qlcnic_83xx_intr(int, void *);
0590 irqreturn_t qlcnic_83xx_tmp_intr(int, void *);
0591 void qlcnic_83xx_check_vf(struct qlcnic_adapter *,
0592               const struct pci_device_id *);
0593 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *);
0594 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *);
0595 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *);
0596 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *);
0597 void qlcnic_83xx_idc_aen_work(struct work_struct *);
0598 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int);
0599 
0600 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32);
0601 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int);
0602 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *);
0603 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *);
0604 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *);
0605 int qlcnic_83xx_save_flash_status(struct qlcnic_adapter *);
0606 int qlcnic_83xx_restore_flash_status(struct qlcnic_adapter *, int);
0607 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *);
0608 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *);
0609 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *, u32, u8 *, int);
0610 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *,
0611                       u32, u8 *, int);
0612 int qlcnic_83xx_init(struct qlcnic_adapter *);
0613 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *);
0614 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *);
0615 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *);
0616 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *, u32);
0617 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *);
0618 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *);
0619 int qlcnic_83xx_set_default_offload_settings(struct qlcnic_adapter *);
0620 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *);
0621 int qlcnic_83xx_disable_vnic_mode(struct qlcnic_adapter *, int);
0622 int qlcnic_83xx_config_vnic_opmode(struct qlcnic_adapter *);
0623 int qlcnic_83xx_get_vnic_vport_info(struct qlcnic_adapter *,
0624                     struct qlcnic_info *, u8);
0625 int qlcnic_83xx_get_vnic_pf_info(struct qlcnic_adapter *, struct qlcnic_info *);
0626 int qlcnic_83xx_set_port_eswitch_status(struct qlcnic_adapter *, int, int *);
0627 
0628 void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *);
0629 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data);
0630 int qlcnic_83xx_extend_md_capab(struct qlcnic_adapter *);
0631 int qlcnic_83xx_get_link_ksettings(struct qlcnic_adapter *adapter,
0632                    struct ethtool_link_ksettings *ecmd);
0633 int qlcnic_83xx_set_link_ksettings(struct qlcnic_adapter *adapter,
0634                    const struct ethtool_link_ksettings *ecmd);
0635 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *,
0636                 struct ethtool_pauseparam *);
0637 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *,
0638                    struct ethtool_pauseparam *);
0639 int qlcnic_83xx_test_link(struct qlcnic_adapter *);
0640 void qlcnic_83xx_get_port_type(struct qlcnic_adapter *adapter);
0641 int qlcnic_83xx_reg_test(struct qlcnic_adapter *);
0642 int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *);
0643 int qlcnic_83xx_get_registers(struct qlcnic_adapter *, u32 *);
0644 int qlcnic_83xx_loopback_test(struct net_device *, u8);
0645 int qlcnic_83xx_interrupt_test(struct net_device *);
0646 int qlcnic_83xx_set_led(struct net_device *, enum ethtool_phys_id_state);
0647 int qlcnic_83xx_flash_test(struct qlcnic_adapter *);
0648 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *);
0649 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *);
0650 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *);
0651 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *);
0652 int qlcnic_83xx_idc_init(struct qlcnic_adapter *);
0653 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *);
0654 int qlcnic_83xx_set_vnic_opmode(struct qlcnic_adapter *);
0655 int qlcnic_83xx_check_vnic_state(struct qlcnic_adapter *);
0656 void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *);
0657 int qlcnic_83xx_aer_reset(struct qlcnic_adapter *);
0658 void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *);
0659 u32 qlcnic_83xx_get_saved_state(void *, u32);
0660 void qlcnic_83xx_set_saved_state(void *, u32, u32);
0661 void qlcnic_83xx_cache_tmpl_hdr_values(struct qlcnic_fw_dump *);
0662 u32 qlcnic_83xx_get_cap_size(void *, int);
0663 void qlcnic_83xx_set_sys_info(void *, int, u32);
0664 void qlcnic_83xx_store_cap_mask(void *, u32);
0665 int qlcnic_ms_mem_write128(struct qlcnic_adapter *, u64, u32 *, u32);
0666 #endif
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!