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OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * QLogic QLA3xxx NIC HBA Driver
0004  * Copyright (c)  2003-2006 QLogic Corporation
0005  */
0006 #ifndef _QLA3XXX_H_
0007 #define _QLA3XXX_H_
0008 
0009 /*
0010  * IOCB Definitions...
0011  */
0012 #pragma pack(1)
0013 
0014 #define OPCODE_OB_MAC_IOCB_FN0          0x01
0015 #define OPCODE_OB_MAC_IOCB_FN2          0x21
0016 
0017 #define OPCODE_IB_MAC_IOCB          0xF9
0018 #define OPCODE_IB_3032_MAC_IOCB     0x09
0019 #define OPCODE_IB_IP_IOCB           0xFA
0020 #define OPCODE_IB_3032_IP_IOCB      0x0A
0021 
0022 #define OPCODE_FUNC_ID_MASK                 0x30
0023 #define OUTBOUND_MAC_IOCB                   0x01    /* plus function bits */
0024 
0025 #define FN0_MA_BITS_MASK    0x00
0026 #define FN1_MA_BITS_MASK    0x80
0027 
0028 struct ob_mac_iocb_req {
0029     u8 opcode;
0030     u8 flags;
0031 #define OB_MAC_IOCB_REQ_MA  0xe0
0032 #define OB_MAC_IOCB_REQ_F   0x10
0033 #define OB_MAC_IOCB_REQ_X   0x08
0034 #define OB_MAC_IOCB_REQ_D   0x02
0035 #define OB_MAC_IOCB_REQ_I   0x01
0036     u8 flags1;
0037 #define OB_3032MAC_IOCB_REQ_IC  0x04
0038 #define OB_3032MAC_IOCB_REQ_TC  0x02
0039 #define OB_3032MAC_IOCB_REQ_UC  0x01
0040     u8 reserved0;
0041 
0042     u32 transaction_id; /* opaque for hardware */
0043     __le16 data_len;
0044     u8 ip_hdr_off;
0045     u8 ip_hdr_len;
0046     __le32 reserved1;
0047     __le32 reserved2;
0048     __le32 buf_addr0_low;
0049     __le32 buf_addr0_high;
0050     __le32 buf_0_len;
0051     __le32 buf_addr1_low;
0052     __le32 buf_addr1_high;
0053     __le32 buf_1_len;
0054     __le32 buf_addr2_low;
0055     __le32 buf_addr2_high;
0056     __le32 buf_2_len;
0057     __le32 reserved3;
0058     __le32 reserved4;
0059 };
0060 /*
0061  * The following constants define control bits for buffer
0062  * length fields for all IOCB's.
0063  */
0064 #define OB_MAC_IOCB_REQ_E   0x80000000  /* Last valid buffer in list. */
0065 #define OB_MAC_IOCB_REQ_C   0x40000000  /* points to an OAL. (continuation) */
0066 #define OB_MAC_IOCB_REQ_L   0x20000000  /* Auburn local address pointer. */
0067 #define OB_MAC_IOCB_REQ_R   0x10000000  /* 32-bit address pointer. */
0068 
0069 struct ob_mac_iocb_rsp {
0070     u8 opcode;
0071     u8 flags;
0072 #define OB_MAC_IOCB_RSP_P   0x08
0073 #define OB_MAC_IOCB_RSP_L   0x04
0074 #define OB_MAC_IOCB_RSP_S   0x02
0075 #define OB_MAC_IOCB_RSP_I   0x01
0076 
0077     __le16 reserved0;
0078     u32 transaction_id; /* opaque for hardware */
0079     __le32 reserved1;
0080     __le32 reserved2;
0081 };
0082 
0083 struct ib_mac_iocb_rsp {
0084     u8 opcode;
0085 #define IB_MAC_IOCB_RSP_V   0x80
0086     u8 flags;
0087 #define IB_MAC_IOCB_RSP_S   0x80
0088 #define IB_MAC_IOCB_RSP_H1  0x40
0089 #define IB_MAC_IOCB_RSP_H0  0x20
0090 #define IB_MAC_IOCB_RSP_B   0x10
0091 #define IB_MAC_IOCB_RSP_M   0x08
0092 #define IB_MAC_IOCB_RSP_MA  0x07
0093 
0094     __le16 length;
0095     __le32 reserved;
0096     __le32 ial_low;
0097     __le32 ial_high;
0098 
0099 };
0100 
0101 struct ob_ip_iocb_req {
0102     u8 opcode;
0103     __le16 flags;
0104 #define OB_IP_IOCB_REQ_O        0x100
0105 #define OB_IP_IOCB_REQ_H        0x008
0106 #define OB_IP_IOCB_REQ_U        0x004
0107 #define OB_IP_IOCB_REQ_D        0x002
0108 #define OB_IP_IOCB_REQ_I        0x001
0109 
0110     u8 reserved0;
0111 
0112     __le32 transaction_id;
0113     __le16 data_len;
0114     __le16 reserved1;
0115     __le32 hncb_ptr_low;
0116     __le32 hncb_ptr_high;
0117     __le32 buf_addr0_low;
0118     __le32 buf_addr0_high;
0119     __le32 buf_0_len;
0120     __le32 buf_addr1_low;
0121     __le32 buf_addr1_high;
0122     __le32 buf_1_len;
0123     __le32 buf_addr2_low;
0124     __le32 buf_addr2_high;
0125     __le32 buf_2_len;
0126     __le32 reserved2;
0127     __le32 reserved3;
0128 };
0129 
0130 /* defines for BufferLength fields above */
0131 #define OB_IP_IOCB_REQ_E    0x80000000
0132 #define OB_IP_IOCB_REQ_C    0x40000000
0133 #define OB_IP_IOCB_REQ_L    0x20000000
0134 #define OB_IP_IOCB_REQ_R    0x10000000
0135 
0136 struct ob_ip_iocb_rsp {
0137     u8 opcode;
0138     u8 flags;
0139 #define OB_MAC_IOCB_RSP_H       0x10
0140 #define OB_MAC_IOCB_RSP_E       0x08
0141 #define OB_MAC_IOCB_RSP_L       0x04
0142 #define OB_MAC_IOCB_RSP_S       0x02
0143 #define OB_MAC_IOCB_RSP_I       0x01
0144 
0145     __le16 reserved0;
0146     __le32 transaction_id;
0147     __le32 reserved1;
0148     __le32 reserved2;
0149 };
0150 
0151 struct ib_ip_iocb_rsp {
0152     u8 opcode;
0153 #define IB_IP_IOCB_RSP_3032_V   0x80
0154 #define IB_IP_IOCB_RSP_3032_O   0x40
0155 #define IB_IP_IOCB_RSP_3032_I   0x20
0156 #define IB_IP_IOCB_RSP_3032_R   0x10
0157     u8 flags;
0158 #define IB_IP_IOCB_RSP_S        0x80
0159 #define IB_IP_IOCB_RSP_H1       0x40
0160 #define IB_IP_IOCB_RSP_H0       0x20
0161 #define IB_IP_IOCB_RSP_B        0x10
0162 #define IB_IP_IOCB_RSP_M        0x08
0163 #define IB_IP_IOCB_RSP_MA       0x07
0164 
0165     __le16 length;
0166     __le16 checksum;
0167 #define IB_IP_IOCB_RSP_3032_ICE     0x01
0168 #define IB_IP_IOCB_RSP_3032_CE      0x02
0169 #define IB_IP_IOCB_RSP_3032_NUC     0x04
0170 #define IB_IP_IOCB_RSP_3032_UDP     0x08
0171 #define IB_IP_IOCB_RSP_3032_TCP     0x10
0172 #define IB_IP_IOCB_RSP_3032_IPE     0x20
0173     __le16 reserved;
0174 #define IB_IP_IOCB_RSP_R        0x01
0175     __le32 ial_low;
0176     __le32 ial_high;
0177 };
0178 
0179 struct net_rsp_iocb {
0180     u8 opcode;
0181     u8 flags;
0182     __le16 reserved0;
0183     __le32 reserved[3];
0184 };
0185 #pragma pack()
0186 
0187 /*
0188  * Register Definitions...
0189  */
0190 #define PORT0_PHY_ADDRESS   0x1e00
0191 #define PORT1_PHY_ADDRESS   0x1f00
0192 
0193 #define ETHERNET_CRC_SIZE   4
0194 
0195 #define MII_SCAN_REGISTER 0x00000001
0196 
0197 #define PHY_ID_0_REG    2
0198 #define PHY_ID_1_REG    3
0199 
0200 #define PHY_OUI_1_MASK       0xfc00
0201 #define PHY_MODEL_MASK       0x03f0
0202 
0203 /*  Address for the Agere Phy */
0204 #define MII_AGERE_ADDR_1  0x00001000
0205 #define MII_AGERE_ADDR_2  0x00001100
0206 
0207 /* 32-bit ispControlStatus */
0208 enum {
0209     ISP_CONTROL_NP_MASK = 0x0003,
0210     ISP_CONTROL_NP_PCSR = 0x0000,
0211     ISP_CONTROL_NP_HMCR = 0x0001,
0212     ISP_CONTROL_NP_LRAMCR = 0x0002,
0213     ISP_CONTROL_NP_PSR = 0x0003,
0214     ISP_CONTROL_RI = 0x0008,
0215     ISP_CONTROL_CI = 0x0010,
0216     ISP_CONTROL_PI = 0x0020,
0217     ISP_CONTROL_IN = 0x0040,
0218     ISP_CONTROL_BE = 0x0080,
0219     ISP_CONTROL_FN_MASK = 0x0700,
0220     ISP_CONTROL_FN0_NET = 0x0400,
0221     ISP_CONTROL_FN0_SCSI = 0x0500,
0222     ISP_CONTROL_FN1_NET = 0x0600,
0223     ISP_CONTROL_FN1_SCSI = 0x0700,
0224     ISP_CONTROL_LINK_DN_0 = 0x0800,
0225     ISP_CONTROL_LINK_DN_1 = 0x1000,
0226     ISP_CONTROL_FSR = 0x2000,
0227     ISP_CONTROL_FE = 0x4000,
0228     ISP_CONTROL_SR = 0x8000,
0229 };
0230 
0231 /* 32-bit ispInterruptMaskReg */
0232 enum {
0233     ISP_IMR_ENABLE_INT = 0x0004,
0234     ISP_IMR_DISABLE_RESET_INT = 0x0008,
0235     ISP_IMR_DISABLE_CMPL_INT = 0x0010,
0236     ISP_IMR_DISABLE_PROC_INT = 0x0020,
0237 };
0238 
0239 /* 32-bit serialPortInterfaceReg */
0240 enum {
0241     ISP_SERIAL_PORT_IF_CLK = 0x0001,
0242     ISP_SERIAL_PORT_IF_CS = 0x0002,
0243     ISP_SERIAL_PORT_IF_D0 = 0x0004,
0244     ISP_SERIAL_PORT_IF_DI = 0x0008,
0245     ISP_NVRAM_MASK = (0x000F << 16),
0246     ISP_SERIAL_PORT_IF_WE = 0x0010,
0247     ISP_SERIAL_PORT_IF_NVR_MASK = 0x001F,
0248     ISP_SERIAL_PORT_IF_SCI = 0x0400,
0249     ISP_SERIAL_PORT_IF_SC0 = 0x0800,
0250     ISP_SERIAL_PORT_IF_SCE = 0x1000,
0251     ISP_SERIAL_PORT_IF_SDI = 0x2000,
0252     ISP_SERIAL_PORT_IF_SDO = 0x4000,
0253     ISP_SERIAL_PORT_IF_SDE = 0x8000,
0254     ISP_SERIAL_PORT_IF_I2C_MASK = 0xFC00,
0255 };
0256 
0257 /* semaphoreReg */
0258 enum {
0259     QL_RESOURCE_MASK_BASE_CODE = 0x7,
0260     QL_RESOURCE_BITS_BASE_CODE = 0x4,
0261     QL_DRVR_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 1),
0262     QL_DDR_RAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 4),
0263     QL_PHY_GIO_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 7),
0264     QL_NVRAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 10),
0265     QL_FLASH_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 13),
0266     QL_DRVR_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (1 + 16)),
0267     QL_DDR_RAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (4 + 16)),
0268     QL_PHY_GIO_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (7 + 16)),
0269     QL_NVRAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (10 + 16)),
0270     QL_FLASH_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (13 + 16)),
0271 };
0272 
0273  /*
0274   * QL3XXX memory-mapped registers
0275   * QL3XXX has 4 "pages" of registers, each page occupying
0276   * 256 bytes.  Each page has a "common" area at the start and then
0277   * page-specific registers after that.
0278   */
0279 struct ql3xxx_common_registers {
0280     u32 MB0;        /* Offset 0x00 */
0281     u32 MB1;        /* Offset 0x04 */
0282     u32 MB2;        /* Offset 0x08 */
0283     u32 MB3;        /* Offset 0x0c */
0284     u32 MB4;        /* Offset 0x10 */
0285     u32 MB5;        /* Offset 0x14 */
0286     u32 MB6;        /* Offset 0x18 */
0287     u32 MB7;        /* Offset 0x1c */
0288     u32 flashBiosAddr;
0289     u32 flashBiosData;
0290     u32 ispControlStatus;
0291     u32 ispInterruptMaskReg;
0292     u32 serialPortInterfaceReg;
0293     u32 semaphoreReg;
0294     u32 reqQProducerIndex;
0295     u32 rspQConsumerIndex;
0296 
0297     u32 rxLargeQProducerIndex;
0298     u32 rxSmallQProducerIndex;
0299     u32 arcMadiCommand;
0300     u32 arcMadiData;
0301 };
0302 
0303 enum {
0304     EXT_HW_CONFIG_SP_MASK = 0x0006,
0305     EXT_HW_CONFIG_SP_NONE = 0x0000,
0306     EXT_HW_CONFIG_SP_BYTE_PARITY = 0x0002,
0307     EXT_HW_CONFIG_SP_ECC = 0x0004,
0308     EXT_HW_CONFIG_SP_ECCx = 0x0006,
0309     EXT_HW_CONFIG_SIZE_MASK = 0x0060,
0310     EXT_HW_CONFIG_SIZE_128M = 0x0000,
0311     EXT_HW_CONFIG_SIZE_256M = 0x0020,
0312     EXT_HW_CONFIG_SIZE_512M = 0x0040,
0313     EXT_HW_CONFIG_SIZE_INVALID = 0x0060,
0314     EXT_HW_CONFIG_PD = 0x0080,
0315     EXT_HW_CONFIG_FW = 0x0200,
0316     EXT_HW_CONFIG_US = 0x0400,
0317     EXT_HW_CONFIG_DCS_MASK = 0x1800,
0318     EXT_HW_CONFIG_DCS_9MA = 0x0000,
0319     EXT_HW_CONFIG_DCS_15MA = 0x0800,
0320     EXT_HW_CONFIG_DCS_18MA = 0x1000,
0321     EXT_HW_CONFIG_DCS_24MA = 0x1800,
0322     EXT_HW_CONFIG_DDS_MASK = 0x6000,
0323     EXT_HW_CONFIG_DDS_9MA = 0x0000,
0324     EXT_HW_CONFIG_DDS_15MA = 0x2000,
0325     EXT_HW_CONFIG_DDS_18MA = 0x4000,
0326     EXT_HW_CONFIG_DDS_24MA = 0x6000,
0327 };
0328 
0329 /* InternalChipConfig */
0330 enum {
0331     INTERNAL_CHIP_DM = 0x0001,
0332     INTERNAL_CHIP_SD = 0x0002,
0333     INTERNAL_CHIP_RAP_MASK = 0x000C,
0334     INTERNAL_CHIP_RAP_RR = 0x0000,
0335     INTERNAL_CHIP_RAP_NRM = 0x0004,
0336     INTERNAL_CHIP_RAP_ERM = 0x0008,
0337     INTERNAL_CHIP_RAP_ERMx = 0x000C,
0338     INTERNAL_CHIP_WE = 0x0010,
0339     INTERNAL_CHIP_EF = 0x0020,
0340     INTERNAL_CHIP_FR = 0x0040,
0341     INTERNAL_CHIP_FW = 0x0080,
0342     INTERNAL_CHIP_FI = 0x0100,
0343     INTERNAL_CHIP_FT = 0x0200,
0344 };
0345 
0346 /* portControl */
0347 enum {
0348     PORT_CONTROL_DS = 0x0001,
0349     PORT_CONTROL_HH = 0x0002,
0350     PORT_CONTROL_EI = 0x0004,
0351     PORT_CONTROL_ET = 0x0008,
0352     PORT_CONTROL_EF = 0x0010,
0353     PORT_CONTROL_DRM = 0x0020,
0354     PORT_CONTROL_RLB = 0x0040,
0355     PORT_CONTROL_RCB = 0x0080,
0356     PORT_CONTROL_MAC = 0x0100,
0357     PORT_CONTROL_IPV = 0x0200,
0358     PORT_CONTROL_IFP = 0x0400,
0359     PORT_CONTROL_ITP = 0x0800,
0360     PORT_CONTROL_FI = 0x1000,
0361     PORT_CONTROL_DFP = 0x2000,
0362     PORT_CONTROL_OI = 0x4000,
0363     PORT_CONTROL_CC = 0x8000,
0364 };
0365 
0366 /* portStatus */
0367 enum {
0368     PORT_STATUS_SM0 = 0x0001,
0369     PORT_STATUS_SM1 = 0x0002,
0370     PORT_STATUS_X = 0x0008,
0371     PORT_STATUS_DL = 0x0080,
0372     PORT_STATUS_IC = 0x0200,
0373     PORT_STATUS_MRC = 0x0400,
0374     PORT_STATUS_NL = 0x0800,
0375     PORT_STATUS_REV_ID_MASK = 0x7000,
0376     PORT_STATUS_REV_ID_1 = 0x1000,
0377     PORT_STATUS_REV_ID_2 = 0x2000,
0378     PORT_STATUS_REV_ID_3 = 0x3000,
0379     PORT_STATUS_64 = 0x8000,
0380     PORT_STATUS_UP0 = 0x10000,
0381     PORT_STATUS_AC0 = 0x20000,
0382     PORT_STATUS_AE0 = 0x40000,
0383     PORT_STATUS_UP1 = 0x100000,
0384     PORT_STATUS_AC1 = 0x200000,
0385     PORT_STATUS_AE1 = 0x400000,
0386     PORT_STATUS_F0_ENABLED = 0x1000000,
0387     PORT_STATUS_F1_ENABLED = 0x2000000,
0388     PORT_STATUS_F2_ENABLED = 0x4000000,
0389     PORT_STATUS_F3_ENABLED = 0x8000000,
0390 };
0391 
0392 /* macMIIMgmtControlReg */
0393 enum {
0394     MAC_ADDR_INDIRECT_PTR_REG_RP_MASK = 0x0003,
0395     MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_LWR = 0x0000,
0396     MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_UPR = 0x0001,
0397     MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_LWR = 0x0002,
0398     MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_UPR = 0x0003,
0399     MAC_ADDR_INDIRECT_PTR_REG_PR = 0x0008,
0400     MAC_ADDR_INDIRECT_PTR_REG_SS = 0x0010,
0401     MAC_ADDR_INDIRECT_PTR_REG_SE = 0x0020,
0402     MAC_ADDR_INDIRECT_PTR_REG_SP = 0x0040,
0403     MAC_ADDR_INDIRECT_PTR_REG_PE = 0x0080,
0404 };
0405 
0406 /* macMIIMgmtControlReg */
0407 enum {
0408     MAC_MII_CONTROL_RC = 0x0001,
0409     MAC_MII_CONTROL_SC = 0x0002,
0410     MAC_MII_CONTROL_AS = 0x0004,
0411     MAC_MII_CONTROL_NP = 0x0008,
0412     MAC_MII_CONTROL_CLK_SEL_MASK = 0x0070,
0413     MAC_MII_CONTROL_CLK_SEL_DIV2 = 0x0000,
0414     MAC_MII_CONTROL_CLK_SEL_DIV4 = 0x0010,
0415     MAC_MII_CONTROL_CLK_SEL_DIV6 = 0x0020,
0416     MAC_MII_CONTROL_CLK_SEL_DIV8 = 0x0030,
0417     MAC_MII_CONTROL_CLK_SEL_DIV10 = 0x0040,
0418     MAC_MII_CONTROL_CLK_SEL_DIV14 = 0x0050,
0419     MAC_MII_CONTROL_CLK_SEL_DIV20 = 0x0060,
0420     MAC_MII_CONTROL_CLK_SEL_DIV28 = 0x0070,
0421     MAC_MII_CONTROL_RM = 0x8000,
0422 };
0423 
0424 /* macMIIStatusReg */
0425 enum {
0426     MAC_MII_STATUS_BSY = 0x0001,
0427     MAC_MII_STATUS_SC = 0x0002,
0428     MAC_MII_STATUS_NV = 0x0004,
0429 };
0430 
0431 enum {
0432     MAC_CONFIG_REG_PE = 0x0001,
0433     MAC_CONFIG_REG_TF = 0x0002,
0434     MAC_CONFIG_REG_RF = 0x0004,
0435     MAC_CONFIG_REG_FD = 0x0008,
0436     MAC_CONFIG_REG_GM = 0x0010,
0437     MAC_CONFIG_REG_LB = 0x0020,
0438     MAC_CONFIG_REG_SR = 0x8000,
0439 };
0440 
0441 enum {
0442     MAC_HALF_DUPLEX_REG_ED = 0x10000,
0443     MAC_HALF_DUPLEX_REG_NB = 0x20000,
0444     MAC_HALF_DUPLEX_REG_BNB = 0x40000,
0445     MAC_HALF_DUPLEX_REG_ALT = 0x80000,
0446 };
0447 
0448 enum {
0449     IP_ADDR_INDEX_REG_MASK = 0x000f,
0450     IP_ADDR_INDEX_REG_FUNC_0_PRI = 0x0000,
0451     IP_ADDR_INDEX_REG_FUNC_0_SEC = 0x0001,
0452     IP_ADDR_INDEX_REG_FUNC_1_PRI = 0x0002,
0453     IP_ADDR_INDEX_REG_FUNC_1_SEC = 0x0003,
0454     IP_ADDR_INDEX_REG_FUNC_2_PRI = 0x0004,
0455     IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005,
0456     IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006,
0457     IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007,
0458     IP_ADDR_INDEX_REG_6 = 0x0008,
0459     IP_ADDR_INDEX_REG_OFFSET_MASK = 0x0030,
0460     IP_ADDR_INDEX_REG_E = 0x0040,
0461 };
0462 enum {
0463     QL3032_PORT_CONTROL_DS = 0x0001,
0464     QL3032_PORT_CONTROL_HH = 0x0002,
0465     QL3032_PORT_CONTROL_EIv6 = 0x0004,
0466     QL3032_PORT_CONTROL_EIv4 = 0x0008,
0467     QL3032_PORT_CONTROL_ET = 0x0010,
0468     QL3032_PORT_CONTROL_EF = 0x0020,
0469     QL3032_PORT_CONTROL_DRM = 0x0040,
0470     QL3032_PORT_CONTROL_RLB = 0x0080,
0471     QL3032_PORT_CONTROL_RCB = 0x0100,
0472     QL3032_PORT_CONTROL_KIE = 0x0200,
0473 };
0474 
0475 enum {
0476     PROBE_MUX_ADDR_REG_MUX_SEL_MASK = 0x003f,
0477     PROBE_MUX_ADDR_REG_SYSCLK = 0x0000,
0478     PROBE_MUX_ADDR_REG_PCICLK = 0x0040,
0479     PROBE_MUX_ADDR_REG_NRXCLK = 0x0080,
0480     PROBE_MUX_ADDR_REG_CPUCLK = 0x00C0,
0481     PROBE_MUX_ADDR_REG_MODULE_SEL_MASK = 0x3f00,
0482     PROBE_MUX_ADDR_REG_UP = 0x4000,
0483     PROBE_MUX_ADDR_REG_RE = 0x8000,
0484 };
0485 
0486 enum {
0487     STATISTICS_INDEX_REG_MASK = 0x01ff,
0488     STATISTICS_INDEX_REG_MAC0_TX_FRAME = 0x0000,
0489     STATISTICS_INDEX_REG_MAC0_TX_BYTES = 0x0001,
0490     STATISTICS_INDEX_REG_MAC0_TX_STAT1 = 0x0002,
0491     STATISTICS_INDEX_REG_MAC0_TX_STAT2 = 0x0003,
0492     STATISTICS_INDEX_REG_MAC0_TX_STAT3 = 0x0004,
0493     STATISTICS_INDEX_REG_MAC0_TX_STAT4 = 0x0005,
0494     STATISTICS_INDEX_REG_MAC0_TX_STAT5 = 0x0006,
0495     STATISTICS_INDEX_REG_MAC0_RX_FRAME = 0x0007,
0496     STATISTICS_INDEX_REG_MAC0_RX_BYTES = 0x0008,
0497     STATISTICS_INDEX_REG_MAC0_RX_STAT1 = 0x0009,
0498     STATISTICS_INDEX_REG_MAC0_RX_STAT2 = 0x000a,
0499     STATISTICS_INDEX_REG_MAC0_RX_STAT3 = 0x000b,
0500     STATISTICS_INDEX_REG_MAC0_RX_ERR_CRC = 0x000c,
0501     STATISTICS_INDEX_REG_MAC0_RX_ERR_ENC = 0x000d,
0502     STATISTICS_INDEX_REG_MAC0_RX_ERR_LEN = 0x000e,
0503     STATISTICS_INDEX_REG_MAC0_RX_STAT4 = 0x000f,
0504     STATISTICS_INDEX_REG_MAC1_TX_FRAME = 0x0010,
0505     STATISTICS_INDEX_REG_MAC1_TX_BYTES = 0x0011,
0506     STATISTICS_INDEX_REG_MAC1_TX_STAT1 = 0x0012,
0507     STATISTICS_INDEX_REG_MAC1_TX_STAT2 = 0x0013,
0508     STATISTICS_INDEX_REG_MAC1_TX_STAT3 = 0x0014,
0509     STATISTICS_INDEX_REG_MAC1_TX_STAT4 = 0x0015,
0510     STATISTICS_INDEX_REG_MAC1_TX_STAT5 = 0x0016,
0511     STATISTICS_INDEX_REG_MAC1_RX_FRAME = 0x0017,
0512     STATISTICS_INDEX_REG_MAC1_RX_BYTES = 0x0018,
0513     STATISTICS_INDEX_REG_MAC1_RX_STAT1 = 0x0019,
0514     STATISTICS_INDEX_REG_MAC1_RX_STAT2 = 0x001a,
0515     STATISTICS_INDEX_REG_MAC1_RX_STAT3 = 0x001b,
0516     STATISTICS_INDEX_REG_MAC1_RX_ERR_CRC = 0x001c,
0517     STATISTICS_INDEX_REG_MAC1_RX_ERR_ENC = 0x001d,
0518     STATISTICS_INDEX_REG_MAC1_RX_ERR_LEN = 0x001e,
0519     STATISTICS_INDEX_REG_MAC1_RX_STAT4 = 0x001f,
0520     STATISTICS_INDEX_REG_IP_TX_PKTS = 0x0020,
0521     STATISTICS_INDEX_REG_IP_TX_BYTES = 0x0021,
0522     STATISTICS_INDEX_REG_IP_TX_FRAG = 0x0022,
0523     STATISTICS_INDEX_REG_IP_RX_PKTS = 0x0023,
0524     STATISTICS_INDEX_REG_IP_RX_BYTES = 0x0024,
0525     STATISTICS_INDEX_REG_IP_RX_FRAG = 0x0025,
0526     STATISTICS_INDEX_REG_IP_DGRM_REASSEMBLY = 0x0026,
0527     STATISTICS_INDEX_REG_IP_V6_RX_PKTS = 0x0027,
0528     STATISTICS_INDEX_REG_IP_RX_PKTERR = 0x0028,
0529     STATISTICS_INDEX_REG_IP_REASSEMBLY_ERR = 0x0029,
0530     STATISTICS_INDEX_REG_TCP_TX_SEG = 0x0030,
0531     STATISTICS_INDEX_REG_TCP_TX_BYTES = 0x0031,
0532     STATISTICS_INDEX_REG_TCP_RX_SEG = 0x0032,
0533     STATISTICS_INDEX_REG_TCP_RX_BYTES = 0x0033,
0534     STATISTICS_INDEX_REG_TCP_TIMER_EXP = 0x0034,
0535     STATISTICS_INDEX_REG_TCP_RX_ACK = 0x0035,
0536     STATISTICS_INDEX_REG_TCP_TX_ACK = 0x0036,
0537     STATISTICS_INDEX_REG_TCP_RX_ERR = 0x0037,
0538     STATISTICS_INDEX_REG_TCP_RX_WIN_PROBE = 0x0038,
0539     STATISTICS_INDEX_REG_TCP_ECC_ERR_CORR = 0x003f,
0540 };
0541 
0542 enum {
0543     PORT_FATAL_ERROR_STATUS_OFB_RE_MAC0 = 0x00000001,
0544     PORT_FATAL_ERROR_STATUS_OFB_RE_MAC1 = 0x00000002,
0545     PORT_FATAL_ERROR_STATUS_OFB_WE = 0x00000004,
0546     PORT_FATAL_ERROR_STATUS_IFB_RE = 0x00000008,
0547     PORT_FATAL_ERROR_STATUS_IFB_WE_MAC0 = 0x00000010,
0548     PORT_FATAL_ERROR_STATUS_IFB_WE_MAC1 = 0x00000020,
0549     PORT_FATAL_ERROR_STATUS_ODE_RE = 0x00000040,
0550     PORT_FATAL_ERROR_STATUS_ODE_WE = 0x00000080,
0551     PORT_FATAL_ERROR_STATUS_IDE_RE = 0x00000100,
0552     PORT_FATAL_ERROR_STATUS_IDE_WE = 0x00000200,
0553     PORT_FATAL_ERROR_STATUS_SDE_RE = 0x00000400,
0554     PORT_FATAL_ERROR_STATUS_SDE_WE = 0x00000800,
0555     PORT_FATAL_ERROR_STATUS_BLE = 0x00001000,
0556     PORT_FATAL_ERROR_STATUS_SPE = 0x00002000,
0557     PORT_FATAL_ERROR_STATUS_EP0 = 0x00004000,
0558     PORT_FATAL_ERROR_STATUS_EP1 = 0x00008000,
0559     PORT_FATAL_ERROR_STATUS_ICE = 0x00010000,
0560     PORT_FATAL_ERROR_STATUS_ILE = 0x00020000,
0561     PORT_FATAL_ERROR_STATUS_OPE = 0x00040000,
0562     PORT_FATAL_ERROR_STATUS_TA = 0x00080000,
0563     PORT_FATAL_ERROR_STATUS_MA = 0x00100000,
0564     PORT_FATAL_ERROR_STATUS_SCE = 0x00200000,
0565     PORT_FATAL_ERROR_STATUS_RPE = 0x00400000,
0566     PORT_FATAL_ERROR_STATUS_MPE = 0x00800000,
0567     PORT_FATAL_ERROR_STATUS_OCE = 0x01000000,
0568 };
0569 
0570 /*
0571  *  port control and status page - page 0
0572  */
0573 
0574 struct ql3xxx_port_registers {
0575     struct ql3xxx_common_registers CommonRegs;
0576 
0577     u32 ExternalHWConfig;
0578     u32 InternalChipConfig;
0579     u32 portControl;
0580     u32 portStatus;
0581     u32 macAddrIndirectPtrReg;
0582     u32 macAddrDataReg;
0583     u32 macMIIMgmtControlReg;
0584     u32 macMIIMgmtAddrReg;
0585     u32 macMIIMgmtDataReg;
0586     u32 macMIIStatusReg;
0587     u32 mac0ConfigReg;
0588     u32 mac0IpgIfgReg;
0589     u32 mac0HalfDuplexReg;
0590     u32 mac0MaxFrameLengthReg;
0591     u32 mac0PauseThresholdReg;
0592     u32 mac1ConfigReg;
0593     u32 mac1IpgIfgReg;
0594     u32 mac1HalfDuplexReg;
0595     u32 mac1MaxFrameLengthReg;
0596     u32 mac1PauseThresholdReg;
0597     u32 ipAddrIndexReg;
0598     u32 ipAddrDataReg;
0599     u32 ipReassemblyTimeout;
0600     u32 tcpMaxWindow;
0601     u32 currentTcpTimestamp[2];
0602     u32 internalRamRWAddrReg;
0603     u32 internalRamWDataReg;
0604     u32 reclaimedBufferAddrRegLow;
0605     u32 reclaimedBufferAddrRegHigh;
0606     u32 tcpConfiguration;
0607     u32 functionControl;
0608     u32 fpgaRevID;
0609     u32 localRamAddr;
0610     u32 localRamDataAutoIncr;
0611     u32 localRamDataNonIncr;
0612     u32 gpOutput;
0613     u32 gpInput;
0614     u32 probeMuxAddr;
0615     u32 probeMuxData;
0616     u32 statisticsIndexReg;
0617     u32 statisticsReadDataRegAutoIncr;
0618     u32 statisticsReadDataRegNoIncr;
0619     u32 PortFatalErrStatus;
0620 };
0621 
0622 /*
0623  * port host memory config page - page 1
0624  */
0625 struct ql3xxx_host_memory_registers {
0626     struct ql3xxx_common_registers CommonRegs;
0627 
0628     u32 reserved[12];
0629 
0630     /* Network Request Queue */
0631     u32 reqConsumerIndex;
0632     u32 reqConsumerIndexAddrLow;
0633     u32 reqConsumerIndexAddrHigh;
0634     u32 reqBaseAddrLow;
0635     u32 reqBaseAddrHigh;
0636     u32 reqLength;
0637 
0638     /* Network Completion Queue */
0639     u32 rspProducerIndex;
0640     u32 rspProducerIndexAddrLow;
0641     u32 rspProducerIndexAddrHigh;
0642     u32 rspBaseAddrLow;
0643     u32 rspBaseAddrHigh;
0644     u32 rspLength;
0645 
0646     /* RX Large Buffer Queue */
0647     u32 rxLargeQConsumerIndex;
0648     u32 rxLargeQBaseAddrLow;
0649     u32 rxLargeQBaseAddrHigh;
0650     u32 rxLargeQLength;
0651     u32 rxLargeBufferLength;
0652 
0653     /* RX Small Buffer Queue */
0654     u32 rxSmallQConsumerIndex;
0655     u32 rxSmallQBaseAddrLow;
0656     u32 rxSmallQBaseAddrHigh;
0657     u32 rxSmallQLength;
0658     u32 rxSmallBufferLength;
0659 
0660 };
0661 
0662 /*
0663  *  port local RAM page - page 2
0664  */
0665 struct ql3xxx_local_ram_registers {
0666     struct ql3xxx_common_registers CommonRegs;
0667     u32 bufletSize;
0668     u32 maxBufletCount;
0669     u32 currentBufletCount;
0670     u32 reserved;
0671     u32 freeBufletThresholdLow;
0672     u32 freeBufletThresholdHigh;
0673     u32 ipHashTableBase;
0674     u32 ipHashTableCount;
0675     u32 tcpHashTableBase;
0676     u32 tcpHashTableCount;
0677     u32 ncbBase;
0678     u32 maxNcbCount;
0679     u32 currentNcbCount;
0680     u32 drbBase;
0681     u32 maxDrbCount;
0682     u32 currentDrbCount;
0683 };
0684 
0685 /*
0686  * definitions for Semaphore bits in Semaphore/Serial NVRAM interface register
0687  */
0688 
0689 #define LS_64BITS(x)    (u32)(0xffffffff & ((u64)x))
0690 #define MS_64BITS(x)    (u32)(0xffffffff & (((u64)x)>>16>>16) )
0691 
0692 /*
0693  * I/O register
0694  */
0695 
0696 enum {
0697     CONTROL_REG = 0,
0698     STATUS_REG = 1,
0699     PHY_STAT_LINK_UP = 0x0004,
0700     PHY_CTRL_LOOPBACK = 0x4000,
0701 
0702     PETBI_CONTROL_REG = 0x00,
0703     PETBI_CTRL_ALL_PARAMS = 0x7140,
0704     PETBI_CTRL_SOFT_RESET = 0x8000,
0705     PETBI_CTRL_AUTO_NEG = 0x1000,
0706     PETBI_CTRL_RESTART_NEG = 0x0200,
0707     PETBI_CTRL_FULL_DUPLEX = 0x0100,
0708     PETBI_CTRL_SPEED_1000 = 0x0040,
0709 
0710     PETBI_STATUS_REG = 0x01,
0711     PETBI_STAT_NEG_DONE = 0x0020,
0712     PETBI_STAT_LINK_UP = 0x0004,
0713 
0714     PETBI_NEG_ADVER = 0x04,
0715     PETBI_NEG_PAUSE = 0x0080,
0716     PETBI_NEG_PAUSE_MASK = 0x0180,
0717     PETBI_NEG_DUPLEX = 0x0020,
0718     PETBI_NEG_DUPLEX_MASK = 0x0060,
0719 
0720     PETBI_NEG_PARTNER = 0x05,
0721     PETBI_NEG_ERROR_MASK = 0x3000,
0722 
0723     PETBI_EXPANSION_REG = 0x06,
0724     PETBI_EXP_PAGE_RX = 0x0002,
0725 
0726     PHY_GIG_CONTROL = 9,
0727     PHY_GIG_ENABLE_MAN = 0x1000,  /* Enable Master/Slave Manual Config*/
0728     PHY_GIG_SET_MASTER = 0x0800,  /* Set Master (slave if clear)*/
0729     PHY_GIG_ALL_PARAMS = 0x0300,
0730     PHY_GIG_ADV_1000F = 0x0200,
0731     PHY_GIG_ADV_1000H = 0x0100,
0732 
0733     PHY_NEG_ADVER = 4,
0734     PHY_NEG_ALL_PARAMS = 0x0fe0,
0735     PHY_NEG_ASY_PAUSE =  0x0800,
0736     PHY_NEG_SYM_PAUSE =  0x0400,
0737     PHY_NEG_ADV_SPEED =  0x01e0,
0738     PHY_NEG_ADV_100F =   0x0100,
0739     PHY_NEG_ADV_100H =   0x0080,
0740     PHY_NEG_ADV_10F =    0x0040,
0741     PHY_NEG_ADV_10H =    0x0020,
0742 
0743     PETBI_TBI_CTRL = 0x11,
0744     PETBI_TBI_RESET = 0x8000,
0745     PETBI_TBI_AUTO_SENSE = 0x0100,
0746     PETBI_TBI_SERDES_MODE = 0x0010,
0747     PETBI_TBI_SERDES_WRAP = 0x0002,
0748 
0749     AUX_CONTROL_STATUS = 0x1c,
0750     PHY_AUX_NEG_DONE = 0x8000,
0751     PHY_NEG_PARTNER = 5,
0752     PHY_AUX_DUPLEX_STAT = 0x0020,
0753     PHY_AUX_SPEED_STAT = 0x0018,
0754     PHY_AUX_NO_HW_STRAP = 0x0004,
0755     PHY_AUX_RESET_STICK = 0x0002,
0756     PHY_NEG_PAUSE = 0x0400,
0757     PHY_CTRL_SOFT_RESET = 0x8000,
0758     PHY_CTRL_AUTO_NEG = 0x1000,
0759     PHY_CTRL_RESTART_NEG = 0x0200,
0760 };
0761 enum {
0762 /* AM29LV Flash definitions */
0763     FM93C56A_START = 0x1,
0764 /* Commands */
0765     FM93C56A_READ = 0x2,
0766     FM93C56A_WEN = 0x0,
0767     FM93C56A_WRITE = 0x1,
0768     FM93C56A_WRITE_ALL = 0x0,
0769     FM93C56A_WDS = 0x0,
0770     FM93C56A_ERASE = 0x3,
0771     FM93C56A_ERASE_ALL = 0x0,
0772 /* Command Extensions */
0773     FM93C56A_WEN_EXT = 0x3,
0774     FM93C56A_WRITE_ALL_EXT = 0x1,
0775     FM93C56A_WDS_EXT = 0x0,
0776     FM93C56A_ERASE_ALL_EXT = 0x2,
0777 /* Special Bits */
0778     FM93C56A_READ_DUMMY_BITS = 1,
0779     FM93C56A_READY = 0,
0780     FM93C56A_BUSY = 1,
0781     FM93C56A_CMD_BITS = 2,
0782 /* AM29LV Flash definitions */
0783     FM93C56A_SIZE_8 = 0x100,
0784     FM93C56A_SIZE_16 = 0x80,
0785     FM93C66A_SIZE_8 = 0x200,
0786     FM93C66A_SIZE_16 = 0x100,
0787     FM93C86A_SIZE_16 = 0x400,
0788 /* Address Bits */
0789     FM93C56A_NO_ADDR_BITS_16 = 8,
0790     FM93C56A_NO_ADDR_BITS_8 = 9,
0791     FM93C86A_NO_ADDR_BITS_16 = 10,
0792 /* Data Bits */
0793     FM93C56A_DATA_BITS_16 = 16,
0794     FM93C56A_DATA_BITS_8 = 8,
0795 };
0796 enum {
0797 /* Auburn Bits */
0798         AUBURN_EEPROM_DI = 0x8,
0799     AUBURN_EEPROM_DI_0 = 0x0,
0800     AUBURN_EEPROM_DI_1 = 0x8,
0801     AUBURN_EEPROM_DO = 0x4,
0802     AUBURN_EEPROM_DO_0 = 0x0,
0803     AUBURN_EEPROM_DO_1 = 0x4,
0804     AUBURN_EEPROM_CS = 0x2,
0805     AUBURN_EEPROM_CS_0 = 0x0,
0806     AUBURN_EEPROM_CS_1 = 0x2,
0807     AUBURN_EEPROM_CLK_RISE = 0x1,
0808     AUBURN_EEPROM_CLK_FALL = 0x0,
0809 };
0810 enum {EEPROM_SIZE = FM93C86A_SIZE_16,
0811     EEPROM_NO_ADDR_BITS = FM93C86A_NO_ADDR_BITS_16,
0812     EEPROM_NO_DATA_BITS = FM93C56A_DATA_BITS_16,
0813 };
0814 
0815 /*
0816  *  MAC Config data structure
0817  */
0818     struct eeprom_port_cfg {
0819     u16 etherMtu_mac;
0820     u16 pauseThreshold_mac;
0821     u16 resumeThreshold_mac;
0822     u16 portConfiguration;
0823 #define PORT_CONFIG_DEFAULT                 0xf700
0824 #define PORT_CONFIG_AUTO_NEG_ENABLED        0x8000
0825 #define PORT_CONFIG_SYM_PAUSE_ENABLED       0x4000
0826 #define PORT_CONFIG_FULL_DUPLEX_ENABLED     0x2000
0827 #define PORT_CONFIG_HALF_DUPLEX_ENABLED     0x1000
0828 #define PORT_CONFIG_1000MB_SPEED            0x0400
0829 #define PORT_CONFIG_100MB_SPEED             0x0200
0830 #define PORT_CONFIG_10MB_SPEED              0x0100
0831 #define PORT_CONFIG_LINK_SPEED_MASK         0x0F00
0832     u16 reserved[12];
0833 
0834 };
0835 
0836 /*
0837  * BIOS data structure
0838  */
0839 struct eeprom_bios_cfg {
0840     u16 SpinDlyEn:1, disBios:1, EnMemMap:1, EnSelectBoot:1, Reserved:12;
0841 
0842     u8 bootID0:7, boodID0Valid:1;
0843     u8 bootLun0[8];
0844 
0845     u8 bootID1:7, boodID1Valid:1;
0846     u8 bootLun1[8];
0847 
0848     u16 MaxLunsTrgt;
0849     u8 reserved[10];
0850 };
0851 
0852 /*
0853  *  Function Specific Data structure
0854  */
0855 struct eeprom_function_cfg {
0856     u8 reserved[30];
0857     u16 macAddress[3];
0858     u16 macAddressSecondary[3];
0859 
0860     u16 subsysVendorId;
0861     u16 subsysDeviceId;
0862 };
0863 
0864 /*
0865  *  EEPROM format
0866  */
0867 struct eeprom_data {
0868     u8 asicId[4];
0869     u16 version_and_numPorts; /* together to avoid endianness crap */
0870     u16 boardId;
0871 
0872 #define EEPROM_BOARDID_STR_SIZE   16
0873 #define EEPROM_SERIAL_NUM_SIZE    16
0874 
0875     u8 boardIdStr[16];
0876     u8 serialNumber[16];
0877     u16 extHwConfig;
0878     struct eeprom_port_cfg macCfg_port0;
0879     struct eeprom_port_cfg macCfg_port1;
0880     u16 bufletSize;
0881     u16 bufletCount;
0882     u16 tcpWindowThreshold50;
0883     u16 tcpWindowThreshold25;
0884     u16 tcpWindowThreshold0;
0885     u16 ipHashTableBaseHi;
0886     u16 ipHashTableBaseLo;
0887     u16 ipHashTableSize;
0888     u16 tcpHashTableBaseHi;
0889     u16 tcpHashTableBaseLo;
0890     u16 tcpHashTableSize;
0891     u16 ncbTableBaseHi;
0892     u16 ncbTableBaseLo;
0893     u16 ncbTableSize;
0894     u16 drbTableBaseHi;
0895     u16 drbTableBaseLo;
0896     u16 drbTableSize;
0897     u16 reserved_142[4];
0898     u16 ipReassemblyTimeout;
0899     u16 tcpMaxWindowSize;
0900     u16 ipSecurity;
0901 #define IPSEC_CONFIG_PRESENT 0x0001
0902     u8 reserved_156[294];
0903     u16 qDebug[8];
0904     struct eeprom_function_cfg funcCfg_fn0;
0905     u16 reserved_510;
0906     u8 oemSpace[432];
0907     struct eeprom_bios_cfg biosCfg_fn1;
0908     struct eeprom_function_cfg funcCfg_fn1;
0909     u16 reserved_1022;
0910     u8 reserved_1024[464];
0911     struct eeprom_function_cfg funcCfg_fn2;
0912     u16 reserved_1534;
0913     u8 reserved_1536[432];
0914     struct eeprom_bios_cfg biosCfg_fn3;
0915     struct eeprom_function_cfg funcCfg_fn3;
0916     u16 checksum;
0917 };
0918 
0919 /*
0920  * General definitions...
0921  */
0922 
0923 /*
0924  * Below are a number compiler switches for controlling driver behavior.
0925  * Some are not supported under certain conditions and are notated as such.
0926  */
0927 
0928 #define QL3XXX_VENDOR_ID    0x1077
0929 #define QL3022_DEVICE_ID    0x3022
0930 #define QL3032_DEVICE_ID    0x3032
0931 
0932 /* MTU & Frame Size stuff */
0933 #define NORMAL_MTU_SIZE         ETH_DATA_LEN
0934 #define JUMBO_MTU_SIZE          9000
0935 #define VLAN_ID_LEN             2
0936 
0937 /* Request Queue Related Definitions */
0938 #define NUM_REQ_Q_ENTRIES   256 /* so that 64 * 64  = 4096 (1 page) */
0939 
0940 /* Response Queue Related Definitions */
0941 #define NUM_RSP_Q_ENTRIES   256 /* so that 256 * 16  = 4096 (1 page) */
0942 
0943 /* Transmit and Receive Buffers */
0944 #define NUM_LBUFQ_ENTRIES       128
0945 #define JUMBO_NUM_LBUFQ_ENTRIES 32
0946 #define NUM_SBUFQ_ENTRIES       64
0947 #define QL_SMALL_BUFFER_SIZE    32
0948 #define QL_ADDR_ELE_PER_BUFQ_ENTRY \
0949 (sizeof(struct lrg_buf_q_entry) / sizeof(struct bufq_addr_element))
0950     /* Each send has at least control block.  This is how many we keep. */
0951 #define NUM_SMALL_BUFFERS       NUM_SBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY
0952 
0953 #define QL_HEADER_SPACE 32  /* make header space at top of skb. */
0954 /*
0955  * Large & Small Buffers for Receives
0956  */
0957 struct lrg_buf_q_entry {
0958 
0959     __le32 addr0_lower;
0960 #define IAL_LAST_ENTRY 0x00000001
0961 #define IAL_CONT_ENTRY 0x00000002
0962 #define IAL_FLAG_MASK  0x00000003
0963     __le32 addr0_upper;
0964     __le32 addr1_lower;
0965     __le32 addr1_upper;
0966     __le32 addr2_lower;
0967     __le32 addr2_upper;
0968     __le32 addr3_lower;
0969     __le32 addr3_upper;
0970     __le32 addr4_lower;
0971     __le32 addr4_upper;
0972     __le32 addr5_lower;
0973     __le32 addr5_upper;
0974     __le32 addr6_lower;
0975     __le32 addr6_upper;
0976     __le32 addr7_lower;
0977     __le32 addr7_upper;
0978 
0979 };
0980 
0981 struct bufq_addr_element {
0982     __le32 addr_low;
0983     __le32 addr_high;
0984 };
0985 
0986 #define QL_NO_RESET         0
0987 #define QL_DO_RESET         1
0988 
0989 enum link_state_t {
0990     LS_UNKNOWN = 0,
0991     LS_DOWN,
0992     LS_DEGRADE,
0993     LS_RECOVER,
0994     LS_UP,
0995 };
0996 
0997 struct ql_rcv_buf_cb {
0998     struct ql_rcv_buf_cb *next;
0999     struct sk_buff *skb;
1000     DEFINE_DMA_UNMAP_ADDR(mapaddr);
1001     DEFINE_DMA_UNMAP_LEN(maplen);
1002     __le32 buf_phy_addr_low;
1003     __le32 buf_phy_addr_high;
1004     int index;
1005 };
1006 
1007 /*
1008  * Original IOCB has 3 sg entries:
1009  * first points to skb-data area
1010  * second points to first frag
1011  * third points to next oal.
1012  * OAL has 5 entries:
1013  * 1 thru 4 point to frags
1014  * fifth points to next oal.
1015  */
1016 #define MAX_OAL_CNT ((MAX_SKB_FRAGS-1)/4 + 1)
1017 
1018 struct oal_entry {
1019     __le32 dma_lo;
1020     __le32 dma_hi;
1021     __le32 len;
1022 #define OAL_LAST_ENTRY   0x80000000 /* Last valid buffer in list. */
1023 #define OAL_CONT_ENTRY   0x40000000 /* points to an OAL. (continuation) */
1024 };
1025 
1026 struct oal {
1027     struct oal_entry oal_entry[5];
1028 };
1029 
1030 struct map_list {
1031     DEFINE_DMA_UNMAP_ADDR(mapaddr);
1032     DEFINE_DMA_UNMAP_LEN(maplen);
1033 };
1034 
1035 struct ql_tx_buf_cb {
1036     struct sk_buff *skb;
1037     struct ob_mac_iocb_req *queue_entry ;
1038     int seg_count;
1039     struct oal *oal;
1040     struct map_list map[MAX_SKB_FRAGS+1];
1041 };
1042 
1043 /* definitions for type field */
1044 #define QL_BUF_TYPE_MACIOCB 0x01
1045 #define QL_BUF_TYPE_IPIOCB  0x02
1046 #define QL_BUF_TYPE_TCPIOCB 0x03
1047 
1048 /* qdev->flags definitions. */
1049 enum { QL_RESET_DONE = 1,   /* Reset finished. */
1050     QL_RESET_ACTIVE = 2,    /* Waiting for reset to finish. */
1051     QL_RESET_START = 3, /* Please reset the chip. */
1052     QL_RESET_PER_SCSI = 4,  /* SCSI driver requests reset. */
1053     QL_TX_TIMEOUT = 5,  /* Timeout in progress. */
1054     QL_LINK_MASTER = 6, /* This driver controls the link. */
1055     QL_ADAPTER_UP = 7,  /* Adapter has been brought up. */
1056     QL_THREAD_UP = 8,   /* This flag is available. */
1057     QL_LINK_UP = 9, /* Link Status. */
1058     QL_ALLOC_REQ_RSP_Q_DONE = 10,
1059     QL_ALLOC_BUFQS_DONE = 11,
1060     QL_ALLOC_SMALL_BUF_DONE = 12,
1061     QL_LINK_OPTICAL = 13,
1062     QL_MSI_ENABLED = 14,
1063 };
1064 
1065 /*
1066  * ql3_adapter - The main Adapter structure definition.
1067  * This structure has all fields relevant to the hardware.
1068  */
1069 
1070 struct ql3_adapter {
1071     u32 reserved_00;
1072     unsigned long flags;
1073 
1074     /* PCI Configuration information for this device */
1075     struct pci_dev *pdev;
1076     struct net_device *ndev;    /* Parent NET device */
1077 
1078     struct napi_struct napi;
1079 
1080     /* Hardware information */
1081     u8 chip_rev_id;
1082     u8 pci_slot;
1083     u8 pci_width;
1084     u8 pci_x;
1085     u32 msi;
1086     int index;
1087     struct timer_list adapter_timer;    /* timer used for various functions */
1088 
1089     spinlock_t adapter_lock;
1090     spinlock_t hw_lock;
1091 
1092     /* PCI Bus Relative Register Addresses */
1093     u8 __iomem *mmap_virt_base; /* stores return value from ioremap() */
1094     struct ql3xxx_port_registers __iomem *mem_map_registers;
1095     u32 current_page;   /* tracks current register page */
1096 
1097     u32 msg_enable;
1098     u8 reserved_01[2];
1099     u8 reserved_02[2];
1100 
1101     /* Page for Shadow Registers */
1102     void *shadow_reg_virt_addr;
1103     dma_addr_t shadow_reg_phy_addr;
1104 
1105     /* Net Request Queue */
1106     u32 req_q_size;
1107     u32 reserved_03;
1108     struct ob_mac_iocb_req *req_q_virt_addr;
1109     dma_addr_t req_q_phy_addr;
1110     u16 req_producer_index;
1111     u16 reserved_04;
1112     u16 *preq_consumer_index;
1113     u32 req_consumer_index_phy_addr_high;
1114     u32 req_consumer_index_phy_addr_low;
1115     atomic_t tx_count;
1116     struct ql_tx_buf_cb tx_buf[NUM_REQ_Q_ENTRIES];
1117 
1118     /* Net Response Queue */
1119     u32 rsp_q_size;
1120     u32 eeprom_cmd_data;
1121     struct net_rsp_iocb *rsp_q_virt_addr;
1122     dma_addr_t rsp_q_phy_addr;
1123     struct net_rsp_iocb *rsp_current;
1124     u16 rsp_consumer_index;
1125     u16 reserved_06;
1126     volatile __le32 *prsp_producer_index;
1127     u32 rsp_producer_index_phy_addr_high;
1128     u32 rsp_producer_index_phy_addr_low;
1129 
1130     /* Large Buffer Queue */
1131     u32 lrg_buf_q_alloc_size;
1132     u32 lrg_buf_q_size;
1133     void *lrg_buf_q_alloc_virt_addr;
1134     void *lrg_buf_q_virt_addr;
1135     dma_addr_t lrg_buf_q_alloc_phy_addr;
1136     dma_addr_t lrg_buf_q_phy_addr;
1137     u32 lrg_buf_q_producer_index;
1138     u32 lrg_buf_release_cnt;
1139     struct bufq_addr_element *lrg_buf_next_free;
1140     u32 num_large_buffers;
1141     u32 num_lbufq_entries;
1142 
1143     /* Large (Receive) Buffers */
1144     struct ql_rcv_buf_cb *lrg_buf;
1145     struct ql_rcv_buf_cb *lrg_buf_free_head;
1146     struct ql_rcv_buf_cb *lrg_buf_free_tail;
1147     u32 lrg_buf_free_count;
1148     u32 lrg_buffer_len;
1149     u32 lrg_buf_index;
1150     u32 lrg_buf_skb_check;
1151 
1152     /* Small Buffer Queue */
1153     u32 small_buf_q_alloc_size;
1154     u32 small_buf_q_size;
1155     u32 small_buf_q_producer_index;
1156     void *small_buf_q_alloc_virt_addr;
1157     void *small_buf_q_virt_addr;
1158     dma_addr_t small_buf_q_alloc_phy_addr;
1159     dma_addr_t small_buf_q_phy_addr;
1160     u32 small_buf_index;
1161 
1162     /* Small (Receive) Buffers */
1163     void *small_buf_virt_addr;
1164     dma_addr_t small_buf_phy_addr;
1165     u32 small_buf_phy_addr_low;
1166     u32 small_buf_phy_addr_high;
1167     u32 small_buf_release_cnt;
1168     u32 small_buf_total_size;
1169 
1170     struct eeprom_data nvram_data;
1171     u32 port_link_state;
1172 
1173     /* 4022 specific */
1174     u32 mac_index;      /* Driver's MAC number can be 0 or 1 for first and second networking functions respectively */
1175     u32 PHYAddr;        /* Address of PHY 0x1e00 Port 0 and 0x1f00 Port 1 */
1176     u32 mac_ob_opcode;  /* Opcode to use on mac transmission */
1177     u32 mb_bit_mask;    /* MA Bits mask to use on transmission */
1178     u32 numPorts;
1179     struct workqueue_struct *workqueue;
1180     struct delayed_work reset_work;
1181     struct delayed_work tx_timeout_work;
1182     struct delayed_work link_state_work;
1183     u32 max_frame_size;
1184     u32 device_id;
1185     u16 phyType;
1186 };
1187 
1188 #endif              /* _QLA3XXX_H_ */
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