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0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
0002 /* QLogic qede NIC Driver
0003  * Copyright (c) 2015-2017  QLogic Corporation
0004  * Copyright (c) 2019-2020 Marvell International Ltd.
0005  */
0006 
0007 #include "qede_ptp.h"
0008 #define QEDE_PTP_TX_TIMEOUT (2 * HZ)
0009 
0010 struct qede_ptp {
0011     const struct qed_eth_ptp_ops    *ops;
0012     struct ptp_clock_info       clock_info;
0013     struct cyclecounter     cc;
0014     struct timecounter      tc;
0015     struct ptp_clock        *clock;
0016     struct work_struct      work;
0017     unsigned long           ptp_tx_start;
0018     struct qede_dev         *edev;
0019     struct sk_buff          *tx_skb;
0020 
0021     /* ptp spinlock is used for protecting the cycle/time counter fields
0022      * and, also for serializing the qed PTP API invocations.
0023      */
0024     spinlock_t          lock;
0025     bool                hw_ts_ioctl_called;
0026     u16             tx_type;
0027     u16             rx_filter;
0028 };
0029 
0030 /**
0031  * qede_ptp_adjfreq() - Adjust the frequency of the PTP cycle counter.
0032  *
0033  * @info: The PTP clock info structure.
0034  * @ppb: Parts per billion adjustment from base.
0035  *
0036  * Return: Zero on success, negative errno otherwise.
0037  */
0038 static int qede_ptp_adjfreq(struct ptp_clock_info *info, s32 ppb)
0039 {
0040     struct qede_ptp *ptp = container_of(info, struct qede_ptp, clock_info);
0041     struct qede_dev *edev = ptp->edev;
0042     int rc;
0043 
0044     __qede_lock(edev);
0045     if (edev->state == QEDE_STATE_OPEN) {
0046         spin_lock_bh(&ptp->lock);
0047         rc = ptp->ops->adjfreq(edev->cdev, ppb);
0048         spin_unlock_bh(&ptp->lock);
0049     } else {
0050         DP_ERR(edev, "PTP adjfreq called while interface is down\n");
0051         rc = -EFAULT;
0052     }
0053     __qede_unlock(edev);
0054 
0055     return rc;
0056 }
0057 
0058 static int qede_ptp_adjtime(struct ptp_clock_info *info, s64 delta)
0059 {
0060     struct qede_dev *edev;
0061     struct qede_ptp *ptp;
0062 
0063     ptp = container_of(info, struct qede_ptp, clock_info);
0064     edev = ptp->edev;
0065 
0066     DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP adjtime called, delta = %llx\n",
0067            delta);
0068 
0069     spin_lock_bh(&ptp->lock);
0070     timecounter_adjtime(&ptp->tc, delta);
0071     spin_unlock_bh(&ptp->lock);
0072 
0073     return 0;
0074 }
0075 
0076 static int qede_ptp_gettime(struct ptp_clock_info *info, struct timespec64 *ts)
0077 {
0078     struct qede_dev *edev;
0079     struct qede_ptp *ptp;
0080     u64 ns;
0081 
0082     ptp = container_of(info, struct qede_ptp, clock_info);
0083     edev = ptp->edev;
0084 
0085     spin_lock_bh(&ptp->lock);
0086     ns = timecounter_read(&ptp->tc);
0087     spin_unlock_bh(&ptp->lock);
0088 
0089     DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP gettime called, ns = %llu\n", ns);
0090 
0091     *ts = ns_to_timespec64(ns);
0092 
0093     return 0;
0094 }
0095 
0096 static int qede_ptp_settime(struct ptp_clock_info *info,
0097                 const struct timespec64 *ts)
0098 {
0099     struct qede_dev *edev;
0100     struct qede_ptp *ptp;
0101     u64 ns;
0102 
0103     ptp = container_of(info, struct qede_ptp, clock_info);
0104     edev = ptp->edev;
0105 
0106     ns = timespec64_to_ns(ts);
0107 
0108     DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP settime called, ns = %llu\n", ns);
0109 
0110     /* Re-init the timecounter */
0111     spin_lock_bh(&ptp->lock);
0112     timecounter_init(&ptp->tc, &ptp->cc, ns);
0113     spin_unlock_bh(&ptp->lock);
0114 
0115     return 0;
0116 }
0117 
0118 /* Enable (or disable) ancillary features of the phc subsystem */
0119 static int qede_ptp_ancillary_feature_enable(struct ptp_clock_info *info,
0120                          struct ptp_clock_request *rq,
0121                          int on)
0122 {
0123     struct qede_dev *edev;
0124     struct qede_ptp *ptp;
0125 
0126     ptp = container_of(info, struct qede_ptp, clock_info);
0127     edev = ptp->edev;
0128 
0129     DP_ERR(edev, "PHC ancillary features are not supported\n");
0130 
0131     return -ENOTSUPP;
0132 }
0133 
0134 static void qede_ptp_task(struct work_struct *work)
0135 {
0136     struct skb_shared_hwtstamps shhwtstamps;
0137     struct qede_dev *edev;
0138     struct qede_ptp *ptp;
0139     u64 timestamp, ns;
0140     bool timedout;
0141     int rc;
0142 
0143     ptp = container_of(work, struct qede_ptp, work);
0144     edev = ptp->edev;
0145     timedout = time_is_before_jiffies(ptp->ptp_tx_start +
0146                       QEDE_PTP_TX_TIMEOUT);
0147 
0148     /* Read Tx timestamp registers */
0149     spin_lock_bh(&ptp->lock);
0150     rc = ptp->ops->read_tx_ts(edev->cdev, &timestamp);
0151     spin_unlock_bh(&ptp->lock);
0152     if (rc) {
0153         if (unlikely(timedout)) {
0154             DP_INFO(edev, "Tx timestamp is not recorded\n");
0155             dev_kfree_skb_any(ptp->tx_skb);
0156             ptp->tx_skb = NULL;
0157             clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS,
0158                      &edev->flags);
0159             edev->ptp_skip_txts++;
0160         } else {
0161             /* Reschedule to keep checking for a valid TS value */
0162             schedule_work(&ptp->work);
0163         }
0164         return;
0165     }
0166 
0167     ns = timecounter_cyc2time(&ptp->tc, timestamp);
0168     memset(&shhwtstamps, 0, sizeof(shhwtstamps));
0169     shhwtstamps.hwtstamp = ns_to_ktime(ns);
0170     skb_tstamp_tx(ptp->tx_skb, &shhwtstamps);
0171     dev_kfree_skb_any(ptp->tx_skb);
0172     ptp->tx_skb = NULL;
0173     clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
0174 
0175     DP_VERBOSE(edev, QED_MSG_DEBUG,
0176            "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
0177            timestamp, ns);
0178 }
0179 
0180 /* Read the PHC. This API is invoked with ptp_lock held. */
0181 static u64 qede_ptp_read_cc(const struct cyclecounter *cc)
0182 {
0183     struct qede_dev *edev;
0184     struct qede_ptp *ptp;
0185     u64 phc_cycles;
0186     int rc;
0187 
0188     ptp = container_of(cc, struct qede_ptp, cc);
0189     edev = ptp->edev;
0190     rc = ptp->ops->read_cc(edev->cdev, &phc_cycles);
0191     if (rc)
0192         WARN_ONCE(1, "PHC read err %d\n", rc);
0193 
0194     DP_VERBOSE(edev, QED_MSG_DEBUG, "PHC read cycles = %llu\n", phc_cycles);
0195 
0196     return phc_cycles;
0197 }
0198 
0199 static int qede_ptp_cfg_filters(struct qede_dev *edev)
0200 {
0201     enum qed_ptp_hwtstamp_tx_type tx_type = QED_PTP_HWTSTAMP_TX_ON;
0202     enum qed_ptp_filter_type rx_filter = QED_PTP_FILTER_NONE;
0203     struct qede_ptp *ptp = edev->ptp;
0204 
0205     if (!ptp)
0206         return -EIO;
0207 
0208     if (!ptp->hw_ts_ioctl_called) {
0209         DP_INFO(edev, "TS IOCTL not called\n");
0210         return 0;
0211     }
0212 
0213     switch (ptp->tx_type) {
0214     case HWTSTAMP_TX_ON:
0215         set_bit(QEDE_FLAGS_TX_TIMESTAMPING_EN, &edev->flags);
0216         tx_type = QED_PTP_HWTSTAMP_TX_ON;
0217         break;
0218 
0219     case HWTSTAMP_TX_OFF:
0220         clear_bit(QEDE_FLAGS_TX_TIMESTAMPING_EN, &edev->flags);
0221         tx_type = QED_PTP_HWTSTAMP_TX_OFF;
0222         break;
0223 
0224     case HWTSTAMP_TX_ONESTEP_SYNC:
0225     case HWTSTAMP_TX_ONESTEP_P2P:
0226         DP_ERR(edev, "One-step timestamping is not supported\n");
0227         return -ERANGE;
0228     }
0229 
0230     spin_lock_bh(&ptp->lock);
0231     switch (ptp->rx_filter) {
0232     case HWTSTAMP_FILTER_NONE:
0233         rx_filter = QED_PTP_FILTER_NONE;
0234         break;
0235     case HWTSTAMP_FILTER_ALL:
0236     case HWTSTAMP_FILTER_SOME:
0237     case HWTSTAMP_FILTER_NTP_ALL:
0238         ptp->rx_filter = HWTSTAMP_FILTER_NONE;
0239         rx_filter = QED_PTP_FILTER_ALL;
0240         break;
0241     case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
0242         ptp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
0243         rx_filter = QED_PTP_FILTER_V1_L4_EVENT;
0244         break;
0245     case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
0246     case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
0247         ptp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
0248         /* Initialize PTP detection for UDP/IPv4 events */
0249         rx_filter = QED_PTP_FILTER_V1_L4_GEN;
0250         break;
0251     case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
0252         ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
0253         rx_filter = QED_PTP_FILTER_V2_L4_EVENT;
0254         break;
0255     case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
0256     case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
0257         ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
0258         /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
0259         rx_filter = QED_PTP_FILTER_V2_L4_GEN;
0260         break;
0261     case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
0262         ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
0263         rx_filter = QED_PTP_FILTER_V2_L2_EVENT;
0264         break;
0265     case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
0266     case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
0267         ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
0268         /* Initialize PTP detection L2 events */
0269         rx_filter = QED_PTP_FILTER_V2_L2_GEN;
0270         break;
0271     case HWTSTAMP_FILTER_PTP_V2_EVENT:
0272         ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
0273         rx_filter = QED_PTP_FILTER_V2_EVENT;
0274         break;
0275     case HWTSTAMP_FILTER_PTP_V2_SYNC:
0276     case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
0277         ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
0278         /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
0279         rx_filter = QED_PTP_FILTER_V2_GEN;
0280         break;
0281     }
0282 
0283     ptp->ops->cfg_filters(edev->cdev, rx_filter, tx_type);
0284 
0285     spin_unlock_bh(&ptp->lock);
0286 
0287     return 0;
0288 }
0289 
0290 int qede_ptp_hw_ts(struct qede_dev *edev, struct ifreq *ifr)
0291 {
0292     struct hwtstamp_config config;
0293     struct qede_ptp *ptp;
0294     int rc;
0295 
0296     ptp = edev->ptp;
0297     if (!ptp)
0298         return -EIO;
0299 
0300     if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
0301         return -EFAULT;
0302 
0303     DP_VERBOSE(edev, QED_MSG_DEBUG,
0304            "HWTSTAMP IOCTL: Requested tx_type = %d, requested rx_filters = %d\n",
0305            config.tx_type, config.rx_filter);
0306 
0307     ptp->hw_ts_ioctl_called = 1;
0308     ptp->tx_type = config.tx_type;
0309     ptp->rx_filter = config.rx_filter;
0310 
0311     rc = qede_ptp_cfg_filters(edev);
0312     if (rc)
0313         return rc;
0314 
0315     config.rx_filter = ptp->rx_filter;
0316 
0317     return copy_to_user(ifr->ifr_data, &config,
0318                 sizeof(config)) ? -EFAULT : 0;
0319 }
0320 
0321 int qede_ptp_get_ts_info(struct qede_dev *edev, struct ethtool_ts_info *info)
0322 {
0323     struct qede_ptp *ptp = edev->ptp;
0324 
0325     if (!ptp) {
0326         info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
0327                     SOF_TIMESTAMPING_RX_SOFTWARE |
0328                     SOF_TIMESTAMPING_SOFTWARE;
0329         info->phc_index = -1;
0330 
0331         return 0;
0332     }
0333 
0334     info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
0335                 SOF_TIMESTAMPING_RX_SOFTWARE |
0336                 SOF_TIMESTAMPING_SOFTWARE |
0337                 SOF_TIMESTAMPING_TX_HARDWARE |
0338                 SOF_TIMESTAMPING_RX_HARDWARE |
0339                 SOF_TIMESTAMPING_RAW_HARDWARE;
0340 
0341     if (ptp->clock)
0342         info->phc_index = ptp_clock_index(ptp->clock);
0343     else
0344         info->phc_index = -1;
0345 
0346     info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
0347                BIT(HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
0348                BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
0349                BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
0350                BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
0351                BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
0352                BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
0353                BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
0354                BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
0355                BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
0356                BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
0357                BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) |
0358                BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
0359 
0360     info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
0361 
0362     return 0;
0363 }
0364 
0365 void qede_ptp_disable(struct qede_dev *edev)
0366 {
0367     struct qede_ptp *ptp;
0368 
0369     ptp = edev->ptp;
0370     if (!ptp)
0371         return;
0372 
0373     if (ptp->clock) {
0374         ptp_clock_unregister(ptp->clock);
0375         ptp->clock = NULL;
0376     }
0377 
0378     /* Cancel PTP work queue. Should be done after the Tx queues are
0379      * drained to prevent additional scheduling.
0380      */
0381     cancel_work_sync(&ptp->work);
0382     if (ptp->tx_skb) {
0383         dev_kfree_skb_any(ptp->tx_skb);
0384         ptp->tx_skb = NULL;
0385         clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
0386     }
0387 
0388     /* Disable PTP in HW */
0389     spin_lock_bh(&ptp->lock);
0390     ptp->ops->disable(edev->cdev);
0391     spin_unlock_bh(&ptp->lock);
0392 
0393     kfree(ptp);
0394     edev->ptp = NULL;
0395 }
0396 
0397 static int qede_ptp_init(struct qede_dev *edev)
0398 {
0399     struct qede_ptp *ptp;
0400     int rc;
0401 
0402     ptp = edev->ptp;
0403     if (!ptp)
0404         return -EINVAL;
0405 
0406     spin_lock_init(&ptp->lock);
0407 
0408     /* Configure PTP in HW */
0409     rc = ptp->ops->enable(edev->cdev);
0410     if (rc) {
0411         DP_INFO(edev, "PTP HW enable failed\n");
0412         return rc;
0413     }
0414 
0415     /* Init work queue for Tx timestamping */
0416     INIT_WORK(&ptp->work, qede_ptp_task);
0417 
0418     /* Init cyclecounter and timecounter */
0419     memset(&ptp->cc, 0, sizeof(ptp->cc));
0420     ptp->cc.read = qede_ptp_read_cc;
0421     ptp->cc.mask = CYCLECOUNTER_MASK(64);
0422     ptp->cc.shift = 0;
0423     ptp->cc.mult = 1;
0424 
0425     timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));
0426 
0427     return 0;
0428 }
0429 
0430 int qede_ptp_enable(struct qede_dev *edev)
0431 {
0432     struct qede_ptp *ptp;
0433     int rc;
0434 
0435     ptp = kzalloc(sizeof(*ptp), GFP_KERNEL);
0436     if (!ptp) {
0437         DP_INFO(edev, "Failed to allocate struct for PTP\n");
0438         return -ENOMEM;
0439     }
0440 
0441     ptp->edev = edev;
0442     ptp->ops = edev->ops->ptp;
0443     if (!ptp->ops) {
0444         DP_INFO(edev, "PTP enable failed\n");
0445         rc = -EIO;
0446         goto err1;
0447     }
0448 
0449     edev->ptp = ptp;
0450 
0451     rc = qede_ptp_init(edev);
0452     if (rc)
0453         goto err1;
0454 
0455     qede_ptp_cfg_filters(edev);
0456 
0457     /* Fill the ptp_clock_info struct and register PTP clock */
0458     ptp->clock_info.owner = THIS_MODULE;
0459     snprintf(ptp->clock_info.name, 16, "%s", edev->ndev->name);
0460     ptp->clock_info.max_adj = QED_MAX_PHC_DRIFT_PPB;
0461     ptp->clock_info.n_alarm = 0;
0462     ptp->clock_info.n_ext_ts = 0;
0463     ptp->clock_info.n_per_out = 0;
0464     ptp->clock_info.pps = 0;
0465     ptp->clock_info.adjfreq = qede_ptp_adjfreq;
0466     ptp->clock_info.adjtime = qede_ptp_adjtime;
0467     ptp->clock_info.gettime64 = qede_ptp_gettime;
0468     ptp->clock_info.settime64 = qede_ptp_settime;
0469     ptp->clock_info.enable = qede_ptp_ancillary_feature_enable;
0470 
0471     ptp->clock = ptp_clock_register(&ptp->clock_info, &edev->pdev->dev);
0472     if (IS_ERR(ptp->clock)) {
0473         DP_ERR(edev, "PTP clock registration failed\n");
0474         qede_ptp_disable(edev);
0475         rc = -EINVAL;
0476         goto err2;
0477     }
0478 
0479     return 0;
0480 
0481 err1:
0482     kfree(ptp);
0483 err2:
0484     edev->ptp = NULL;
0485 
0486     return rc;
0487 }
0488 
0489 void qede_ptp_tx_ts(struct qede_dev *edev, struct sk_buff *skb)
0490 {
0491     struct qede_ptp *ptp;
0492 
0493     ptp = edev->ptp;
0494     if (!ptp)
0495         return;
0496 
0497     if (test_and_set_bit_lock(QEDE_FLAGS_PTP_TX_IN_PRORGESS,
0498                   &edev->flags)) {
0499         DP_VERBOSE(edev, QED_MSG_DEBUG, "Timestamping in progress\n");
0500         edev->ptp_skip_txts++;
0501         return;
0502     }
0503 
0504     if (unlikely(!test_bit(QEDE_FLAGS_TX_TIMESTAMPING_EN, &edev->flags))) {
0505         DP_VERBOSE(edev, QED_MSG_DEBUG,
0506                "Tx timestamping was not enabled, this pkt will not be timestamped\n");
0507         clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
0508         edev->ptp_skip_txts++;
0509     } else if (unlikely(ptp->tx_skb)) {
0510         DP_VERBOSE(edev, QED_MSG_DEBUG,
0511                "Device supports a single outstanding pkt to ts, It will not be ts\n");
0512         clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
0513         edev->ptp_skip_txts++;
0514     } else {
0515         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
0516         /* schedule check for Tx timestamp */
0517         ptp->tx_skb = skb_get(skb);
0518         ptp->ptp_tx_start = jiffies;
0519         schedule_work(&ptp->work);
0520     }
0521 }
0522 
0523 void qede_ptp_rx_ts(struct qede_dev *edev, struct sk_buff *skb)
0524 {
0525     struct qede_ptp *ptp;
0526     u64 timestamp, ns;
0527     int rc;
0528 
0529     ptp = edev->ptp;
0530     if (!ptp)
0531         return;
0532 
0533     spin_lock_bh(&ptp->lock);
0534     rc = ptp->ops->read_rx_ts(edev->cdev, &timestamp);
0535     if (rc) {
0536         spin_unlock_bh(&ptp->lock);
0537         DP_INFO(edev, "Invalid Rx timestamp\n");
0538         return;
0539     }
0540 
0541     ns = timecounter_cyc2time(&ptp->tc, timestamp);
0542     spin_unlock_bh(&ptp->lock);
0543     skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
0544     DP_VERBOSE(edev, QED_MSG_DEBUG,
0545            "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
0546            timestamp, ns);
0547 }
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